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| author | Heiko Stuebner <heiko.stuebner@cherry.de> | 2023-12-06 15:50:41 +0100 |
|---|---|---|
| committer | Krzysztof Wilczyński <kwilczynski@kernel.org> | 2023-12-16 00:06:29 +0000 |
| commit | 639f666cf84e9192ef2ca0b5d638a258062513b7 (patch) | |
| tree | a8dfe9b615f6f1a26d599978634eee3cb4f7752c | |
| parent | 3b74713a0321de5e4b1507990ef87049f8c887d8 (diff) | |
| download | lwn-639f666cf84e9192ef2ca0b5d638a258062513b7.tar.gz lwn-639f666cf84e9192ef2ca0b5d638a258062513b7.zip | |
dt-bindings: PCI: dwc: rockchip: Document optional PCIe reference clock input
On some boards the 100MHz PCIe reference clock to both controller and
devices is controllable. Add that clock to the list of clocks.
The clock is optional, so the minItems stays the same.
Link: https://lore.kernel.org/linux-pci/20231206145041.667900-1-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 1ae8dcfa072c..5f719218c472 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -49,6 +49,7 @@ properties: - description: APB clock for PCIe - description: Auxiliary clock for PCIe - description: PIPE clock + - description: Reference clock for PCIe clock-names: minItems: 5 @@ -59,6 +60,7 @@ properties: - const: pclk - const: aux - const: pipe + - const: ref interrupts: items: |