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authorFei Shao <fshao@chromium.org>2024-09-25 18:57:46 +0800
committerBjorn Helgaas <bhelgaas@google.com>2024-10-02 15:29:34 -0500
commit5efa23224bf573d4bceb51bc646dd67b6ccb83b5 (patch)
tree3b692ac93010d3793baba0adbc518094864a2a40
parent9852d85ec9d492ebef56dc5f229416c925758edc (diff)
downloadlwn-5efa23224bf573d4bceb51bc646dd67b6ccb83b5.tar.gz
lwn-5efa23224bf573d4bceb51bc646dd67b6ccb83b5.zip
dt-bindings: PCI: mediatek-gen3: Allow exact number of clocks only
In MediaTek PCIe gen3 bindings, "clocks" accepts a range of 1-6 clocks across all SoCs. But in practice, each SoC requires a particular number of clocks as defined in "clock-names", and the length of "clocks" and "clock-names" can be inconsistent with current bindings. For example: - MT8188, MT8192 and MT8195 all require 6 clocks, while the bindings accept 4-6 clocks. - MT7986 requires 4 clocks, while the bindings accept 4-6 clocks. Update minItems and maxItems properties for individual SoCs as needed to only accept the correct number of clocks. Fixes: c6abd0eadec6 ("dt-bindings: PCI: mediatek-gen3: Add support for Airoha EN7581") Link: https://lore.kernel.org/r/20240925110044.3678055-3-fshao@chromium.org Signed-off-by: Fei Shao <fshao@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml5
1 files changed, 3 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
index 898c1be2d6a4..f05aab2b1add 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -149,7 +149,7 @@ allOf:
then:
properties:
clocks:
- minItems: 4
+ minItems: 6
clock-names:
items:
@@ -178,7 +178,7 @@ allOf:
then:
properties:
clocks:
- minItems: 4
+ minItems: 6
clock-names:
items:
@@ -207,6 +207,7 @@ allOf:
properties:
clocks:
minItems: 4
+ maxItems: 4
clock-names:
items: