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| author | Rajendra Nayak <rnayak@ti.com> | 2012-05-07 23:55:21 -0600 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2012-05-07 23:55:21 -0600 |
| commit | 4e68f5a79da5b595fc40ceff5ebcfa3e6637bf37 (patch) | |
| tree | 1756942d86be26b7790a7fb825e816708f5b197d | |
| parent | 96566043b19ae76d3828ce75cbf28dc6d0bcaaf1 (diff) | |
| download | lwn-4e68f5a79da5b595fc40ceff5ebcfa3e6637bf37.tar.gz lwn-4e68f5a79da5b595fc40ceff5ebcfa3e6637bf37.zip | |
ARM: OMAP3: Fix CM register bit masks
The register bits for MPU_CLK_SRC and IVA2_CLK_SRC in CM_CLKSEL1_PLL
register are 3 bits wide. Fix the MASK definition accordingly.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-34xx.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index b91275908f33..8083a8cdc55f 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -79,7 +79,7 @@ /* CM_CLKSEL1_PLL_IVA2 */ #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 -#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) +#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19) #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 @@ -124,7 +124,7 @@ /* CM_CLKSEL1_PLL_MPU */ #define OMAP3430_MPU_CLK_SRC_SHIFT 19 -#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) +#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19) #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 |