diff options
| author | Sean Nyekjaer <sean@geanix.com> | 2023-06-02 08:24:25 +0200 |
|---|---|---|
| committer | Lee Jones <lee@kernel.org> | 2023-06-15 09:19:39 +0100 |
| commit | 48b4371b98676e8db3f72e4355af7707103d9c07 (patch) | |
| tree | d9dc61eb0321664e90f60612568298e58002b31b | |
| parent | 2ce68cf10081f906f29a1ad9027c2bcfc2f8465d (diff) | |
| download | lwn-48b4371b98676e8db3f72e4355af7707103d9c07.tar.gz lwn-48b4371b98676e8db3f72e4355af7707103d9c07.zip | |
mfd: stpmic1: Fixup main control register and bits naming
Fixup main control register and bits naming so the match the naming from
the datasheet.
https://www.st.com/resource/en/datasheet/stpmic1.pdf
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20230602062426.3947116-1-sean@geanix.com
| -rw-r--r-- | drivers/mfd/stpmic1.c | 4 | ||||
| -rw-r--r-- | include/linux/mfd/stpmic1.h | 12 |
2 files changed, 8 insertions, 8 deletions
diff --git a/drivers/mfd/stpmic1.c b/drivers/mfd/stpmic1.c index d0ff46961910..a79dfb9923d7 100644 --- a/drivers/mfd/stpmic1.c +++ b/drivers/mfd/stpmic1.c @@ -19,7 +19,7 @@ static const struct regmap_range stpmic1_readable_ranges[] = { regmap_reg_range(TURN_ON_SR, VERSION_SR), - regmap_reg_range(SWOFF_PWRCTRL_CR, LDO6_STDBY_CR), + regmap_reg_range(MAIN_CR, LDO6_STDBY_CR), regmap_reg_range(BST_SW_CR, BST_SW_CR), regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4), regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4), @@ -30,7 +30,7 @@ static const struct regmap_range stpmic1_readable_ranges[] = { }; static const struct regmap_range stpmic1_writeable_ranges[] = { - regmap_reg_range(SWOFF_PWRCTRL_CR, LDO6_STDBY_CR), + regmap_reg_range(MAIN_CR, LDO6_STDBY_CR), regmap_reg_range(BST_SW_CR, BST_SW_CR), regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4), regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4), diff --git a/include/linux/mfd/stpmic1.h b/include/linux/mfd/stpmic1.h index fa3f99f7e9a1..dc00bac24f5a 100644 --- a/include/linux/mfd/stpmic1.h +++ b/include/linux/mfd/stpmic1.h @@ -15,7 +15,7 @@ #define RREQ_STATE_SR 0x5 #define VERSION_SR 0x6 -#define SWOFF_PWRCTRL_CR 0x10 +#define MAIN_CR 0x10 #define PADS_PULL_CR 0x11 #define BUCKS_PD_CR 0x12 #define LDO14_PD_CR 0x13 @@ -148,14 +148,14 @@ #define LDO_BYPASS_MASK BIT(7) /* Main PMIC Control Register - * SWOFF_PWRCTRL_CR + * MAIN_CR * Address : 0x10 */ -#define ICC_EVENT_ENABLED BIT(4) +#define OCP_OFF_DBG BIT(4) #define PWRCTRL_POLARITY_HIGH BIT(3) -#define PWRCTRL_PIN_VALID BIT(2) -#define RESTART_REQUEST_ENABLED BIT(1) -#define SOFTWARE_SWITCH_OFF_ENABLED BIT(0) +#define PWRCTRL_ENABLE BIT(2) +#define RESTART_REQUEST_ENABLE BIT(1) +#define SOFTWARE_SWITCH_OFF BIT(0) /* Main PMIC PADS Control Register * PADS_PULL_CR |