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author | Vineet Gupta <vgupta@synopsys.com> | 2015-11-05 09:13:31 +0530 |
---|---|---|
committer | Willy Tarreau <w@1wt.eu> | 2016-08-27 11:40:31 +0200 |
commit | 46d597e212135b8cd6d4752babcfad8f1669dbc1 (patch) | |
tree | b0ecefeac3d96aa6aa7abf080e1aaf92adb4e6ba | |
parent | e5201134028bd04d5f0fb020a2579605b61a3078 (diff) | |
download | lwn-46d597e212135b8cd6d4752babcfad8f1669dbc1.tar.gz lwn-46d597e212135b8cd6d4752babcfad8f1669dbc1.zip |
ARC: use ASL assembler mnemonic
commit a6416f57ce57fb390b6ee30b12c01c29032a26af upstream.
ARCompact and ARCv2 only have ASL, while binutils used to support LSL as
a alias mnemonic.
Newer binutils (upstream) don't want to do that so replace it.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Willy Tarreau <w@1wt.eu>
-rw-r--r-- | arch/arc/mm/tlbex.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S index 3357d26ffe54..74691e652a3a 100644 --- a/arch/arc/mm/tlbex.S +++ b/arch/arc/mm/tlbex.S @@ -219,7 +219,7 @@ ex_saved_reg1: #ifdef CONFIG_SMP sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with GET_CPU_ID r0 ; get to per cpu scratch mem, - lsl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu + asl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu add r0, @ex_saved_reg1, r0 #else st r0, [@ex_saved_reg1] @@ -239,7 +239,7 @@ ex_saved_reg1: .macro TLBMISS_RESTORE_REGS #ifdef CONFIG_SMP GET_CPU_ID r0 ; get to per cpu scratch mem - lsl r0, r0, L1_CACHE_SHIFT ; each is cache line wide + asl r0, r0, L1_CACHE_SHIFT ; each is cache line wide add r0, @ex_saved_reg1, r0 ld_s r3, [r0,12] ld_s r2, [r0, 8] |