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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-05-31 15:47:35 +0300 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-06-25 22:29:22 -0500 |
| commit | 3ba500dee327e0261e728edec8a4f2f563d2760c (patch) | |
| tree | 22d9e7d9c7541c1dcad78ad7c8126eb23f326a18 | |
| parent | fc8b0b9b630df6de7415f527fe27c0c441b5dc70 (diff) | |
| download | lwn-3ba500dee327e0261e728edec8a4f2f563d2760c.tar.gz lwn-3ba500dee327e0261e728edec8a4f2f563d2760c.zip | |
arm64: dts: qcom: sdm845: use dispcc AHB clock for mdss node
It was noticed that on sdm845 after an MDSS suspend/resume cycle the
driver can not read HW_REV registers properly (they will return 0
instead). Chaning the "iface" clock from <&gcc GCC_DISP_AHB_CLK> to
<&dispcc DISP_CC_MDSS_AHB_CLK> fixes the issue.
Fixes: 08c2a076d18f ("arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220531124735.1165582-1-dmitry.baryshkov@linaro.org
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0692ae0e60a4..038538c8c614 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4244,7 +4244,7 @@ power-domains = <&dispcc MDSS_GDSC>; - clocks = <&gcc GCC_DISP_AHB_CLK>, + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "core"; |