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| author | Sebastian Reichel <sebastian.reichel@collabora.com> | 2023-06-16 19:00:21 +0200 |
|---|---|---|
| committer | Rob Herring <robh@kernel.org> | 2023-06-27 07:54:00 -0600 |
| commit | 3216ceeb708b816ffacb19ae2387ac68bb872631 (patch) | |
| tree | 86da85177e8422b08c21ab439b3c44a10766ae64 | |
| parent | 74f02dd73906f5a0e48dfc39b8f3adc03ad86274 (diff) | |
| download | lwn-3216ceeb708b816ffacb19ae2387ac68bb872631.tar.gz lwn-3216ceeb708b816ffacb19ae2387ac68bb872631.zip | |
dt-bindings: PCI: dwc: rockchip: Update for RK3588
The PCIe 2.0 controllers on RK3588 need one additional clock,
one additional reset line and one for ranges entry.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230616170022.76107-4-sebastian.reichel@collabora.com
Signed-off-by: Rob Herring <robh@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 24c88942e59e..a4f61ced5e88 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -41,20 +41,24 @@ properties: - const: config clocks: + minItems: 5 items: - description: AHB clock for PCIe master - description: AHB clock for PCIe slave - description: AHB clock for PCIe dbi - description: APB clock for PCIe - description: Auxiliary clock for PCIe + - description: PIPE clock clock-names: + minItems: 5 items: - const: aclk_mst - const: aclk_slv - const: aclk_dbi - const: pclk - const: aux + - const: pipe msi-map: true @@ -70,13 +74,19 @@ properties: maxItems: 1 ranges: - maxItems: 2 + minItems: 2 + maxItems: 3 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 reset-names: - const: pipe + oneOf: + - const: pipe + - items: + - const: pwr + - const: pipe vpcie3v3-supply: true |