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| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-03-06 15:05:21 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-03-13 11:50:16 -0700 |
| commit | 2562dc42aec84fc6f263ff4198dea85752c4f703 (patch) | |
| tree | 4d4ca81f8f20e9f5522059e35a58f412bea63ebb | |
| parent | 6b7daeaa7e64151df080208d6636ae433dbe07c1 (diff) | |
| download | lwn-2562dc42aec84fc6f263ff4198dea85752c4f703.tar.gz lwn-2562dc42aec84fc6f263ff4198dea85752c4f703.zip | |
clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set critical clock
Instead of calling clk_prepare_enable() at probe time, add the PLL_AO
flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediatek/clk-mt7986-apmixed.c index 62080ee4dbe3..227ca572056e 100644 --- a/drivers/clk/mediatek/clk-mt7986-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c @@ -42,7 +42,7 @@ "clkxtal") static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32, + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32, 0x0200, 4, 0, 0x0204, 0), PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32, 0x0210, 4, 0, 0x0214, 0), @@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(struct platform_device *pdev) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { pr_err("%s(): could not register clock provider: %d\n", |