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| author | Charlie Jenkins <charlie@rivosinc.com> | 2024-11-08 15:47:36 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-11-12 14:45:26 -0800 |
| commit | 0eb512779d642b21ced83778287a0f7a3ca8f2a1 (patch) | |
| tree | 7f15cdf45952c986d13287acb6c34dcf6d38a309 | |
| parent | 64f7b77f0bd9271861ed9e410e9856b6b0b21c48 (diff) | |
| download | lwn-0eb512779d642b21ced83778287a0f7a3ca8f2a1.tar.gz lwn-0eb512779d642b21ced83778287a0f7a3ca8f2a1.zip | |
riscv: Fix default misaligned access trap
Commit d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses
supported") removed the default handlers for handle_misaligned_load()
and handle_misaligned_store(). When the kernel is compiled without
RISCV_SCALAR_MISALIGNED, these handlers are never defined, causing
compilation errors.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Fixes: d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses supported")
Reviewed-by: Jesse Taube <mr.bossman075@gmail.com>
Link: https://lore.kernel.org/r/20241108-fix_handle_misaligned_load-v2-1-91d547ce64db@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| -rw-r--r-- | arch/riscv/include/asm/entry-common.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h index 7b32d2b08bb6..b28ccc6cdeea 100644 --- a/arch/riscv/include/asm/entry-common.h +++ b/arch/riscv/include/asm/entry-common.h @@ -25,7 +25,19 @@ static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs, void handle_page_fault(struct pt_regs *regs); void handle_break(struct pt_regs *regs); +#ifdef CONFIG_RISCV_MISALIGNED int handle_misaligned_load(struct pt_regs *regs); int handle_misaligned_store(struct pt_regs *regs); +#else +static inline int handle_misaligned_load(struct pt_regs *regs) +{ + return -1; +} + +static inline int handle_misaligned_store(struct pt_regs *regs) +{ + return -1; +} +#endif #endif /* _ASM_RISCV_ENTRY_COMMON_H */ |