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| author | Kan Liang <kan.liang@linux.intel.com> | 2019-10-08 08:50:09 -0700 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2019-10-12 15:13:09 +0200 |
| commit | 0917b95079af82c69d8f5bab301faeebcd2cb3cd (patch) | |
| tree | 58240abdca52e93df0b760beea1fd95aa23a80a9 | |
| parent | 23645a76ba816652d6898def2ee69c6a6250c9b1 (diff) | |
| download | lwn-0917b95079af82c69d8f5bab301faeebcd2cb3cd.tar.gz lwn-0917b95079af82c69d8f5bab301faeebcd2cb3cd.zip | |
perf/x86/msr: Add Tiger Lake CPU support
Tiger Lake is the followon to Ice Lake. PPERF and SMI_COUNT MSRs are
also supported.
The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-9-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
| -rw-r--r-- | arch/x86/events/msr.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 8515512e98ef..6f86650b3f77 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -95,6 +95,8 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_ICELAKE: case INTEL_FAM6_ICELAKE_X: case INTEL_FAM6_ICELAKE_D: + case INTEL_FAM6_TIGERLAKE_L: + case INTEL_FAM6_TIGERLAKE: if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) return true; break; |