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| author | Siddharth Vadapalli <s-vadapalli@ti.com> | 2024-05-24 14:53:49 +0530 |
|---|---|---|
| committer | Krzysztof Wilczyński <kwilczynski@kernel.org> | 2024-11-03 19:11:30 +0000 |
| commit | 08e835268c35e851b308f326357224248cfb445b (patch) | |
| tree | c05afc3b72e83e0bb78550f0e9124a6318b8a2f9 | |
| parent | 9852d85ec9d492ebef56dc5f229416c925758edc (diff) | |
| download | lwn-08e835268c35e851b308f326357224248cfb445b.tar.gz lwn-08e835268c35e851b308f326357224248cfb445b.zip | |
PCI: j721e: Add PCIe support for J722S SoC
TI's J722S SoC has one instance of PCIe namely PCIe0 which is a Gen3
single lane PCIe controller. Add support for the "ti,j722s-pcie-host"
compatible specific to J722S SoC.
Link: https://lore.kernel.org/r/20240524092349.158443-1-s-vadapalli@ti.com
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
| -rw-r--r-- | drivers/pci/controller/cadence/pci-j721e.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 284f2e0e4d26..c9f3103d68e1 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -386,6 +386,13 @@ static const struct j721e_pcie_data j784s4_pcie_ep_data = { .max_lanes = 4, }; +static const struct j721e_pcie_data j722s_pcie_rc_data = { + .mode = PCI_MODE_RC, + .linkdown_irq_regfield = J7200_LINK_DOWN, + .byte_access_allowed = true, + .max_lanes = 1, +}; + static const struct of_device_id of_j721e_pcie_match[] = { { .compatible = "ti,j721e-pcie-host", @@ -419,6 +426,10 @@ static const struct of_device_id of_j721e_pcie_match[] = { .compatible = "ti,j784s4-pcie-ep", .data = &j784s4_pcie_ep_data, }, + { + .compatible = "ti,j722s-pcie-host", + .data = &j722s_pcie_rc_data, + }, {}, }; |