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author | Stephen Boyd <sboyd@codeaurora.org> | 2013-10-31 18:20:30 -0700 |
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committer | Kumar Gala <galak@codeaurora.org> | 2014-02-11 15:00:38 -0600 |
commit | 007290cb3db0bba6a7f441b3dc849b365b0d54b1 (patch) | |
tree | ac70a0544fe5f902bcb5485b55c3e6acc2c790c1 | |
parent | b00c927d06855be4f1aa3d6931cb07fd641c8d8c (diff) | |
download | lwn-007290cb3db0bba6a7f441b3dc849b365b0d54b1.tar.gz lwn-007290cb3db0bba6a7f441b3dc849b365b0d54b1.zip |
devicetree: bindings: Document qcom,kpss-acc
The kpss acc binding describes the clock, reset, and power domain
controller for a Krait CPU.
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
-rw-r--r-- | Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt new file mode 100644 index 000000000000..1333db9acfee --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt @@ -0,0 +1,30 @@ +Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) + +The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. +There is one ACC register region per CPU within the KPSS remapped region as +well as an alias register region that remaps accesses to the ACC associated +with the CPU accessing the region. + +PROPERTIES + +- compatible: + Usage: required + Value type: <string> + Definition: should be one of: + "qcom,kpss-acc-v1" + "qcom,kpss-acc-v2" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the first element specifies the base address and size of + the register region. An optional second element specifies + the base address and size of the alias register region. + +Example: + + clock-controller@2088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x02088000 0x1000>, + <0x02008000 0x1000>; + }; |