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/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2026 Intel Corporation
*/
#ifndef _XE_SYSCTRL_REGS_H_
#define _XE_SYSCTRL_REGS_H_
#include "xe_regs.h"
#define SYSCTRL_BASE_OFFSET 0xdb000
#define SYSCTRL_BASE (SOC_BASE + SYSCTRL_BASE_OFFSET)
#define SYSCTRL_MAILBOX_INDEX 0x03
#define SYSCTRL_BAR_LENGTH 0x1000
#define SYSCTRL_MB_CTRL XE_REG(0x10)
#define SYSCTRL_MB_CTRL_RUN_BUSY REG_BIT(31)
#define SYSCTRL_MB_CTRL_IRQ REG_BIT(30)
#define SYSCTRL_MB_CTRL_RUN_BUSY_OUT REG_BIT(29)
#define SYSCTRL_MB_CTRL_PARAM3_MASK REG_GENMASK(28, 24)
#define SYSCTRL_MB_CTRL_PARAM2_MASK REG_GENMASK(23, 16)
#define SYSCTRL_MB_CTRL_PARAM1_MASK REG_GENMASK(15, 8)
#define SYSCTRL_MB_CTRL_COMMAND_MASK REG_GENMASK(7, 0)
#define SYSCTRL_MB_CTRL_CMD REG_FIELD_PREP(SYSCTRL_MB_CTRL_COMMAND_MASK, 5)
#define SYSCTRL_MB_DATA0 XE_REG(0x14)
#define SYSCTRL_MB_DATA1 XE_REG(0x18)
#define SYSCTRL_MB_DATA2 XE_REG(0x1c)
#define SYSCTRL_MB_DATA3 XE_REG(0x20)
#define SYSCTRL_FRAME_PHASE REG_BIT(24)
#define SYSCTRL_FRAME_CURRENT_MASK REG_GENMASK(21, 16)
#define SYSCTRL_FRAME_TOTAL_MASK REG_GENMASK(13, 8)
#define SYSCTRL_FRAME_COMMAND_MASK REG_GENMASK(7, 0)
#endif
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