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| author | José Roberto de Souza <jose.souza@intel.com> | 2024-12-27 10:32:19 -0800 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2025-01-02 05:35:16 -0800 |
| commit | 88fca61ba5e2ecd0552b9dea2500a16da12d0106 (patch) | |
| tree | 017082436264998ac7f99e1a59b7af9799210307 /drivers/gpu/drm/xe/xe_ring_ops.c | |
| parent | fba0f039affdd0c8767f24e41d5dbef49addea78 (diff) | |
| download | linux-88fca61ba5e2ecd0552b9dea2500a16da12d0106.tar.gz linux-88fca61ba5e2ecd0552b9dea2500a16da12d0106.zip | |
Revert "drm/xe: Force write completion of MI_STORE_DATA_IMM"
This reverts commit 1460bb1fef9ccf7390af0d74a15252442fd6effd.
In all places the MI_STORE_DATA_IMM are not followed by a read of
the same memory address in the same batch buffer and the posted writes
are flushed with PIPE_CONTROL or MI_FLUSH_DW in xe_ring_ops.c functions
so there is no need to set this register.
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Fixes: 1460bb1fef9c ("drm/xe: Force write completion of MI_STORE_DATA_IMM")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241227183230.101334-1-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/xe/xe_ring_ops.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_ring_ops.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c index c8ab37fa0d19..9f327f27c072 100644 --- a/drivers/gpu/drm/xe/xe_ring_ops.c +++ b/drivers/gpu/drm/xe/xe_ring_ops.c @@ -72,8 +72,7 @@ static int emit_user_interrupt(u32 *dw, int i) static int emit_store_imm_ggtt(u32 addr, u32 value, u32 *dw, int i) { - dw[i++] = MI_STORE_DATA_IMM | MI_SDI_GGTT | - MI_FORCE_WRITE_COMPLETION_CHECK | MI_SDI_NUM_DW(1); + dw[i++] = MI_STORE_DATA_IMM | MI_SDI_GGTT | MI_SDI_NUM_DW(1); dw[i++] = addr; dw[i++] = 0; dw[i++] = value; @@ -163,8 +162,7 @@ static int emit_pipe_invalidate(u32 mask_flags, bool invalidate_tlb, u32 *dw, static int emit_store_imm_ppgtt_posted(u64 addr, u64 value, u32 *dw, int i) { - dw[i++] = MI_STORE_DATA_IMM | MI_FORCE_WRITE_COMPLETION_CHECK | - MI_SDI_NUM_QW(1); + dw[i++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(1); dw[i++] = lower_32_bits(addr); dw[i++] = upper_32_bits(addr); dw[i++] = lower_32_bits(value); |