blob: 58f06db822cb0388340e55175eb732fb5defcc13 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 MediaTek Inc.
*
* Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
*/
#ifndef __PHY_MTK_H__
#define __PHY_MTK_H__
#include <linux/bitfield.h>
#include <linux/io.h>
static inline void mtk_phy_clear_bits(void __iomem *reg, u32 bits)
{
u32 tmp = readl(reg);
tmp &= ~bits;
writel(tmp, reg);
}
static inline void mtk_phy_set_bits(void __iomem *reg, u32 bits)
{
u32 tmp = readl(reg);
tmp |= bits;
writel(tmp, reg);
}
static inline void mtk_phy_update_bits(void __iomem *reg, u32 mask, u32 val)
{
u32 tmp = readl(reg);
tmp &= ~mask;
tmp |= val & mask;
writel(tmp, reg);
}
/* field @mask shall be constant and continuous */
#define mtk_phy_update_field(reg, mask, val) \
({ \
BUILD_BUG_ON_MSG(!__builtin_constant_p(mask), "mask is not constant"); \
mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val)); \
})
#endif
|
