summaryrefslogtreecommitdiff
path: root/drivers/phy/broadcom/phy-bcm-ns2-pcie.c
blob: 9e7434a0d3e0076ec49a9fcd733caa1c03aea330 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
/*
 * Copyright (C) 2016 Broadcom
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/device.h>
#include <linux/module.h>
#include <linux/of_mdio.h>
#include <linux/mdio.h>
#include <linux/phy.h>
#include <linux/phy/phy.h>

#define BLK_ADDR_REG_OFFSET	0x1f
#define PLL_AFE1_100MHZ_BLK	0x2100
#define PLL_CLK_AMP_OFFSET	0x03
#define PLL_CLK_AMP_2P05V	0x2b18

static int ns2_pci_phy_init(struct phy *p)
{
	struct mdio_device *mdiodev = phy_get_drvdata(p);
	int rc;

	/* select the AFE 100MHz block page */
	rc = mdiodev_write(mdiodev, BLK_ADDR_REG_OFFSET, PLL_AFE1_100MHZ_BLK);
	if (rc)
		goto err;

	/* set the 100 MHz reference clock amplitude to 2.05 v */
	rc = mdiodev_write(mdiodev, PLL_CLK_AMP_OFFSET, PLL_CLK_AMP_2P05V);
	if (rc)
		goto err;

	return 0;

err:
	dev_err(&mdiodev->dev, "Error %d writing to phy\n", rc);
	return rc;
}

static const struct phy_ops ns2_pci_phy_ops = {
	.init = ns2_pci_phy_init,
	.owner = THIS_MODULE,
};

static int ns2_pci_phy_probe(struct mdio_device *mdiodev)
{
	struct device *dev = &mdiodev->dev;
	struct phy_provider *provider;
	struct phy *phy;

	phy = devm_phy_create(dev, dev->of_node, &ns2_pci_phy_ops);
	if (IS_ERR(phy)) {
		dev_err(dev, "failed to create Phy\n");
		return PTR_ERR(phy);
	}

	phy_set_drvdata(phy, mdiodev);

	provider = devm_of_phy_provider_register(&phy->dev,
						 of_phy_simple_xlate);
	if (IS_ERR(provider)) {
		dev_err(dev, "failed to register Phy provider\n");
		return PTR_ERR(provider);
	}

	dev_info(dev, "%s PHY registered\n", dev_name(dev));

	return 0;
}

static const struct of_device_id ns2_pci_phy_of_match[] = {
	{ .compatible = "brcm,ns2-pcie-phy", },
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, ns2_pci_phy_of_match);

static struct mdio_driver ns2_pci_phy_driver = {
	.mdiodrv = {
		.driver = {
			.name = "phy-bcm-ns2-pci",
			.of_match_table = ns2_pci_phy_of_match,
		},
	},
	.probe = ns2_pci_phy_probe,
};
mdio_module_driver(ns2_pci_phy_driver);

MODULE_AUTHOR("Broadcom");
MODULE_DESCRIPTION("Broadcom Northstar2 PCI Phy driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:phy-bcm-ns2-pci");