1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* ARC PGU DRM driver.
*
* Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
*/
#include <drm/drm_atomic_helper.h>
#include <drm/drm_device.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_probe_helper.h>
#include <linux/clk.h>
#include <linux/platform_data/simplefb.h>
#include "arcpgu.h"
#include "arcpgu_regs.h"
#define ENCODE_PGU_XY(x, y) ((((x) - 1) << 16) | ((y) - 1))
static const u32 arc_pgu_supported_formats[] = {
DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB8888,
DRM_FORMAT_ARGB8888,
};
static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
{
struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
const struct drm_framebuffer *fb = crtc->primary->state->fb;
uint32_t pixel_format = fb->format->format;
u32 format = DRM_FORMAT_INVALID;
int i;
u32 reg_ctrl;
for (i = 0; i < ARRAY_SIZE(arc_pgu_supported_formats); i++) {
if (arc_pgu_supported_formats[i] == pixel_format)
format = arc_pgu_supported_formats[i];
}
if (WARN_ON(format == DRM_FORMAT_INVALID))
return;
reg_ctrl = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
if (format == DRM_FORMAT_RGB565)
reg_ctrl &= ~ARCPGU_MODE_XRGB8888;
else
reg_ctrl |= ARCPGU_MODE_XRGB8888;
arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, reg_ctrl);
}
static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
.destroy = drm_crtc_cleanup,
.set_config = drm_atomic_helper_set_config,
.page_flip = drm_atomic_helper_page_flip,
.reset = drm_atomic_helper_crtc_reset,
.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
};
static enum drm_mode_status arc_pgu_crtc_mode_valid(struct drm_crtc *crtc,
const struct drm_display_mode *mode)
{
struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
long rate, clk_rate = mode->clock * 1000;
long diff = clk_rate / 200; /* +-0.5% allowed by HDMI spec */
rate = clk_round_rate(arcpgu->clk, clk_rate);
if ((max(rate, clk_rate) - min(rate, clk_rate) < diff) && (rate > 0))
return MODE_OK;
return MODE_NOCLOCK;
}
static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
struct drm_display_mode *m = &crtc->state->adjusted_mode;
u32 val;
arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
m->crtc_hsync_end - m->crtc_hdisplay));
arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
m->crtc_vsync_end - m->crtc_vdisplay));
arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
m->crtc_vblank_end - m->crtc_vblank_start));
val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
if (m->flags & DRM_MODE_FLAG_PVSYNC)
val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
else
val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
if (m->flags & DRM_MODE_FLAG_PHSYNC)
val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
else
val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
arc_pgu_set_pxl_fmt(crtc);
clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
}
static void arc_pgu_crtc_atomic_enable(struct drm_crtc *crtc,
struct drm_atomic_state *state)
{
struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
clk_prepare_enable(arcpgu->clk);
arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
ARCPGU_CTRL_ENABLE_MASK);
}
static void arc_pgu_crtc_atomic_disable(struct drm_crtc *crtc,
struct drm_atomic_state *state)
{
struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
clk_disable_unprepare(arcpgu->clk);
arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
~ARCPGU_CTRL_ENABLE_MASK);
}
static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
.mode_valid = arc_pgu_crtc_mode_valid,
.mode_set_nofb = arc_pgu_crtc_mode_set_nofb,
.atomic_enable = arc_pgu_crtc_atomic_enable,
.atomic_disable = arc_pgu_crtc_atomic_disable,
};
static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
struct drm_atomic_state *state)
{
struct drm_plane_state *new_plane_state = plane->state;
struct arcpgu_drm_private *arcpgu;
struct drm_gem_cma_object *gem;
if (!new_plane_state->crtc || !new_plane_state->fb)
return;
arcpgu = crtc_to_arcpgu_priv(new_plane_state->crtc);
gem = drm_fb_cma_get_gem_obj(new_plane_state->fb, 0);
arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
}
static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
.atomic_update = arc_pgu_plane_atomic_update,
};
static const struct drm_plane_funcs arc_pgu_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
.destroy = drm_plane_cleanup,
.reset = drm_atomic_helper_plane_reset,
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
};
static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm)
{
struct arcpgu_drm_private *arcpgu = drm->dev_private;
struct drm_plane *plane = NULL;
int ret;
plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
if (!plane)
return ERR_PTR(-ENOMEM);
ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
arc_pgu_supported_formats,
ARRAY_SIZE(arc_pgu_supported_formats),
NULL,
DRM_PLANE_TYPE_PRIMARY, NULL);
if (ret)
return ERR_PTR(ret);
drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
arcpgu->plane = plane;
return plane;
}
int arc_pgu_setup_crtc(struct drm_device *drm)
{
struct arcpgu_drm_private *arcpgu = drm->dev_private;
struct drm_plane *primary;
int ret;
primary = arc_pgu_plane_init(drm);
if (IS_ERR(primary))
return PTR_ERR(primary);
ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
&arc_pgu_crtc_funcs, NULL);
if (ret) {
drm_plane_cleanup(primary);
return ret;
}
drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
return 0;
}
|
