1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
|
// SPDX-License-Identifier: GPL-2.0
/*
* GPIO driver for AMD 8111 south bridges
*
* Copyright (c) 2012 Dmitry Eremin-Solenikov
*
* Based on the AMD RNG driver:
* Copyright 2005 (c) MontaVista Software, Inc.
* with the majority of the code coming from:
*
* Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
* (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
*
* derived from
*
* Hardware driver for the AMD 768 Random Number Generator (RNG)
* (c) Copyright 2001 Red Hat Inc
*
* derived from
*
* Hardware driver for Intel i810 Random Number Generator (RNG)
* Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
* Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
*/
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/gpio/driver.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#define PMBASE_OFFSET 0xb0
#define PMBASE_SIZE 0x30
#define AMD_REG_GPIO(i) (0x10 + (i))
#define AMD_GPIO_LTCH_STS 0x40 /* Latch status, w1 */
#define AMD_GPIO_RTIN 0x20 /* Real Time in, ro */
#define AMD_GPIO_DEBOUNCE 0x10 /* Debounce, rw */
#define AMD_GPIO_MODE_MASK 0x0c /* Pin Mode Select, rw */
#define AMD_GPIO_MODE_IN 0x00
#define AMD_GPIO_MODE_OUT 0x04
/* Enable alternative (e.g. clkout, IRQ, etc) function of the pin */
#define AMD_GPIO_MODE_ALTFN 0x08 /* Or 0x09 */
#define AMD_GPIO_X_MASK 0x03 /* In/Out specific, rw */
#define AMD_GPIO_X_IN_ACTIVEHI 0x01 /* Active High */
#define AMD_GPIO_X_IN_LATCH 0x02 /* Latched version is selected */
#define AMD_GPIO_X_OUT_LOW 0x00
#define AMD_GPIO_X_OUT_HI 0x01
#define AMD_GPIO_X_OUT_CLK0 0x02
#define AMD_GPIO_X_OUT_CLK1 0x03
/*
* Data for PCI driver interface
*
* This data only exists for exporting the supported
* PCI ids via MODULE_DEVICE_TABLE. We do not actually
* register a pci_driver, because someone else might one day
* want to register another driver on the same PCI id.
*/
static const struct pci_device_id pci_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS), 0 },
{ 0, }, /* terminate list */
};
MODULE_DEVICE_TABLE(pci, pci_tbl);
struct amd_gpio {
struct gpio_chip chip;
u32 pmbase;
void __iomem *pm;
struct pci_dev *pdev;
spinlock_t lock; /* guards hw registers and orig table */
u8 orig[32];
};
static int amd_gpio_request(struct gpio_chip *chip, unsigned offset)
{
struct amd_gpio *agp = gpiochip_get_data(chip);
agp->orig[offset] = ioread8(agp->pm + AMD_REG_GPIO(offset)) &
(AMD_GPIO_DEBOUNCE | AMD_GPIO_MODE_MASK | AMD_GPIO_X_MASK);
dev_dbg(&agp->pdev->dev, "Requested gpio %d, data %x\n", offset, agp->orig[offset]);
return 0;
}
static void amd_gpio_free(struct gpio_chip *chip, unsigned offset)
{
struct amd_gpio *agp = gpiochip_get_data(chip);
dev_dbg(&agp->pdev->dev, "Freed gpio %d, data %x\n", offset, agp->orig[offset]);
iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset));
}
static void amd_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct amd_gpio *agp = gpiochip_get_data(chip);
u8 temp;
unsigned long flags;
spin_lock_irqsave(&agp->lock, flags);
temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
spin_unlock_irqrestore(&agp->lock, flags);
dev_dbg(&agp->pdev->dev, "Setting gpio %d, value %d, reg=%02x\n", offset, !!value, temp);
}
static int amd_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct amd_gpio *agp = gpiochip_get_data(chip);
u8 temp;
temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
dev_dbg(&agp->pdev->dev, "Getting gpio %d, reg=%02x\n", offset, temp);
return (temp & AMD_GPIO_RTIN) ? 1 : 0;
}
static int amd_gpio_dirout(struct gpio_chip *chip, unsigned offset, int value)
{
struct amd_gpio *agp = gpiochip_get_data(chip);
u8 temp;
unsigned long flags;
spin_lock_irqsave(&agp->lock, flags);
temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
spin_unlock_irqrestore(&agp->lock, flags);
dev_dbg(&agp->pdev->dev, "Dirout gpio %d, value %d, reg=%02x\n", offset, !!value, temp);
return 0;
}
static int amd_gpio_dirin(struct gpio_chip *chip, unsigned offset)
{
struct amd_gpio *agp = gpiochip_get_data(chip);
u8 temp;
unsigned long flags;
spin_lock_irqsave(&agp->lock, flags);
temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_IN;
iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
spin_unlock_irqrestore(&agp->lock, flags);
dev_dbg(&agp->pdev->dev, "Dirin gpio %d, reg=%02x\n", offset, temp);
return 0;
}
static struct amd_gpio gp = {
.chip = {
.label = "AMD GPIO",
.owner = THIS_MODULE,
.base = -1,
.ngpio = 32,
.request = amd_gpio_request,
.free = amd_gpio_free,
.set = amd_gpio_set,
.get = amd_gpio_get,
.direction_output = amd_gpio_dirout,
.direction_input = amd_gpio_dirin,
},
};
static int __init amd_gpio_init(void)
{
int err = -ENODEV;
struct pci_dev *pdev = NULL;
const struct pci_device_id *ent;
/* We look for our device - AMD South Bridge
* I don't know about a system with two such bridges,
* so we can assume that there is max. one device.
*
* We can't use plain pci_driver mechanism,
* as the device is really a multiple function device,
* main driver that binds to the pci_device is an smbus
* driver and have to find & bind to the device this way.
*/
for_each_pci_dev(pdev) {
ent = pci_match_id(pci_tbl, pdev);
if (ent)
goto found;
}
/* Device not found. */
goto out;
found:
err = pci_read_config_dword(pdev, 0x58, &gp.pmbase);
if (err)
goto out;
err = -EIO;
gp.pmbase &= 0x0000FF00;
if (gp.pmbase == 0)
goto out;
if (!devm_request_region(&pdev->dev, gp.pmbase + PMBASE_OFFSET,
PMBASE_SIZE, "AMD GPIO")) {
dev_err(&pdev->dev, "AMD GPIO region 0x%x already in use!\n",
gp.pmbase + PMBASE_OFFSET);
err = -EBUSY;
goto out;
}
gp.pm = ioport_map(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE);
if (!gp.pm) {
dev_err(&pdev->dev, "Couldn't map io port into io memory\n");
err = -ENOMEM;
goto out;
}
gp.pdev = pdev;
gp.chip.parent = &pdev->dev;
spin_lock_init(&gp.lock);
dev_info(&pdev->dev, "AMD-8111 GPIO detected\n");
err = gpiochip_add_data(&gp.chip, &gp);
if (err) {
dev_err(&pdev->dev, "GPIO registering failed (%d)\n", err);
ioport_unmap(gp.pm);
goto out;
}
out:
return err;
}
static void __exit amd_gpio_exit(void)
{
gpiochip_remove(&gp.chip);
ioport_unmap(gp.pm);
}
module_init(amd_gpio_init);
module_exit(amd_gpio_exit);
MODULE_AUTHOR("The Linux Kernel team");
MODULE_DESCRIPTION("GPIO driver for AMD chipsets");
MODULE_LICENSE("GPL");
|
