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# SPDX-License-Identifier: GPL-2.0
if (BF561)
source "arch/blackfin/mach-bf561/boards/Kconfig"
menu "BF561 Specific Configuration"
if (!SMP)
comment "Core B Support"
config BF561_COREB
bool "Enable Core B loader"
default y
endif
comment "Interrupt Priority Assignment"
menu "Priority"
config IRQ_PLL_WAKEUP
int "PLL Wakeup Interrupt"
default 7
config IRQ_DMA1_ERROR
int "DMA1 Error (generic)"
default 7
config IRQ_DMA2_ERROR
int "DMA2 Error (generic)"
default 7
config IRQ_IMDMA_ERROR
int "IMDMA Error (generic)"
default 7
config IRQ_PPI0_ERROR
int "PPI0 Error Interrupt"
default 7
config IRQ_PPI1_ERROR
int "PPI1 Error Interrupt"
default 7
config IRQ_SPORT0_ERROR
int "SPORT0 Error Interrupt"
default 7
config IRQ_SPORT1_ERROR
int "SPORT1 Error Interrupt"
default 7
config IRQ_SPI_ERROR
int "SPI Error Interrupt"
default 7
config IRQ_UART_ERROR
int "UART Error Interrupt"
default 7
config IRQ_RESERVED_ERROR
int "Reserved Interrupt"
default 7
config IRQ_DMA1_0
int "DMA1 0 Interrupt(PPI1)"
default 8
config IRQ_DMA1_1
int "DMA1 1 Interrupt(PPI2)"
default 8
config IRQ_DMA1_2
int "DMA1 2 Interrupt"
default 8
config IRQ_DMA1_3
int "DMA1 3 Interrupt"
default 8
config IRQ_DMA1_4
int "DMA1 4 Interrupt"
default 8
config IRQ_DMA1_5
int "DMA1 5 Interrupt"
default 8
config IRQ_DMA1_6
int "DMA1 6 Interrupt"
default 8
config IRQ_DMA1_7
int "DMA1 7 Interrupt"
default 8
config IRQ_DMA1_8
int "DMA1 8 Interrupt"
default 8
config IRQ_DMA1_9
int "DMA1 9 Interrupt"
default 8
config IRQ_DMA1_10
int "DMA1 10 Interrupt"
default 8
config IRQ_DMA1_11
int "DMA1 11 Interrupt"
default 8
config IRQ_DMA2_0
int "DMA2 0 (SPORT0 RX)"
default 9
config IRQ_DMA2_1
int "DMA2 1 (SPORT0 TX)"
default 9
config IRQ_DMA2_2
int "DMA2 2 (SPORT1 RX)"
default 9
config IRQ_DMA2_3
int "DMA2 3 (SPORT2 TX)"
default 9
config IRQ_DMA2_4
int "DMA2 4 (SPI)"
default 9
config IRQ_DMA2_5
int "DMA2 5 (UART RX)"
default 9
config IRQ_DMA2_6
int "DMA2 6 (UART TX)"
default 9
config IRQ_DMA2_7
int "DMA2 7 Interrupt"
default 9
config IRQ_DMA2_8
int "DMA2 8 Interrupt"
default 9
config IRQ_DMA2_9
int "DMA2 9 Interrupt"
default 9
config IRQ_DMA2_10
int "DMA2 10 Interrupt"
default 9
config IRQ_DMA2_11
int "DMA2 11 Interrupt"
default 9
config IRQ_TIMER0
int "TIMER 0 Interrupt"
default 7 if TICKSOURCE_GPTMR0
default 8
config IRQ_TIMER1
int "TIMER 1 Interrupt"
default 10
config IRQ_TIMER2
int "TIMER 2 Interrupt"
default 10
config IRQ_TIMER3
int "TIMER 3 Interrupt"
default 10
config IRQ_TIMER4
int "TIMER 4 Interrupt"
default 10
config IRQ_TIMER5
int "TIMER 5 Interrupt"
default 10
config IRQ_TIMER6
int "TIMER 6 Interrupt"
default 10
config IRQ_TIMER7
int "TIMER 7 Interrupt"
default 10
config IRQ_TIMER8
int "TIMER 8 Interrupt"
default 10
config IRQ_TIMER9
int "TIMER 9 Interrupt"
default 10
config IRQ_TIMER10
int "TIMER 10 Interrupt"
default 10
config IRQ_TIMER11
int "TIMER 11 Interrupt"
default 10
config IRQ_PROG0_INTA
int "Programmable Flags0 A (8)"
default 11
config IRQ_PROG0_INTB
int "Programmable Flags0 B (8)"
default 11
config IRQ_PROG1_INTA
int "Programmable Flags1 A (8)"
default 11
config IRQ_PROG1_INTB
int "Programmable Flags1 B (8)"
default 11
config IRQ_PROG2_INTA
int "Programmable Flags2 A (8)"
default 11
config IRQ_PROG2_INTB
int "Programmable Flags2 B (8)"
default 11
config IRQ_DMA1_WRRD0
int "MDMA1 0 write/read INT"
default 8
config IRQ_DMA1_WRRD1
int "MDMA1 1 write/read INT"
default 8
config IRQ_DMA2_WRRD0
int "MDMA2 0 write/read INT"
default 9
config IRQ_DMA2_WRRD1
int "MDMA2 1 write/read INT"
default 9
config IRQ_IMDMA_WRRD0
int "IMDMA 0 write/read INT"
default 12
config IRQ_IMDMA_WRRD1
int "IMDMA 1 write/read INT"
default 12
config IRQ_WDTIMER
int "Watch Dog Timer"
default 13
help
Enter the priority numbers between 7-13 ONLY. Others are Reserved.
This applies to all the above. It is not recommended to assign the
highest priority number 7 to UART or any other device.
endmenu
endmenu
endif
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