blob: fe85bc5b131fc594ba16f712066a5b1f89b4e4b4 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* Orion CPU Bridge Registers */
#ifndef __ASM_ARCH_BRIDGE_REGS_H
#define __ASM_ARCH_BRIDGE_REGS_H
#include "orion5x.h"
#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
#define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300)
#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300)
#endif
|
