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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Tegra Quad SPI Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jonathan Hunter <jonathanh@nvidia.com>
allOf:
- $ref: spi-controller.yaml#
properties:
compatible:
enum:
- nvidia,tegra210-qspi
- nvidia,tegra186-qspi
- nvidia,tegra194-qspi
- nvidia,tegra234-qspi
- nvidia,tegra241-qspi
reg:
maxItems: 1
interrupts:
maxItems: 1
clock-names:
items:
- const: qspi
- const: qspi_out
clocks:
maxItems: 2
resets:
maxItems: 1
dmas:
maxItems: 2
dma-names:
items:
- const: rx
- const: tx
patternProperties:
"@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
spi-rx-bus-width:
enum: [1, 2, 4]
spi-tx-bus-width:
enum: [1, 2, 4]
required:
- compatible
- reg
- interrupts
- clock-names
- clocks
- resets
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/reset/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
spi@70410000 {
compatible = "nvidia,tegra210-qspi";
reg = <0x70410000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_QSPI>,
<&tegra_car TEGRA210_CLK_QSPI_PM>;
clock-names = "qspi", "qspi_out";
resets = <&tegra_car 211>;
dmas = <&apbdma 5>, <&apbdma 5>;
dma-names = "rx", "tx";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
nvidia,tx-clk-tap-delay = <0>;
nvidia,rx-clk-tap-delay = <0>;
};
};
|
