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SiFive asynchronous serial interface (UART)
Required properties:
- compatible: should be something similar to
"sifive,<chip>-uart" for the UART as integrated
on a particular chip, and "sifive,uart<version>" for the
general UART IP block programming model. Supported
compatible strings as of the date of this writing are:
"sifive,fu540-c000-uart" for the SiFive UART v0 as
integrated onto the SiFive FU540 chip, or "sifive,uart0"
for the SiFive UART v0 IP block with no chip integration
tweaks (if any)
- reg: address and length of the register space
- interrupts: Should contain the UART interrupt identifier
- clocks: Should contain a clock identifier for the UART's parent clock
UART HDL that corresponds to the IP block version numbers can be found
here:
https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
Example:
uart0: serial@10010000 {
compatible = "sifive,fu540-c000-uart", "sifive,uart0";
interrupt-parent = <&plic0>;
interrupts = <80>;
reg = <0x0 0x10010000 0x0 0x1000>;
clocks = <&prci PRCI_CLK_TLCLK>;
};
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