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|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/nvmem.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVMEM (Non Volatile Memory)
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
This binding is intended to represent the location of hardware
configuration data stored in NVMEMs like eeprom, efuses and so on.
On a significant proportion of boards, the manufacturer has stored
some data on NVMEM, for the OS to be able to retrieve these
information and act upon it. Obviously, the OS has to know about
where to retrieve these data from, and where they are stored on the
storage device.
properties:
"#address-cells":
const: 1
"#size-cells":
const: 1
read-only:
$ref: /schemas/types.yaml#/definitions/flag
description:
Mark the provider as read only.
wp-gpios:
description:
GPIO to which the write-protect pin of the chip is connected.
The write-protect GPIO is asserted, when it's driven high
(logical '1') to block the write operation. It's deasserted,
when it's driven low (logical '0') to allow writing.
maxItems: 1
nvmem-layout:
$ref: /schemas/nvmem/layouts/nvmem-layout.yaml
description:
Alternative to the statically defined nvmem cells, this
container may reference more advanced (dynamic) layout
parsers.
patternProperties:
"@[0-9a-f]+(,[0-7])?$":
type: object
properties:
reg:
maxItems: 1
description:
Offset and size in bytes within the storage device.
bits:
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- minimum: 0
maximum: 7
description:
Offset in bit within the address range specified by reg.
- minimum: 1
description:
Size in bit within the address range specified by reg.
additionalProperties: true
examples:
- |
#include <dt-bindings/gpio/gpio.h>
qfprom: eeprom@700000 {
compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00700000 0x100000>;
wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
/* ... */
/* Data cells */
tsens_calibration: calib@404 {
reg = <0x404 0x10>;
};
tsens_calibration_bckp: calib_bckp@504 {
reg = <0x504 0x11>;
bits = <6 128>;
};
pvs_version: pvs-version@6 {
reg = <0x6 0x2>;
bits = <7 2>;
};
speed_bin: speed-bin@c{
reg = <0xc 0x1>;
bits = <2 3>;
};
};
...
|
