From 8cbc5d2f2fe42a1bb1491f25486999d8f4ba9733 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Sat, 17 Apr 2021 13:29:47 +0200 Subject: dt-bindings: add power-domain header for RK3568 SoCs According to a description from TRM, add all the power domains Signed-off-by: Elaine Zhang Reviewed-by: Enric Balletbo i Serra Signed-off-by: Johan Jonker Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210417112952.8516-11-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- include/dt-bindings/power/rk3568-power.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/power/rk3568-power.h (limited to 'include') diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h new file mode 100644 index 000000000000..6cc1af1a9d26 --- /dev/null +++ b/include/dt-bindings/power/rk3568-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ + +/* VD_CORE */ +#define RK3568_PD_CPU_0 0 +#define RK3568_PD_CPU_1 1 +#define RK3568_PD_CPU_2 2 +#define RK3568_PD_CPU_3 3 +#define RK3568_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3568_PD_PMU 5 + +/* VD_NPU */ +#define RK3568_PD_NPU 6 + +/* VD_GPU */ +#define RK3568_PD_GPU 7 + +/* VD_LOGIC */ +#define RK3568_PD_VI 8 +#define RK3568_PD_VO 9 +#define RK3568_PD_RGA 10 +#define RK3568_PD_VPU 11 +#define RK3568_PD_CENTER 12 +#define RK3568_PD_RKVDEC 13 +#define RK3568_PD_RKVENC 14 +#define RK3568_PD_PIPE 15 +#define RK3568_PD_LOGIC_ALIVE 16 + +#endif -- cgit v1.2.3 From dfa3d406e2ab1136333d6d0f13723a0467206d1a Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 20 Jan 2021 14:50:36 -0800 Subject: dt-bindings: power: rpmpd: Add SC8180X to rpmpd binding Add compatible and constants for the power domains exposed by the RPMH in the Qualcomm SC8180X platform. Reviewed-by: Shawn Guo Reviewed-by: Vinod Koul Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210120225037.1611353-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 13 +++++++++++++ 2 files changed, 14 insertions(+) (limited to 'include') diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index ff21bfef8204..c01bb5f0d6ea 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -26,6 +26,7 @@ properties: - qcom,sdm660-rpmpd - qcom,sc7180-rpmhpd - qcom,sc7280-rpmhpd + - qcom,sc8180x-rpmhpd - qcom,sdm845-rpmhpd - qcom,sdx55-rpmhpd - qcom,sm8150-rpmhpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index eedb5d94c020..93c134f3724d 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -81,6 +81,19 @@ #define SC7280_LCX 7 #define SC7280_MSS 8 +/* SC8180X Power Domain Indexes */ +#define SC8180X_CX 0 +#define SC8180X_CX_AO 1 +#define SC8180X_EBI 2 +#define SC8180X_GFX 3 +#define SC8180X_LCX 4 +#define SC8180X_LMX 5 +#define SC8180X_MMCX 6 +#define SC8180X_MMCX_AO 7 +#define SC8180X_MSS 8 +#define SC8180X_MX 9 +#define SC8180X_MX_AO 10 + /* SDM845 Power Domain performance levels */ #define RPMH_REGULATOR_LEVEL_RETENTION 16 #define RPMH_REGULATOR_LEVEL_MIN_SVS 48 -- cgit v1.2.3 From e781858488b918e30a6ff28e9eab6058b787e3b3 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 21 May 2021 16:10:29 +0100 Subject: firmware: arm_ffa: Add initial FFA bus support for device enumeration The Arm FF for Armv8-A specification has concept of endpoints or partitions. In the Normal world, a partition could be a VM when the Virtualization extension is enabled or the kernel itself. In order to handle multiple partitions, we can create a FFA device for each such partition on a dedicated FFA bus. Similarly, different drivers requiring FFA transport can be registered on the same bus. We can match the device and drivers using UUID. This is mostly for the in-kernel users with FFA drivers. Link: https://lore.kernel.org/r/20210521151033.181846-2-sudeep.holla@arm.com Tested-by: Jens Wiklander Signed-off-by: Sudeep Holla --- MAINTAINERS | 7 ++ drivers/firmware/Kconfig | 1 + drivers/firmware/Makefile | 1 + drivers/firmware/arm_ffa/Kconfig | 16 +++ drivers/firmware/arm_ffa/Makefile | 4 + drivers/firmware/arm_ffa/bus.c | 207 ++++++++++++++++++++++++++++++++++++++ include/linux/arm_ffa.h | 91 +++++++++++++++++ 7 files changed, 327 insertions(+) create mode 100644 drivers/firmware/arm_ffa/Kconfig create mode 100644 drivers/firmware/arm_ffa/Makefile create mode 100644 drivers/firmware/arm_ffa/bus.c create mode 100644 include/linux/arm_ffa.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index bd7aff0c120f..3b8ab94cf697 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7069,6 +7069,13 @@ F: include/linux/firewire.h F: include/uapi/linux/firewire*.h F: tools/firewire/ +FIRMWARE FRAMEWORK FOR ARMV8-A +M: Sudeep Holla +L: linux-arm-kernel@lists.infradead.org +S: Maintained +F: drivers/firmware/arm_ffa/ +F: include/linux/arm_ffa.h + FIRMWARE LOADER (request_firmware) M: Luis Chamberlain L: linux-kernel@vger.kernel.org diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index db0ea2d2d75a..b53ac9fc7704 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -296,6 +296,7 @@ config TURRIS_MOX_RWTM other manufacturing data and also utilize the Entropy Bit Generator for hardware random number generation. +source "drivers/firmware/arm_ffa/Kconfig" source "drivers/firmware/broadcom/Kconfig" source "drivers/firmware/google/Kconfig" source "drivers/firmware/efi/Kconfig" diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index 5e013b6a3692..546ac8e7f6d0 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o obj-$(CONFIG_TURRIS_MOX_RWTM) += turris-mox-rwtm.o +obj-y += arm_ffa/ obj-y += arm_scmi/ obj-y += broadcom/ obj-y += meson/ diff --git a/drivers/firmware/arm_ffa/Kconfig b/drivers/firmware/arm_ffa/Kconfig new file mode 100644 index 000000000000..261a3660650a --- /dev/null +++ b/drivers/firmware/arm_ffa/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only +config ARM_FFA_TRANSPORT + tristate "Arm Firmware Framework for Armv8-A" + depends on OF + depends on ARM64 + default n + help + This Firmware Framework(FF) for Arm A-profile processors describes + interfaces that standardize communication between the various + software images which includes communication between images in + the Secure world and Normal world. It also leverages the + virtualization extension to isolate software images provided + by an ecosystem of vendors from each other. + + This driver provides interface for all the client drivers making + use of the features offered by ARM FF-A. diff --git a/drivers/firmware/arm_ffa/Makefile b/drivers/firmware/arm_ffa/Makefile new file mode 100644 index 000000000000..bfe4323a8784 --- /dev/null +++ b/drivers/firmware/arm_ffa/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +ffa-bus-y = bus.o +ffa-module-objs := $(ffa-bus-y) +obj-$(CONFIG_ARM_FFA_TRANSPORT) = ffa-module.o diff --git a/drivers/firmware/arm_ffa/bus.c b/drivers/firmware/arm_ffa/bus.c new file mode 100644 index 000000000000..a17874bed946 --- /dev/null +++ b/drivers/firmware/arm_ffa/bus.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 ARM Ltd. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include + +static int ffa_device_match(struct device *dev, struct device_driver *drv) +{ + const struct ffa_device_id *id_table; + struct ffa_device *ffa_dev; + + id_table = to_ffa_driver(drv)->id_table; + ffa_dev = to_ffa_dev(dev); + + while (!uuid_is_null(&id_table->uuid)) { + if (uuid_equal(&ffa_dev->uuid, &id_table->uuid)) + return 1; + id_table++; + } + + return 0; +} + +static int ffa_device_probe(struct device *dev) +{ + struct ffa_driver *ffa_drv = to_ffa_driver(dev->driver); + struct ffa_device *ffa_dev = to_ffa_dev(dev); + + if (!ffa_device_match(dev, dev->driver)) + return -ENODEV; + + return ffa_drv->probe(ffa_dev); +} + +static int ffa_device_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + struct ffa_device *ffa_dev = to_ffa_dev(dev); + + return add_uevent_var(env, "MODALIAS=arm_ffa:%04x:%pUb", + ffa_dev->vm_id, &ffa_dev->uuid); +} + +static ssize_t partition_id_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ffa_device *ffa_dev = to_ffa_dev(dev); + + return sprintf(buf, "0x%04x\n", ffa_dev->vm_id); +} +static DEVICE_ATTR_RO(partition_id); + +static ssize_t uuid_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct ffa_device *ffa_dev = to_ffa_dev(dev); + + return sprintf(buf, "%pUb\n", &ffa_dev->uuid); +} +static DEVICE_ATTR_RO(uuid); + +static struct attribute *ffa_device_attributes_attrs[] = { + &dev_attr_partition_id.attr, + &dev_attr_uuid.attr, + NULL, +}; +ATTRIBUTE_GROUPS(ffa_device_attributes); + +struct bus_type ffa_bus_type = { + .name = "arm_ffa", + .match = ffa_device_match, + .probe = ffa_device_probe, + .uevent = ffa_device_uevent, + .dev_groups = ffa_device_attributes_groups, +}; +EXPORT_SYMBOL_GPL(ffa_bus_type); + +int ffa_driver_register(struct ffa_driver *driver, struct module *owner, + const char *mod_name) +{ + int ret; + + driver->driver.bus = &ffa_bus_type; + driver->driver.name = driver->name; + driver->driver.owner = owner; + driver->driver.mod_name = mod_name; + + ret = driver_register(&driver->driver); + if (!ret) + pr_debug("registered new ffa driver %s\n", driver->name); + + return ret; +} +EXPORT_SYMBOL_GPL(ffa_driver_register); + +void ffa_driver_unregister(struct ffa_driver *driver) +{ + driver_unregister(&driver->driver); +} +EXPORT_SYMBOL_GPL(ffa_driver_unregister); + +static void ffa_release_device(struct device *dev) +{ + struct ffa_device *ffa_dev = to_ffa_dev(dev); + + kfree(ffa_dev); +} + +static int __ffa_devices_unregister(struct device *dev, void *data) +{ + ffa_release_device(dev); + + return 0; +} + +static void ffa_devices_unregister(void) +{ + bus_for_each_dev(&ffa_bus_type, NULL, NULL, + __ffa_devices_unregister); +} + +bool ffa_device_is_valid(struct ffa_device *ffa_dev) +{ + bool valid = false; + struct device *dev = NULL; + struct ffa_device *tmp_dev; + + do { + dev = bus_find_next_device(&ffa_bus_type, dev); + tmp_dev = to_ffa_dev(dev); + if (tmp_dev == ffa_dev) { + valid = true; + break; + } + put_device(dev); + } while (dev); + + put_device(dev); + + return valid; +} + +struct ffa_device *ffa_device_register(const uuid_t *uuid, int vm_id) +{ + int ret; + struct device *dev; + struct ffa_device *ffa_dev; + + ffa_dev = kzalloc(sizeof(*ffa_dev), GFP_KERNEL); + if (!ffa_dev) + return NULL; + + dev = &ffa_dev->dev; + dev->bus = &ffa_bus_type; + dev->release = ffa_release_device; + dev_set_name(&ffa_dev->dev, "arm-ffa-%04x", vm_id); + + ffa_dev->vm_id = vm_id; + uuid_copy(&ffa_dev->uuid, uuid); + + ret = device_register(&ffa_dev->dev); + if (ret) { + dev_err(dev, "unable to register device %s err=%d\n", + dev_name(dev), ret); + put_device(dev); + return NULL; + } + + return ffa_dev; +} +EXPORT_SYMBOL_GPL(ffa_device_register); + +void ffa_device_unregister(struct ffa_device *ffa_dev) +{ + if (!ffa_dev) + return; + + device_unregister(&ffa_dev->dev); +} +EXPORT_SYMBOL_GPL(ffa_device_unregister); + +static int __init arm_ffa_bus_init(void) +{ + return bus_register(&ffa_bus_type); +} +module_init(arm_ffa_bus_init); + +static void __exit arm_ffa_bus_exit(void) +{ + ffa_devices_unregister(); + bus_unregister(&ffa_bus_type); +} + +module_exit(arm_ffa_bus_exit); + +MODULE_ALIAS("arm-ffa-bus"); +MODULE_AUTHOR("Sudeep Holla "); +MODULE_DESCRIPTION("Arm FF-A bus driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/arm_ffa.h b/include/linux/arm_ffa.h new file mode 100644 index 000000000000..331ff62c9873 --- /dev/null +++ b/include/linux/arm_ffa.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 ARM Ltd. + */ + +#ifndef _LINUX_ARM_FFA_H +#define _LINUX_ARM_FFA_H + +#include +#include +#include +#include +#include + +/* FFA Bus/Device/Driver related */ +struct ffa_device { + int vm_id; + uuid_t uuid; + struct device dev; +}; + +#define to_ffa_dev(d) container_of(d, struct ffa_device, dev) + +struct ffa_device_id { + uuid_t uuid; +}; + +struct ffa_driver { + const char *name; + int (*probe)(struct ffa_device *sdev); + void (*remove)(struct ffa_device *sdev); + const struct ffa_device_id *id_table; + + struct device_driver driver; +}; + +#define to_ffa_driver(d) container_of(d, struct ffa_driver, driver) + +static inline void ffa_dev_set_drvdata(struct ffa_device *fdev, void *data) +{ + fdev->dev.driver_data = data; +} + +#if IS_REACHABLE(CONFIG_ARM_FFA_TRANSPORT) +struct ffa_device *ffa_device_register(const uuid_t *uuid, int vm_id); +void ffa_device_unregister(struct ffa_device *ffa_dev); +int ffa_driver_register(struct ffa_driver *driver, struct module *owner, + const char *mod_name); +void ffa_driver_unregister(struct ffa_driver *driver); +bool ffa_device_is_valid(struct ffa_device *ffa_dev); + +#else +static inline +struct ffa_device *ffa_device_register(const uuid_t *uuid, int vm_id) +{ + return NULL; +} + +static inline void ffa_device_unregister(struct ffa_device *dev) {} + +static inline int +ffa_driver_register(struct ffa_driver *driver, struct module *owner, + const char *mod_name) +{ + return -EINVAL; +} + +static inline void ffa_driver_unregister(struct ffa_driver *driver) {} + +static inline +bool ffa_device_is_valid(struct ffa_device *ffa_dev) { return false; } + +#endif /* CONFIG_ARM_FFA_TRANSPORT */ + +#define ffa_register(driver) \ + ffa_driver_register(driver, THIS_MODULE, KBUILD_MODNAME) +#define ffa_unregister(driver) \ + ffa_driver_unregister(driver) + +/** + * module_ffa_driver() - Helper macro for registering a psa_ffa driver + * @__ffa_driver: ffa_driver structure + * + * Helper macro for psa_ffa drivers to set up proper module init / exit + * functions. Replaces module_init() and module_exit() and keeps people from + * printing pointless things to the kernel log when their driver is loaded. + */ +#define module_ffa_driver(__ffa_driver) \ + module_driver(__ffa_driver, ffa_register, ffa_unregister) + +#endif /* _LINUX_ARM_FFA_H */ -- cgit v1.2.3 From d0c0bce831223b08e5bade2cefc93c3ddb790796 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 21 May 2021 16:10:32 +0100 Subject: firmware: arm_ffa: Setup in-kernel users of FFA partitions Parse the FFA nodes from the device-tree and register all the partitions whose services will be used in the kernel. In order to also enable in-kernel users of FFA interface, let us add simple set of operations for such devices. The in-kernel users are registered without the character device interface. Link: https://lore.kernel.org/r/20210521151033.181846-5-sudeep.holla@arm.com Tested-by: Jens Wiklander Reviewed-by: Jens Wiklander Signed-off-by: Sudeep Holla --- drivers/firmware/arm_ffa/bus.c | 9 ++ drivers/firmware/arm_ffa/common.h | 3 + drivers/firmware/arm_ffa/driver.c | 221 ++++++++++++++++++++++++++++++++++++++ include/linux/arm_ffa.h | 39 ++++++- 4 files changed, 271 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/firmware/arm_ffa/bus.c b/drivers/firmware/arm_ffa/bus.c index ae1eada5dc0c..83166e02b191 100644 --- a/drivers/firmware/arm_ffa/bus.c +++ b/drivers/firmware/arm_ffa/bus.c @@ -24,6 +24,15 @@ static int ffa_device_match(struct device *dev, struct device_driver *drv) ffa_dev = to_ffa_dev(dev); while (!uuid_is_null(&id_table->uuid)) { + /* + * FF-A v1.0 doesn't provide discovery of UUIDs, just the + * partition IDs, so fetch the partitions IDs for this + * id_table UUID and assign the UUID to the device if the + * partition ID matches + */ + if (uuid_is_null(&ffa_dev->uuid)) + ffa_device_match_uuid(ffa_dev, &id_table->uuid); + if (uuid_equal(&ffa_dev->uuid, &id_table->uuid)) return 1; id_table++; diff --git a/drivers/firmware/arm_ffa/common.h b/drivers/firmware/arm_ffa/common.h index f24754a59f47..d6eccf1fd3f6 100644 --- a/drivers/firmware/arm_ffa/common.h +++ b/drivers/firmware/arm_ffa/common.h @@ -6,6 +6,7 @@ #ifndef _FFA_COMMON_H #define _FFA_COMMON_H +#include #include #include @@ -15,6 +16,8 @@ typedef void (ffa_fn)(ffa_value_t, ffa_value_t *); int arm_ffa_bus_init(void); void arm_ffa_bus_exit(void); +bool ffa_device_is_valid(struct ffa_device *ffa_dev); +void ffa_device_match_uuid(struct ffa_device *ffa_dev, const uuid_t *uuid); #ifdef CONFIG_ARM_FFA_SMCCC int __init ffa_transport_init(ffa_fn **invoke_ffa_fn); diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c index 4846f079dca0..85b9bbdbeabe 100644 --- a/drivers/firmware/arm_ffa/driver.c +++ b/drivers/firmware/arm_ffa/driver.c @@ -24,9 +24,12 @@ #include #include +#include #include +#include #include #include +#include #include "common.h" @@ -185,6 +188,22 @@ static int ffa_version_check(u32 *version) return 0; } +static int ffa_rx_release(void) +{ + ffa_value_t ret; + + invoke_ffa_fn((ffa_value_t){ + .a0 = FFA_RX_RELEASE, + }, &ret); + + if (ret.a0 == FFA_ERROR) + return ffa_to_linux_errno((int)ret.a2); + + /* check for ret.a0 == FFA_RX_RELEASE ? */ + + return 0; +} + static int ffa_rxtx_map(phys_addr_t tx_buf, phys_addr_t rx_buf, u32 pg_cnt) { ffa_value_t ret; @@ -214,6 +233,65 @@ static int ffa_rxtx_unmap(u16 vm_id) return 0; } +/* buffer must be sizeof(struct ffa_partition_info) * num_partitions */ +static int +__ffa_partition_info_get(u32 uuid0, u32 uuid1, u32 uuid2, u32 uuid3, + struct ffa_partition_info *buffer, int num_partitions) +{ + int count; + ffa_value_t partition_info; + + mutex_lock(&drv_info->rx_lock); + invoke_ffa_fn((ffa_value_t){ + .a0 = FFA_PARTITION_INFO_GET, + .a1 = uuid0, .a2 = uuid1, .a3 = uuid2, .a4 = uuid3, + }, &partition_info); + + if (partition_info.a0 == FFA_ERROR) { + mutex_unlock(&drv_info->rx_lock); + return ffa_to_linux_errno((int)partition_info.a2); + } + + count = partition_info.a2; + + if (buffer && count <= num_partitions) + memcpy(buffer, drv_info->rx_buffer, sizeof(*buffer) * count); + + ffa_rx_release(); + + mutex_unlock(&drv_info->rx_lock); + + return count; +} + +/* buffer is allocated and caller must free the same if returned count > 0 */ +static int +ffa_partition_probe(const uuid_t *uuid, struct ffa_partition_info **buffer) +{ + int count; + u32 uuid0_4[4]; + struct ffa_partition_info *pbuf; + + export_uuid((u8 *)uuid0_4, uuid); + count = __ffa_partition_info_get(uuid0_4[0], uuid0_4[1], uuid0_4[2], + uuid0_4[3], NULL, 0); + if (count <= 0) + return count; + + pbuf = kcalloc(count, sizeof(*pbuf), GFP_KERNEL); + if (!pbuf) + return -ENOMEM; + + count = __ffa_partition_info_get(uuid0_4[0], uuid0_4[1], uuid0_4[2], + uuid0_4[3], pbuf, count); + if (count <= 0) + kfree(pbuf); + else + *buffer = pbuf; + + return count; +} + #define VM_ID_MASK GENMASK(15, 0) static int ffa_id_get(u16 *vm_id) { @@ -231,6 +309,147 @@ static int ffa_id_get(u16 *vm_id) return 0; } +static int ffa_msg_send_direct_req(u16 src_id, u16 dst_id, bool mode_32bit, + struct ffa_send_direct_data *data) +{ + u32 req_id, resp_id, src_dst_ids = PACK_TARGET_INFO(src_id, dst_id); + ffa_value_t ret; + + if (mode_32bit) { + req_id = FFA_MSG_SEND_DIRECT_REQ; + resp_id = FFA_MSG_SEND_DIRECT_RESP; + } else { + req_id = FFA_FN_NATIVE(MSG_SEND_DIRECT_REQ); + resp_id = FFA_FN_NATIVE(MSG_SEND_DIRECT_RESP); + } + + invoke_ffa_fn((ffa_value_t){ + .a0 = req_id, .a1 = src_dst_ids, .a2 = 0, + .a3 = data->data0, .a4 = data->data1, .a5 = data->data2, + .a6 = data->data3, .a7 = data->data4, + }, &ret); + + while (ret.a0 == FFA_INTERRUPT) + invoke_ffa_fn((ffa_value_t){ + .a0 = FFA_RUN, .a1 = ret.a1, + }, &ret); + + if (ret.a0 == FFA_ERROR) + return ffa_to_linux_errno((int)ret.a2); + + if (ret.a0 == resp_id) { + data->data0 = ret.a3; + data->data1 = ret.a4; + data->data2 = ret.a5; + data->data3 = ret.a6; + data->data4 = ret.a7; + return 0; + } + + return -EINVAL; +} + +static u32 ffa_api_version_get(void) +{ + return drv_info->version; +} + +static int ffa_partition_info_get(const char *uuid_str, + struct ffa_partition_info *buffer) +{ + int count; + uuid_t uuid; + struct ffa_partition_info *pbuf; + + if (uuid_parse(uuid_str, &uuid)) { + pr_err("invalid uuid (%s)\n", uuid_str); + return -ENODEV; + } + + count = ffa_partition_probe(&uuid_null, &pbuf); + if (count <= 0) + return -ENOENT; + + memcpy(buffer, pbuf, sizeof(*pbuf) * count); + kfree(pbuf); + return 0; +} + +static void ffa_mode_32bit_set(struct ffa_device *dev) +{ + dev->mode_32bit = true; +} + +static int ffa_sync_send_receive(struct ffa_device *dev, + struct ffa_send_direct_data *data) +{ + return ffa_msg_send_direct_req(drv_info->vm_id, dev->vm_id, + dev->mode_32bit, data); +} + +static const struct ffa_dev_ops ffa_ops = { + .api_version_get = ffa_api_version_get, + .partition_info_get = ffa_partition_info_get, + .mode_32bit_set = ffa_mode_32bit_set, + .sync_send_receive = ffa_sync_send_receive, +}; + +const struct ffa_dev_ops *ffa_dev_ops_get(struct ffa_device *dev) +{ + if (ffa_device_is_valid(dev)) + return &ffa_ops; + + return NULL; +} +EXPORT_SYMBOL_GPL(ffa_dev_ops_get); + +void ffa_device_match_uuid(struct ffa_device *ffa_dev, const uuid_t *uuid) +{ + int count, idx; + struct ffa_partition_info *pbuf, *tpbuf; + + count = ffa_partition_probe(uuid, &pbuf); + if (count <= 0) + return; + + for (idx = 0, tpbuf = pbuf; idx < count; idx++, tpbuf++) + if (tpbuf->id == ffa_dev->vm_id) + uuid_copy(&ffa_dev->uuid, uuid); + kfree(pbuf); +} + +static void ffa_setup_partitions(void) +{ + int count, idx; + struct ffa_device *ffa_dev; + struct ffa_partition_info *pbuf, *tpbuf; + + count = ffa_partition_probe(&uuid_null, &pbuf); + if (count <= 0) { + pr_info("%s: No partitions found, error %d\n", __func__, count); + return; + } + + for (idx = 0, tpbuf = pbuf; idx < count; idx++, tpbuf++) { + /* Note that the &uuid_null parameter will require + * ffa_device_match() to find the UUID of this partition id + * with help of ffa_device_match_uuid(). Once the FF-A spec + * is updated to provide correct UUID here for each partition + * as part of the discovery API, we need to pass the + * discovered UUID here instead. + */ + ffa_dev = ffa_device_register(&uuid_null, tpbuf->id); + if (!ffa_dev) { + pr_err("%s: failed to register partition ID 0x%x\n", + __func__, tpbuf->id); + continue; + } + + ffa_dev_set_drvdata(ffa_dev, drv_info); + } + kfree(pbuf); +} + static int __init ffa_init(void) { int ret; @@ -282,6 +501,8 @@ static int __init ffa_init(void) mutex_init(&drv_info->rx_lock); mutex_init(&drv_info->tx_lock); + ffa_setup_partitions(); + return 0; free_pages: if (drv_info->tx_buffer) diff --git a/include/linux/arm_ffa.h b/include/linux/arm_ffa.h index 331ff62c9873..d672673fc621 100644 --- a/include/linux/arm_ffa.h +++ b/include/linux/arm_ffa.h @@ -6,7 +6,6 @@ #ifndef _LINUX_ARM_FFA_H #define _LINUX_ARM_FFA_H -#include #include #include #include @@ -15,6 +14,7 @@ /* FFA Bus/Device/Driver related */ struct ffa_device { int vm_id; + bool mode_32bit; uuid_t uuid; struct device dev; }; @@ -48,6 +48,7 @@ int ffa_driver_register(struct ffa_driver *driver, struct module *owner, const char *mod_name); void ffa_driver_unregister(struct ffa_driver *driver); bool ffa_device_is_valid(struct ffa_device *ffa_dev); +const struct ffa_dev_ops *ffa_dev_ops_get(struct ffa_device *dev); #else static inline @@ -70,6 +71,11 @@ static inline void ffa_driver_unregister(struct ffa_driver *driver) {} static inline bool ffa_device_is_valid(struct ffa_device *ffa_dev) { return false; } +static inline +const struct ffa_dev_ops *ffa_dev_ops_get(struct ffa_device *dev) +{ + return NULL; +} #endif /* CONFIG_ARM_FFA_TRANSPORT */ #define ffa_register(driver) \ @@ -88,4 +94,35 @@ bool ffa_device_is_valid(struct ffa_device *ffa_dev) { return false; } #define module_ffa_driver(__ffa_driver) \ module_driver(__ffa_driver, ffa_register, ffa_unregister) +/* FFA transport related */ +struct ffa_partition_info { + u16 id; + u16 exec_ctxt; +/* partition supports receipt of direct requests */ +#define FFA_PARTITION_DIRECT_RECV BIT(0) +/* partition can send direct requests. */ +#define FFA_PARTITION_DIRECT_SEND BIT(1) +/* partition can send and receive indirect messages. */ +#define FFA_PARTITION_INDIRECT_MSG BIT(2) + u32 properties; +}; + +/* For use with FFA_MSG_SEND_DIRECT_{REQ,RESP} which pass data via registers */ +struct ffa_send_direct_data { + unsigned long data0; /* w3/x3 */ + unsigned long data1; /* w4/x4 */ + unsigned long data2; /* w5/x5 */ + unsigned long data3; /* w6/x6 */ + unsigned long data4; /* w7/x7 */ +}; + +struct ffa_dev_ops { + u32 (*api_version_get)(void); + int (*partition_info_get)(const char *uuid_str, + struct ffa_partition_info *buffer); + void (*mode_32bit_set)(struct ffa_device *dev); + int (*sync_send_receive)(struct ffa_device *dev, + struct ffa_send_direct_data *data); +}; + #endif /* _LINUX_ARM_FFA_H */ -- cgit v1.2.3 From cc2195fe536c28e192df5d07e6dd277af36814b4 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 21 May 2021 16:10:33 +0100 Subject: firmware: arm_ffa: Add support for MEM_* interfaces Most of the MEM_* APIs share the same parameters, so they can be generalised. Currently only MEM_SHARE is implemented and the user space interface for that is not added yet. Link: https://lore.kernel.org/r/20210521151033.181846-6-sudeep.holla@arm.com Tested-by: Jens Wiklander Signed-off-by: Sudeep Holla --- drivers/firmware/arm_ffa/driver.c | 199 ++++++++++++++++++++++++++++++++++++++ include/linux/arm_ffa.h | 139 ++++++++++++++++++++++++++ 2 files changed, 338 insertions(+) (limited to 'include') diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c index 85b9bbdbeabe..b1edb4b2e94a 100644 --- a/drivers/firmware/arm_ffa/driver.c +++ b/drivers/firmware/arm_ffa/driver.c @@ -28,6 +28,8 @@ #include #include #include +#include +#include #include #include @@ -349,6 +351,192 @@ static int ffa_msg_send_direct_req(u16 src_id, u16 dst_id, bool mode_32bit, return -EINVAL; } +static int ffa_mem_first_frag(u32 func_id, phys_addr_t buf, u32 buf_sz, + u32 frag_len, u32 len, u64 *handle) +{ + ffa_value_t ret; + + invoke_ffa_fn((ffa_value_t){ + .a0 = func_id, .a1 = len, .a2 = frag_len, + .a3 = buf, .a4 = buf_sz, + }, &ret); + + while (ret.a0 == FFA_MEM_OP_PAUSE) + invoke_ffa_fn((ffa_value_t){ + .a0 = FFA_MEM_OP_RESUME, + .a1 = ret.a1, .a2 = ret.a2, + }, &ret); + + if (ret.a0 == FFA_ERROR) + return ffa_to_linux_errno((int)ret.a2); + + if (ret.a0 != FFA_SUCCESS) + return -EOPNOTSUPP; + + if (handle) + *handle = PACK_HANDLE(ret.a2, ret.a3); + + return frag_len; +} + +static int ffa_mem_next_frag(u64 handle, u32 frag_len) +{ + ffa_value_t ret; + + invoke_ffa_fn((ffa_value_t){ + .a0 = FFA_MEM_FRAG_TX, + .a1 = HANDLE_LOW(handle), .a2 = HANDLE_HIGH(handle), + .a3 = frag_len, + }, &ret); + + while (ret.a0 == FFA_MEM_OP_PAUSE) + invoke_ffa_fn((ffa_value_t){ + .a0 = FFA_MEM_OP_RESUME, + .a1 = ret.a1, .a2 = ret.a2, + }, &ret); + + if (ret.a0 == FFA_ERROR) + return ffa_to_linux_errno((int)ret.a2); + + if (ret.a0 != FFA_MEM_FRAG_RX) + return -EOPNOTSUPP; + + return ret.a3; +} + +static int +ffa_transmit_fragment(u32 func_id, phys_addr_t buf, u32 buf_sz, u32 frag_len, + u32 len, u64 *handle, bool first) +{ + if (!first) + return ffa_mem_next_frag(*handle, frag_len); + + return ffa_mem_first_frag(func_id, buf, buf_sz, frag_len, len, handle); +} + +static u32 ffa_get_num_pages_sg(struct scatterlist *sg) +{ + u32 num_pages = 0; + + do { + num_pages += sg->length / FFA_PAGE_SIZE; + } while ((sg = sg_next(sg))); + + return num_pages; +} + +static int +ffa_setup_and_transmit(u32 func_id, void *buffer, u32 max_fragsize, + struct ffa_mem_ops_args *args) +{ + int rc = 0; + bool first = true; + phys_addr_t addr = 0; + struct ffa_composite_mem_region *composite; + struct ffa_mem_region_addr_range *constituents; + struct ffa_mem_region_attributes *ep_mem_access; + struct ffa_mem_region *mem_region = buffer; + u32 idx, frag_len, length, buf_sz = 0, num_entries = sg_nents(args->sg); + + mem_region->tag = args->tag; + mem_region->flags = args->flags; + mem_region->sender_id = drv_info->vm_id; + mem_region->attributes = FFA_MEM_NORMAL | FFA_MEM_WRITE_BACK | + FFA_MEM_INNER_SHAREABLE; + ep_mem_access = &mem_region->ep_mem_access[0]; + + for (idx = 0; idx < args->nattrs; idx++, ep_mem_access++) { + ep_mem_access->receiver = args->attrs[idx].receiver; + ep_mem_access->attrs = args->attrs[idx].attrs; + ep_mem_access->composite_off = COMPOSITE_OFFSET(args->nattrs); + } + mem_region->ep_count = args->nattrs; + + composite = buffer + COMPOSITE_OFFSET(args->nattrs); + composite->total_pg_cnt = ffa_get_num_pages_sg(args->sg); + composite->addr_range_cnt = num_entries; + + length = COMPOSITE_CONSTITUENTS_OFFSET(args->nattrs, num_entries); + frag_len = COMPOSITE_CONSTITUENTS_OFFSET(args->nattrs, 0); + if (frag_len > max_fragsize) + return -ENXIO; + + if (!args->use_txbuf) { + addr = virt_to_phys(buffer); + buf_sz = max_fragsize / FFA_PAGE_SIZE; + } + + constituents = buffer + frag_len; + idx = 0; + do { + if (frag_len == max_fragsize) { + rc = ffa_transmit_fragment(func_id, addr, buf_sz, + frag_len, length, + &args->g_handle, first); + if (rc < 0) + return -ENXIO; + + first = false; + idx = 0; + frag_len = 0; + constituents = buffer; + } + + if ((void *)constituents - buffer > max_fragsize) { + pr_err("Memory Region Fragment > Tx Buffer size\n"); + return -EFAULT; + } + + constituents->address = sg_phys(args->sg); + constituents->pg_cnt = args->sg->length / FFA_PAGE_SIZE; + constituents++; + frag_len += sizeof(struct ffa_mem_region_addr_range); + } while ((args->sg = sg_next(args->sg))); + + return ffa_transmit_fragment(func_id, addr, buf_sz, frag_len, + length, &args->g_handle, first); +} + +static int ffa_memory_ops(u32 func_id, struct ffa_mem_ops_args *args) +{ + int ret; + void *buffer; + + if (!args->use_txbuf) { + buffer = alloc_pages_exact(RXTX_BUFFER_SIZE, GFP_KERNEL); + if (!buffer) + return -ENOMEM; + } else { + buffer = drv_info->tx_buffer; + mutex_lock(&drv_info->tx_lock); + } + + ret = ffa_setup_and_transmit(func_id, buffer, RXTX_BUFFER_SIZE, args); + + if (args->use_txbuf) + mutex_unlock(&drv_info->tx_lock); + else + free_pages_exact(buffer, RXTX_BUFFER_SIZE); + + return ret < 0 ? ret : 0; +} + +static int ffa_memory_reclaim(u64 g_handle, u32 flags) +{ + ffa_value_t ret; + + invoke_ffa_fn((ffa_value_t){ + .a0 = FFA_MEM_RECLAIM, + .a1 = HANDLE_LOW(g_handle), .a2 = HANDLE_HIGH(g_handle), + .a3 = flags, + }, &ret); + + if (ret.a0 == FFA_ERROR) + return ffa_to_linux_errno((int)ret.a2); + + return 0; +} + static u32 ffa_api_version_get(void) { return drv_info->version; @@ -387,11 +575,22 @@ static int ffa_sync_send_receive(struct ffa_device *dev, dev->mode_32bit, data); } +static int +ffa_memory_share(struct ffa_device *dev, struct ffa_mem_ops_args *args) +{ + if (dev->mode_32bit) + return ffa_memory_ops(FFA_MEM_SHARE, args); + + return ffa_memory_ops(FFA_FN_NATIVE(MEM_SHARE), args); +} + static const struct ffa_dev_ops ffa_ops = { .api_version_get = ffa_api_version_get, .partition_info_get = ffa_partition_info_get, .mode_32bit_set = ffa_mode_32bit_set, .sync_send_receive = ffa_sync_send_receive, + .memory_reclaim = ffa_memory_reclaim, + .memory_share = ffa_memory_share, }; const struct ffa_dev_ops *ffa_dev_ops_get(struct ffa_device *dev) diff --git a/include/linux/arm_ffa.h b/include/linux/arm_ffa.h index d672673fc621..505c679b6a9b 100644 --- a/include/linux/arm_ffa.h +++ b/include/linux/arm_ffa.h @@ -116,6 +116,142 @@ struct ffa_send_direct_data { unsigned long data4; /* w7/x7 */ }; +struct ffa_mem_region_addr_range { + /* The base IPA of the constituent memory region, aligned to 4 kiB */ + u64 address; + /* The number of 4 kiB pages in the constituent memory region. */ + u32 pg_cnt; + u32 reserved; +}; + +struct ffa_composite_mem_region { + /* + * The total number of 4 kiB pages included in this memory region. This + * must be equal to the sum of page counts specified in each + * `struct ffa_mem_region_addr_range`. + */ + u32 total_pg_cnt; + /* The number of constituents included in this memory region range */ + u32 addr_range_cnt; + u64 reserved; + /** An array of `addr_range_cnt` memory region constituents. */ + struct ffa_mem_region_addr_range constituents[]; +}; + +struct ffa_mem_region_attributes { + /* The ID of the VM to which the memory is being given or shared. */ + u16 receiver; + /* + * The permissions with which the memory region should be mapped in the + * receiver's page table. + */ +#define FFA_MEM_EXEC BIT(3) +#define FFA_MEM_NO_EXEC BIT(2) +#define FFA_MEM_RW BIT(1) +#define FFA_MEM_RO BIT(0) + u8 attrs; + /* + * Flags used during FFA_MEM_RETRIEVE_REQ and FFA_MEM_RETRIEVE_RESP + * for memory regions with multiple borrowers. + */ +#define FFA_MEM_RETRIEVE_SELF_BORROWER BIT(0) + u8 flag; + u32 composite_off; + /* + * Offset in bytes from the start of the outer `ffa_memory_region` to + * an `struct ffa_mem_region_addr_range`. + */ + u64 reserved; +}; + +struct ffa_mem_region { + /* The ID of the VM/owner which originally sent the memory region */ + u16 sender_id; +#define FFA_MEM_NORMAL BIT(5) +#define FFA_MEM_DEVICE BIT(4) + +#define FFA_MEM_WRITE_BACK (3 << 2) +#define FFA_MEM_NON_CACHEABLE (1 << 2) + +#define FFA_DEV_nGnRnE (0 << 2) +#define FFA_DEV_nGnRE (1 << 2) +#define FFA_DEV_nGRE (2 << 2) +#define FFA_DEV_GRE (3 << 2) + +#define FFA_MEM_NON_SHAREABLE (0) +#define FFA_MEM_OUTER_SHAREABLE (2) +#define FFA_MEM_INNER_SHAREABLE (3) + u8 attributes; + u8 reserved_0; +/* + * Clear memory region contents after unmapping it from the sender and + * before mapping it for any receiver. + */ +#define FFA_MEM_CLEAR BIT(0) +/* + * Whether the hypervisor may time slice the memory sharing or retrieval + * operation. + */ +#define FFA_TIME_SLICE_ENABLE BIT(1) + +#define FFA_MEM_RETRIEVE_TYPE_IN_RESP (0 << 3) +#define FFA_MEM_RETRIEVE_TYPE_SHARE (1 << 3) +#define FFA_MEM_RETRIEVE_TYPE_LEND (2 << 3) +#define FFA_MEM_RETRIEVE_TYPE_DONATE (3 << 3) + +#define FFA_MEM_RETRIEVE_ADDR_ALIGN_HINT BIT(9) +#define FFA_MEM_RETRIEVE_ADDR_ALIGN(x) ((x) << 5) + /* Flags to control behaviour of the transaction. */ + u32 flags; +#define HANDLE_LOW_MASK GENMASK_ULL(31, 0) +#define HANDLE_HIGH_MASK GENMASK_ULL(63, 32) +#define HANDLE_LOW(x) ((u32)(FIELD_GET(HANDLE_LOW_MASK, (x)))) +#define HANDLE_HIGH(x) ((u32)(FIELD_GET(HANDLE_HIGH_MASK, (x)))) + +#define PACK_HANDLE(l, h) \ + (FIELD_PREP(HANDLE_LOW_MASK, (l)) | FIELD_PREP(HANDLE_HIGH_MASK, (h))) + /* + * A globally-unique ID assigned by the hypervisor for a region + * of memory being sent between VMs. + */ + u64 handle; + /* + * An implementation defined value associated with the receiver and the + * memory region. + */ + u64 tag; + u32 reserved_1; + /* + * The number of `ffa_mem_region_attributes` entries included in this + * transaction. + */ + u32 ep_count; + /* + * An array of endpoint memory access descriptors. + * Each one specifies a memory region offset, an endpoint and the + * attributes with which this memory region should be mapped in that + * endpoint's page table. + */ + struct ffa_mem_region_attributes ep_mem_access[]; +}; + +#define COMPOSITE_OFFSET(x) \ + (offsetof(struct ffa_mem_region, ep_mem_access[x])) +#define CONSTITUENTS_OFFSET(x) \ + (offsetof(struct ffa_composite_mem_region, constituents[x])) +#define COMPOSITE_CONSTITUENTS_OFFSET(x, y) \ + (COMPOSITE_OFFSET(x) + CONSTITUENTS_OFFSET(y)) + +struct ffa_mem_ops_args { + bool use_txbuf; + u32 nattrs; + u32 flags; + u64 tag; + u64 g_handle; + struct scatterlist *sg; + struct ffa_mem_region_attributes *attrs; +}; + struct ffa_dev_ops { u32 (*api_version_get)(void); int (*partition_info_get)(const char *uuid_str, @@ -123,6 +259,9 @@ struct ffa_dev_ops { void (*mode_32bit_set)(struct ffa_device *dev); int (*sync_send_receive)(struct ffa_device *dev, struct ffa_send_direct_data *data); + int (*memory_reclaim)(u64 g_handle, u32 flags); + int (*memory_share)(struct ffa_device *dev, + struct ffa_mem_ops_args *args); }; #endif /* _LINUX_ARM_FFA_H */ -- cgit v1.2.3 From 30af8513bdb59a3e57f58f51c340130b6328b59e Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 10 May 2021 12:00:42 +0800 Subject: dt-bindings: power: add defines for i.MX8MM power domains Adding defines for i.MX8MM GPC power domains. Tested-by: Frieder Schrempf Acked-by: Rob Herring Signed-off-by: Lucas Stach Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- .../devicetree/bindings/power/fsl,imx-gpcv2.yaml | 2 ++ include/dt-bindings/power/imx8mm-power.h | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 include/dt-bindings/power/imx8mm-power.h (limited to 'include') diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml index a96e6dbf1858..cac2869af3d0 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml @@ -26,6 +26,7 @@ properties: enum: - fsl,imx7d-gpc - fsl,imx8mq-gpc + - fsl,imx8mm-gpc reg: maxItems: 1 @@ -54,6 +55,7 @@ properties: Power domain index. Valid values are defined in include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc + include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc maxItems: 1 clocks: diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h new file mode 100644 index 000000000000..fc9c2e16aadc --- /dev/null +++ b/include/dt-bindings/power/imx8mm-power.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Pengutronix, Lucas Stach + */ + +#ifndef __DT_BINDINGS_IMX8MM_POWER_H__ +#define __DT_BINDINGS_IMX8MM_POWER_H__ + +#define IMX8MM_POWER_DOMAIN_HSIOMIX 0 +#define IMX8MM_POWER_DOMAIN_PCIE 1 +#define IMX8MM_POWER_DOMAIN_OTG1 2 +#define IMX8MM_POWER_DOMAIN_OTG2 3 +#define IMX8MM_POWER_DOMAIN_GPUMIX 4 +#define IMX8MM_POWER_DOMAIN_GPU 5 +#define IMX8MM_POWER_DOMAIN_VPUMIX 6 +#define IMX8MM_POWER_DOMAIN_VPUG1 7 +#define IMX8MM_POWER_DOMAIN_VPUG2 8 +#define IMX8MM_POWER_DOMAIN_VPUH1 9 +#define IMX8MM_POWER_DOMAIN_DISPMIX 10 +#define IMX8MM_POWER_DOMAIN_MIPI 11 + +#endif -- cgit v1.2.3 From 8c84a7335e71de1f045247eb035d55712e13222a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 1 Jun 2021 18:06:07 +0200 Subject: memory: renesas-rpc-if: correct whitespace Use spaces instead of tabs as word separator. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210601160608.312446-1-krzysztof.kozlowski@canonical.com --- include/memory/renesas-rpc-if.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/memory/renesas-rpc-if.h b/include/memory/renesas-rpc-if.h index 14cfd036268a..e3e770f76f34 100644 --- a/include/memory/renesas-rpc-if.h +++ b/include/memory/renesas-rpc-if.h @@ -19,7 +19,7 @@ enum rpcif_data_dir { RPCIF_DATA_OUT, }; -struct rpcif_op { +struct rpcif_op { struct { u8 buswidth; u8 opcode; @@ -57,7 +57,7 @@ struct rpcif_op { } data; }; -struct rpcif { +struct rpcif { struct device *dev; void __iomem *dirmap; struct regmap *regmap; @@ -76,7 +76,7 @@ struct rpcif { u32 ddr; /* DRDRENR or SMDRENR */ }; -int rpcif_sw_init(struct rpcif *rpc, struct device *dev); +int rpcif_sw_init(struct rpcif *rpc, struct device *dev); void rpcif_hw_init(struct rpcif *rpc, bool hyperflash); void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs, size_t *len); -- cgit v1.2.3 From 4f1ac76e5ed9436ff3cd72e308527fd1e90b193a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 2 Jun 2021 18:32:51 +0200 Subject: memory: tegra: Consolidate register fields Subsequent patches will add more register fields to the tegra_mc_client structure, so consolidate all register field definitions into a common sub-structure for coherency. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210602163302.120041-2-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/iommu/tegra-smmu.c | 16 +- drivers/memory/tegra/mc.c | 10 +- drivers/memory/tegra/tegra114.c | 1244 +++++++++++++++++++--------------- drivers/memory/tegra/tegra124.c | 1304 +++++++++++++++++++---------------- drivers/memory/tegra/tegra210.c | 1432 +++++++++++++++++++++------------------ drivers/memory/tegra/tegra30.c | 1291 +++++++++++++++++++---------------- include/soc/tegra/mc.h | 30 +- 7 files changed, 2933 insertions(+), 2394 deletions(-) (limited to 'include') diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 1e98dc63ad13..0a281833f611 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -376,9 +376,9 @@ static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, if (client->swgroup != swgroup) continue; - value = smmu_readl(smmu, client->smmu.reg); - value |= BIT(client->smmu.bit); - smmu_writel(smmu, value, client->smmu.reg); + value = smmu_readl(smmu, client->regs.smmu.reg); + value |= BIT(client->regs.smmu.bit); + smmu_writel(smmu, value, client->regs.smmu.reg); } } @@ -404,9 +404,9 @@ static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup, if (client->swgroup != swgroup) continue; - value = smmu_readl(smmu, client->smmu.reg); - value &= ~BIT(client->smmu.bit); - smmu_writel(smmu, value, client->smmu.reg); + value = smmu_readl(smmu, client->regs.smmu.reg); + value &= ~BIT(client->regs.smmu.bit); + smmu_writel(smmu, value, client->regs.smmu.reg); } } @@ -1042,9 +1042,9 @@ static int tegra_smmu_clients_show(struct seq_file *s, void *data) const struct tegra_mc_client *client = &smmu->soc->clients[i]; const char *status; - value = smmu_readl(smmu, client->smmu.reg); + value = smmu_readl(smmu, client->regs.smmu.reg); - if (value & BIT(client->smmu.bit)) + if (value & BIT(client->regs.smmu.bit)) status = "yes"; else status = "no"; diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index e58c3e5baea0..b7e104bf6614 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -316,13 +316,13 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) /* write latency allowance defaults */ for (i = 0; i < mc->soc->num_clients; i++) { - const struct tegra_mc_la *la = &mc->soc->clients[i].la; + const struct tegra_mc_client *client = &mc->soc->clients[i]; u32 value; - value = mc_readl(mc, la->reg); - value &= ~(la->mask << la->shift); - value |= (la->def & la->mask) << la->shift; - mc_writel(mc, value, la->reg); + value = mc_readl(mc, client->regs.la.reg); + value &= ~(client->regs.la.mask << client->regs.la.shift); + value |= (client->regs.la.def & client->regs.la.mask) << client->regs.la.shift; + mc_writel(mc, value, client->regs.la.reg); } /* latch new values */ diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c index ed376ba2d2fe..1f2054d34bf5 100644 --- a/drivers/memory/tegra/tegra114.c +++ b/drivers/memory/tegra/tegra114.c @@ -15,883 +15,1013 @@ static const struct tegra_mc_client tegra114_mc_clients[] = { .id = 0x00, .name = "ptcr", .swgroup = TEGRA_SWGROUP_PTC, - .la = { - .reg = 0x34c, - .shift = 0, - .mask = 0xff, - .def = 0x0, + .regs = { + .la = { + .reg = 0x34c, + .shift = 0, + .mask = 0xff, + .def = 0x0, + }, }, }, { .id = 0x01, .name = "display0a", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 1, - }, - .la = { - .reg = 0x2e8, - .shift = 0, - .mask = 0xff, - .def = 0x4e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 1, + }, + .la = { + .reg = 0x2e8, + .shift = 0, + .mask = 0xff, + .def = 0x4e, + }, }, }, { .id = 0x02, .name = "display0ab", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 2, - }, - .la = { - .reg = 0x2f4, - .shift = 0, - .mask = 0xff, - .def = 0x4e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 2, + }, + .la = { + .reg = 0x2f4, + .shift = 0, + .mask = 0xff, + .def = 0x4e, + }, }, }, { .id = 0x03, .name = "display0b", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 3, - }, - .la = { - .reg = 0x2e8, - .shift = 16, - .mask = 0xff, - .def = 0x4e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 3, + }, + .la = { + .reg = 0x2e8, + .shift = 16, + .mask = 0xff, + .def = 0x4e, + }, }, }, { .id = 0x04, .name = "display0bb", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 4, - }, - .la = { - .reg = 0x2f4, - .shift = 16, - .mask = 0xff, - .def = 0x4e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 4, + }, + .la = { + .reg = 0x2f4, + .shift = 16, + .mask = 0xff, + .def = 0x4e, + }, }, }, { .id = 0x05, .name = "display0c", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 5, - }, - .la = { - .reg = 0x2ec, - .shift = 0, - .mask = 0xff, - .def = 0x4e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 5, + }, + .la = { + .reg = 0x2ec, + .shift = 0, + .mask = 0xff, + .def = 0x4e, + }, }, }, { .id = 0x06, .name = "display0cb", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 6, - }, - .la = { - .reg = 0x2f8, - .shift = 0, - .mask = 0xff, - .def = 0x4e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 6, + }, + .la = { + .reg = 0x2f8, + .shift = 0, + .mask = 0xff, + .def = 0x4e, + }, }, }, { .id = 0x09, .name = "eppup", .swgroup = TEGRA_SWGROUP_EPP, - .smmu = { - .reg = 0x228, - .bit = 9, - }, - .la = { - .reg = 0x300, - .shift = 0, - .mask = 0xff, - .def = 0x33, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 9, + }, + .la = { + .reg = 0x300, + .shift = 0, + .mask = 0xff, + .def = 0x33, + }, }, }, { .id = 0x0a, .name = "g2pr", .swgroup = TEGRA_SWGROUP_G2, - .smmu = { - .reg = 0x228, - .bit = 10, - }, - .la = { - .reg = 0x308, - .shift = 0, - .mask = 0xff, - .def = 0x09, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 10, + }, + .la = { + .reg = 0x308, + .shift = 0, + .mask = 0xff, + .def = 0x09, + }, }, }, { .id = 0x0b, .name = "g2sr", .swgroup = TEGRA_SWGROUP_G2, - .smmu = { - .reg = 0x228, - .bit = 11, - }, - .la = { - .reg = 0x308, - .shift = 16, - .mask = 0xff, - .def = 0x09, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 11, + }, + .la = { + .reg = 0x308, + .shift = 16, + .mask = 0xff, + .def = 0x09, + }, }, }, { .id = 0x0f, .name = "avpcarm7r", .swgroup = TEGRA_SWGROUP_AVPC, - .smmu = { - .reg = 0x228, - .bit = 15, - }, - .la = { - .reg = 0x2e4, - .shift = 0, - .mask = 0xff, - .def = 0x04, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 15, + }, + .la = { + .reg = 0x2e4, + .shift = 0, + .mask = 0xff, + .def = 0x04, + }, }, }, { .id = 0x10, .name = "displayhc", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 16, - }, - .la = { - .reg = 0x2f0, - .shift = 0, - .mask = 0xff, - .def = 0x68, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 16, + }, + .la = { + .reg = 0x2f0, + .shift = 0, + .mask = 0xff, + .def = 0x68, + }, }, }, { .id = 0x11, .name = "displayhcb", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 17, - }, - .la = { - .reg = 0x2fc, - .shift = 0, - .mask = 0xff, - .def = 0x68, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 17, + }, + .la = { + .reg = 0x2fc, + .shift = 0, + .mask = 0xff, + .def = 0x68, + }, }, }, { .id = 0x12, .name = "fdcdrd", .swgroup = TEGRA_SWGROUP_NV, - .smmu = { - .reg = 0x228, - .bit = 18, - }, - .la = { - .reg = 0x334, - .shift = 0, - .mask = 0xff, - .def = 0x0c, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 18, + }, + .la = { + .reg = 0x334, + .shift = 0, + .mask = 0xff, + .def = 0x0c, + }, }, }, { .id = 0x13, .name = "fdcdrd2", .swgroup = TEGRA_SWGROUP_NV, - .smmu = { - .reg = 0x228, - .bit = 19, - }, - .la = { - .reg = 0x33c, - .shift = 0, - .mask = 0xff, - .def = 0x0c, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 19, + }, + .la = { + .reg = 0x33c, + .shift = 0, + .mask = 0xff, + .def = 0x0c, + }, }, }, { .id = 0x14, .name = "g2dr", .swgroup = TEGRA_SWGROUP_G2, - .smmu = { - .reg = 0x228, - .bit = 20, - }, - .la = { - .reg = 0x30c, - .shift = 0, - .mask = 0xff, - .def = 0x0a, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 20, + }, + .la = { + .reg = 0x30c, + .shift = 0, + .mask = 0xff, + .def = 0x0a, + }, }, }, { .id = 0x15, .name = "hdar", .swgroup = TEGRA_SWGROUP_HDA, - .smmu = { - .reg = 0x228, - .bit = 21, - }, - .la = { - .reg = 0x318, - .shift = 0, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 21, + }, + .la = { + .reg = 0x318, + .shift = 0, + .mask = 0xff, + .def = 0xff, + }, }, }, { .id = 0x16, .name = "host1xdmar", .swgroup = TEGRA_SWGROUP_HC, - .smmu = { - .reg = 0x228, - .bit = 22, - }, - .la = { - .reg = 0x310, - .shift = 0, - .mask = 0xff, - .def = 0x10, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 22, + }, + .la = { + .reg = 0x310, + .shift = 0, + .mask = 0xff, + .def = 0x10, + }, }, }, { .id = 0x17, .name = "host1xr", .swgroup = TEGRA_SWGROUP_HC, - .smmu = { - .reg = 0x228, - .bit = 23, - }, - .la = { - .reg = 0x310, - .shift = 16, - .mask = 0xff, - .def = 0xa5, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 23, + }, + .la = { + .reg = 0x310, + .shift = 16, + .mask = 0xff, + .def = 0xa5, + }, }, }, { .id = 0x18, .name = "idxsrd", .swgroup = TEGRA_SWGROUP_NV, - .smmu = { - .reg = 0x228, - .bit = 24, - }, - .la = { - .reg = 0x334, - .shift = 16, - .mask = 0xff, - .def = 0x0b, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 24, + }, + .la = { + .reg = 0x334, + .shift = 16, + .mask = 0xff, + .def = 0x0b, + }, }, }, { .id = 0x1c, .name = "msencsrd", .swgroup = TEGRA_SWGROUP_MSENC, - .smmu = { - .reg = 0x228, - .bit = 28, - }, - .la = { - .reg = 0x328, - .shift = 0, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 28, + }, + .la = { + .reg = 0x328, + .shift = 0, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x1d, .name = "ppcsahbdmar", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x228, - .bit = 29, - }, - .la = { - .reg = 0x344, - .shift = 0, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 29, + }, + .la = { + .reg = 0x344, + .shift = 0, + .mask = 0xff, + .def = 0x50, + }, }, }, { .id = 0x1e, .name = "ppcsahbslvr", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x228, - .bit = 30, - }, - .la = { - .reg = 0x344, - .shift = 16, - .mask = 0xff, - .def = 0xe8, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 30, + }, + .la = { + .reg = 0x344, + .shift = 16, + .mask = 0xff, + .def = 0xe8, + }, }, }, { .id = 0x20, .name = "texl2srd", .swgroup = TEGRA_SWGROUP_NV, - .smmu = { - .reg = 0x22c, - .bit = 0, - }, - .la = { - .reg = 0x338, - .shift = 0, - .mask = 0xff, - .def = 0x0c, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 0, + }, + .la = { + .reg = 0x338, + .shift = 0, + .mask = 0xff, + .def = 0x0c, + }, }, }, { .id = 0x22, .name = "vdebsevr", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 2, - }, - .la = { - .reg = 0x354, - .shift = 0, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 2, + }, + .la = { + .reg = 0x354, + .shift = 0, + .mask = 0xff, + .def = 0xff, + }, }, }, { .id = 0x23, .name = "vdember", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 3, - }, - .la = { - .reg = 0x354, - .shift = 16, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 3, + }, + .la = { + .reg = 0x354, + .shift = 16, + .mask = 0xff, + .def = 0xff, + }, }, }, { .id = 0x24, .name = "vdemcer", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 4, - }, - .la = { - .reg = 0x358, - .shift = 0, - .mask = 0xff, - .def = 0xb8, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 4, + }, + .la = { + .reg = 0x358, + .shift = 0, + .mask = 0xff, + .def = 0xb8, + }, }, }, { .id = 0x25, .name = "vdetper", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 5, - }, - .la = { - .reg = 0x358, - .shift = 16, - .mask = 0xff, - .def = 0xee, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 5, + }, + .la = { + .reg = 0x358, + .shift = 16, + .mask = 0xff, + .def = 0xee, + }, }, }, { .id = 0x26, .name = "mpcorelpr", .swgroup = TEGRA_SWGROUP_MPCORELP, - .la = { - .reg = 0x324, - .shift = 0, - .mask = 0xff, - .def = 0x04, + .regs = { + .la = { + .reg = 0x324, + .shift = 0, + .mask = 0xff, + .def = 0x04, + }, }, }, { .id = 0x27, .name = "mpcorer", .swgroup = TEGRA_SWGROUP_MPCORE, - .la = { - .reg = 0x320, - .shift = 0, - .mask = 0xff, - .def = 0x04, + .regs = { + .la = { + .reg = 0x320, + .shift = 0, + .mask = 0xff, + .def = 0x04, + }, }, }, { .id = 0x28, .name = "eppu", .swgroup = TEGRA_SWGROUP_EPP, - .smmu = { - .reg = 0x22c, - .bit = 8, - }, - .la = { - .reg = 0x300, - .shift = 16, - .mask = 0xff, - .def = 0x33, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 8, + }, + .la = { + .reg = 0x300, + .shift = 16, + .mask = 0xff, + .def = 0x33, + }, }, }, { .id = 0x29, .name = "eppv", .swgroup = TEGRA_SWGROUP_EPP, - .smmu = { - .reg = 0x22c, - .bit = 9, - }, - .la = { - .reg = 0x304, - .shift = 0, - .mask = 0xff, - .def = 0x6c, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 9, + }, + .la = { + .reg = 0x304, + .shift = 0, + .mask = 0xff, + .def = 0x6c, + }, }, }, { .id = 0x2a, .name = "eppy", .swgroup = TEGRA_SWGROUP_EPP, - .smmu = { - .reg = 0x22c, - .bit = 10, - }, - .la = { - .reg = 0x304, - .shift = 16, - .mask = 0xff, - .def = 0x6c, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 10, + }, + .la = { + .reg = 0x304, + .shift = 16, + .mask = 0xff, + .def = 0x6c, + }, }, }, { .id = 0x2b, .name = "msencswr", .swgroup = TEGRA_SWGROUP_MSENC, - .smmu = { - .reg = 0x22c, - .bit = 11, - }, - .la = { - .reg = 0x328, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 11, + }, + .la = { + .reg = 0x328, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x2c, .name = "viwsb", .swgroup = TEGRA_SWGROUP_VI, - .smmu = { - .reg = 0x22c, - .bit = 12, - }, - .la = { - .reg = 0x364, - .shift = 0, - .mask = 0xff, - .def = 0x47, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 12, + }, + .la = { + .reg = 0x364, + .shift = 0, + .mask = 0xff, + .def = 0x47, + }, }, }, { .id = 0x2d, .name = "viwu", .swgroup = TEGRA_SWGROUP_VI, - .smmu = { - .reg = 0x22c, - .bit = 13, - }, - .la = { - .reg = 0x368, - .shift = 0, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 13, + }, + .la = { + .reg = 0x368, + .shift = 0, + .mask = 0xff, + .def = 0xff, + }, }, }, { .id = 0x2e, .name = "viwv", .swgroup = TEGRA_SWGROUP_VI, - .smmu = { - .reg = 0x22c, - .bit = 14, - }, - .la = { - .reg = 0x368, - .shift = 16, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 14, + }, + .la = { + .reg = 0x368, + .shift = 16, + .mask = 0xff, + .def = 0xff, + }, }, }, { .id = 0x2f, .name = "viwy", .swgroup = TEGRA_SWGROUP_VI, - .smmu = { - .reg = 0x22c, - .bit = 15, - }, - .la = { - .reg = 0x36c, - .shift = 0, - .mask = 0xff, - .def = 0x47, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 15, + }, + .la = { + .reg = 0x36c, + .shift = 0, + .mask = 0xff, + .def = 0x47, + }, }, }, { .id = 0x30, .name = "g2dw", .swgroup = TEGRA_SWGROUP_G2, - .smmu = { - .reg = 0x22c, - .bit = 16, - }, - .la = { - .reg = 0x30c, - .shift = 16, - .mask = 0xff, - .def = 0x9, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 16, + }, + .la = { + .reg = 0x30c, + .shift = 16, + .mask = 0xff, + .def = 0x9, + }, }, }, { .id = 0x32, .name = "avpcarm7w", .swgroup = TEGRA_SWGROUP_AVPC, - .smmu = { - .reg = 0x22c, - .bit = 18, - }, - .la = { - .reg = 0x2e4, - .shift = 16, - .mask = 0xff, - .def = 0x0e, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 18, + }, + .la = { + .reg = 0x2e4, + .shift = 16, + .mask = 0xff, + .def = 0x0e, + }, }, }, { .id = 0x33, .name = "fdcdwr", .swgroup = TEGRA_SWGROUP_NV, - .smmu = { - .reg = 0x22c, - .bit = 19, - }, - .la = { - .reg = 0x338, - .shift = 16, - .mask = 0xff, - .def = 0x10, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 19, + }, + .la = { + .reg = 0x338, + .shift = 16, + .mask = 0xff, + .def = 0x10, + }, }, }, { .id = 0x34, .name = "fdcdwr2", .swgroup = TEGRA_SWGROUP_NV, - .smmu = { - .reg = 0x22c, - .bit = 20, - }, - .la = { - .reg = 0x340, - .shift = 0, - .mask = 0xff, - .def = 0x10, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 20, + }, + .la = { + .reg = 0x340, + .shift = 0, + .mask = 0xff, + .def = 0x10, + }, }, }, { .id = 0x35, .name = "hdaw", .swgroup = TEGRA_SWGROUP_HDA, - .smmu = { - .reg = 0x22c, - .bit = 21, - }, - .la = { - .reg = 0x318, - .shift = 16, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 21, + }, + .la = { + .reg = 0x318, + .shift = 16, + .mask = 0xff, + .def = 0xff, + }, }, }, { .id = 0x36, .name = "host1xw", .swgroup = TEGRA_SWGROUP_HC, - .smmu = { - .reg = 0x22c, - .bit = 22, - }, - .la = { - .reg = 0x314, - .shift = 0, - .mask = 0xff, - .def = 0x25, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 22, + }, + .la = { + .reg = 0x314, + .shift = 0, + .mask = 0xff, + .def = 0x25, + }, }, }, { .id = 0x37, .name = "ispw", .swgroup = TEGRA_SWGROUP_ISP, - .smmu = { - .reg = 0x22c, - .bit = 23, - }, - .la = { - .reg = 0x31c, - .shift = 0, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 23, + }, + .la = { + .reg = 0x31c, + .shift = 0, + .mask = 0xff, + .def = 0xff, + }, }, }, { .id = 0x38, .name = "mpcorelpw", .swgroup = TEGRA_SWGROUP_MPCORELP, - .la = { - .reg = 0x324, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .la = { + .reg = 0x324, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x39, .name = "mpcorew", .swgroup = TEGRA_SWGROUP_MPCORE, - .la = { - .reg = 0x320, - .shift = 16, - .mask = 0xff, - .def = 0x0e, + .regs = { + .la = { + .reg = 0x320, + .shift = 16, + .mask = 0xff, + .def = 0x0e, + }, }, }, { .id = 0x3b, .name = "ppcsahbdmaw", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x22c, - .bit = 27, - }, - .la = { - .reg = 0x348, - .shift = 0, - .mask = 0xff, - .def = 0xa5, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 27, + }, + .la = { + .reg = 0x348, + .shift = 0, + .mask = 0xff, + .def = 0xa5, + }, }, }, { .id = 0x3c, .name = "ppcsahbslvw", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x22c, - .bit = 28, - }, - .la = { - .reg = 0x348, - .shift = 16, - .mask = 0xff, - .def = 0xe8, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 28, + }, + .la = { + .reg = 0x348, + .shift = 16, + .mask = 0xff, + .def = 0xe8, + }, }, }, { .id = 0x3e, .name = "vdebsevw", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 30, - }, - .la = { - .reg = 0x35c, - .shift = 0, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 30, + }, + .la = { + .reg = 0x35c, + .shift = 0, + .mask = 0xff, + .def = 0xff, + }, }, }, { .id = 0x3f, .name = "vdedbgw", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 31, - }, - .la = { - .reg = 0x35c, - .shift = 16, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 31, + }, + .la = { + .reg = 0x35c, + .shift = 16, + .mask = 0xff, + .def = 0xff, + }, }, }, { .id = 0x40, .name = "vdembew", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x230, - .bit = 0, - }, - .la = { - .reg = 0x360, - .shift = 0, - .mask = 0xff, - .def = 0x89, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 0, + }, + .la = { + .reg = 0x360, + .shift = 0, + .mask = 0xff, + .def = 0x89, + }, }, }, { .id = 0x41, .name = "vdetpmw", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x230, - .bit = 1, - }, - .la = { - .reg = 0x360, - .shift = 16, - .mask = 0xff, - .def = 0x59, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 1, + }, + .la = { + .reg = 0x360, + .shift = 16, + .mask = 0xff, + .def = 0x59, + }, }, }, { .id = 0x4a, .name = "xusb_hostr", .swgroup = TEGRA_SWGROUP_XUSB_HOST, - .smmu = { - .reg = 0x230, - .bit = 10, - }, - .la = { - .reg = 0x37c, - .shift = 0, - .mask = 0xff, - .def = 0xa5, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 10, + }, + .la = { + .reg = 0x37c, + .shift = 0, + .mask = 0xff, + .def = 0xa5, + }, }, }, { .id = 0x4b, .name = "xusb_hostw", .swgroup = TEGRA_SWGROUP_XUSB_HOST, - .smmu = { - .reg = 0x230, - .bit = 11, - }, - .la = { - .reg = 0x37c, - .shift = 16, - .mask = 0xff, - .def = 0xa5, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 11, + }, + .la = { + .reg = 0x37c, + .shift = 16, + .mask = 0xff, + .def = 0xa5, + }, }, }, { .id = 0x4c, .name = "xusb_devr", .swgroup = TEGRA_SWGROUP_XUSB_DEV, - .smmu = { - .reg = 0x230, - .bit = 12, - }, - .la = { - .reg = 0x380, - .shift = 0, - .mask = 0xff, - .def = 0xa5, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 12, + }, + .la = { + .reg = 0x380, + .shift = 0, + .mask = 0xff, + .def = 0xa5, + }, }, }, { .id = 0x4d, .name = "xusb_devw", .swgroup = TEGRA_SWGROUP_XUSB_DEV, - .smmu = { - .reg = 0x230, - .bit = 13, - }, - .la = { - .reg = 0x380, - .shift = 16, - .mask = 0xff, - .def = 0xa5, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 13, + }, + .la = { + .reg = 0x380, + .shift = 16, + .mask = 0xff, + .def = 0xa5, + }, }, }, { .id = 0x4e, .name = "fdcdwr3", .swgroup = TEGRA_SWGROUP_NV, - .smmu = { - .reg = 0x230, - .bit = 14, - }, - .la = { - .reg = 0x388, - .shift = 0, - .mask = 0xff, - .def = 0x10, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 14, + }, + .la = { + .reg = 0x388, + .shift = 0, + .mask = 0xff, + .def = 0x10, + }, }, }, { .id = 0x4f, .name = "fdcdrd3", .swgroup = TEGRA_SWGROUP_NV, - .smmu = { - .reg = 0x230, - .bit = 15, - }, - .la = { - .reg = 0x384, - .shift = 0, - .mask = 0xff, - .def = 0x0c, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 15, + }, + .la = { + .reg = 0x384, + .shift = 0, + .mask = 0xff, + .def = 0x0c, + }, }, }, { .id = 0x50, .name = "fdcwr4", .swgroup = TEGRA_SWGROUP_NV, - .smmu = { - .reg = 0x230, - .bit = 16, - }, - .la = { - .reg = 0x388, - .shift = 16, - .mask = 0xff, - .def = 0x10, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 16, + }, + .la = { + .reg = 0x388, + .shift = 16, + .mask = 0xff, + .def = 0x10, + }, }, }, { .id = 0x51, .name = "fdcrd4", .swgroup = TEGRA_SWGROUP_NV, - .smmu = { - .reg = 0x230, - .bit = 17, - }, - .la = { - .reg = 0x384, - .shift = 16, - .mask = 0xff, - .def = 0x0c, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 17, + }, + .la = { + .reg = 0x384, + .shift = 16, + .mask = 0xff, + .def = 0x0c, + }, }, }, { .id = 0x52, .name = "emucifr", .swgroup = TEGRA_SWGROUP_EMUCIF, - .la = { - .reg = 0x38c, - .shift = 0, - .mask = 0xff, - .def = 0x04, + .regs = { + .la = { + .reg = 0x38c, + .shift = 0, + .mask = 0xff, + .def = 0x04, + }, }, }, { .id = 0x53, .name = "emucifw", .swgroup = TEGRA_SWGROUP_EMUCIF, - .la = { - .reg = 0x38c, - .shift = 16, - .mask = 0xff, - .def = 0x0e, + .regs = { + .la = { + .reg = 0x38c, + .shift = 16, + .mask = 0xff, + .def = 0x0e, + }, }, }, { .id = 0x54, .name = "tsecsrd", .swgroup = TEGRA_SWGROUP_TSEC, - .smmu = { - .reg = 0x230, - .bit = 20, - }, - .la = { - .reg = 0x390, - .shift = 0, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 20, + }, + .la = { + .reg = 0x390, + .shift = 0, + .mask = 0xff, + .def = 0x50, + }, }, }, { .id = 0x55, .name = "tsecswr", .swgroup = TEGRA_SWGROUP_TSEC, - .smmu = { - .reg = 0x230, - .bit = 21, - }, - .la = { - .reg = 0x390, - .shift = 16, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 21, + }, + .la = { + .reg = 0x390, + .shift = 16, + .mask = 0xff, + .def = 0x50, + }, }, }, }; diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c index 459211f50c08..8a8485ceb789 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -16,921 +16,1055 @@ static const struct tegra_mc_client tegra124_mc_clients[] = { .id = 0x00, .name = "ptcr", .swgroup = TEGRA_SWGROUP_PTC, - .la = { - .reg = 0x34c, - .shift = 0, - .mask = 0xff, - .def = 0x0, + .regs = { + .la = { + .reg = 0x34c, + .shift = 0, + .mask = 0xff, + .def = 0x0, + }, }, }, { .id = 0x01, .name = "display0a", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 1, - }, - .la = { - .reg = 0x2e8, - .shift = 0, - .mask = 0xff, - .def = 0xc2, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 1, + }, + .la = { + .reg = 0x2e8, + .shift = 0, + .mask = 0xff, + .def = 0xc2, + }, }, }, { .id = 0x02, .name = "display0ab", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 2, - }, - .la = { - .reg = 0x2f4, - .shift = 0, - .mask = 0xff, - .def = 0xc6, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 2, + }, + .la = { + .reg = 0x2f4, + .shift = 0, + .mask = 0xff, + .def = 0xc6, + }, }, }, { .id = 0x03, .name = "display0b", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 3, - }, - .la = { - .reg = 0x2e8, - .shift = 16, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 3, + }, + .la = { + .reg = 0x2e8, + .shift = 16, + .mask = 0xff, + .def = 0x50, + }, }, }, { .id = 0x04, .name = "display0bb", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 4, - }, - .la = { - .reg = 0x2f4, - .shift = 16, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 4, + }, + .la = { + .reg = 0x2f4, + .shift = 16, + .mask = 0xff, + .def = 0x50, + }, }, }, { .id = 0x05, .name = "display0c", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 5, - }, - .la = { - .reg = 0x2ec, - .shift = 0, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 5, + }, + .la = { + .reg = 0x2ec, + .shift = 0, + .mask = 0xff, + .def = 0x50, + }, }, }, { .id = 0x06, .name = "display0cb", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 6, - }, - .la = { - .reg = 0x2f8, - .shift = 0, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 6, + }, + .la = { + .reg = 0x2f8, + .shift = 0, + .mask = 0xff, + .def = 0x50, + }, }, }, { .id = 0x0e, .name = "afir", .swgroup = TEGRA_SWGROUP_AFI, - .smmu = { - .reg = 0x228, - .bit = 14, - }, - .la = { - .reg = 0x2e0, - .shift = 0, - .mask = 0xff, - .def = 0x13, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 14, + }, + .la = { + .reg = 0x2e0, + .shift = 0, + .mask = 0xff, + .def = 0x13, + }, }, }, { .id = 0x0f, .name = "avpcarm7r", .swgroup = TEGRA_SWGROUP_AVPC, - .smmu = { - .reg = 0x228, - .bit = 15, - }, - .la = { - .reg = 0x2e4, - .shift = 0, - .mask = 0xff, - .def = 0x04, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 15, + }, + .la = { + .reg = 0x2e4, + .shift = 0, + .mask = 0xff, + .def = 0x04, + }, }, }, { .id = 0x10, .name = "displayhc", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 16, - }, - .la = { - .reg = 0x2f0, - .shift = 0, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 16, + }, + .la = { + .reg = 0x2f0, + .shift = 0, + .mask = 0xff, + .def = 0x50, + }, }, }, { .id = 0x11, .name = "displayhcb", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 17, - }, - .la = { - .reg = 0x2fc, - .shift = 0, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 17, + }, + .la = { + .reg = 0x2fc, + .shift = 0, + .mask = 0xff, + .def = 0x50, + }, }, }, { .id = 0x15, .name = "hdar", .swgroup = TEGRA_SWGROUP_HDA, - .smmu = { - .reg = 0x228, - .bit = 21, - }, - .la = { - .reg = 0x318, - .shift = 0, - .mask = 0xff, - .def = 0x24, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 21, + }, + .la = { + .reg = 0x318, + .shift = 0, + .mask = 0xff, + .def = 0x24, + }, }, }, { .id = 0x16, .name = "host1xdmar", .swgroup = TEGRA_SWGROUP_HC, - .smmu = { - .reg = 0x228, - .bit = 22, - }, - .la = { - .reg = 0x310, - .shift = 0, - .mask = 0xff, - .def = 0x1e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 22, + }, + .la = { + .reg = 0x310, + .shift = 0, + .mask = 0xff, + .def = 0x1e, + }, }, }, { .id = 0x17, .name = "host1xr", .swgroup = TEGRA_SWGROUP_HC, - .smmu = { - .reg = 0x228, - .bit = 23, - }, - .la = { - .reg = 0x310, - .shift = 16, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 23, + }, + .la = { + .reg = 0x310, + .shift = 16, + .mask = 0xff, + .def = 0x50, + }, }, }, { .id = 0x1c, .name = "msencsrd", .swgroup = TEGRA_SWGROUP_MSENC, - .smmu = { - .reg = 0x228, - .bit = 28, - }, - .la = { - .reg = 0x328, - .shift = 0, - .mask = 0xff, - .def = 0x23, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 28, + }, + .la = { + .reg = 0x328, + .shift = 0, + .mask = 0xff, + .def = 0x23, + }, }, }, { .id = 0x1d, .name = "ppcsahbdmar", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x228, - .bit = 29, - }, - .la = { - .reg = 0x344, - .shift = 0, - .mask = 0xff, - .def = 0x49, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 29, + }, + .la = { + .reg = 0x344, + .shift = 0, + .mask = 0xff, + .def = 0x49, + }, }, }, { .id = 0x1e, .name = "ppcsahbslvr", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x228, - .bit = 30, - }, - .la = { - .reg = 0x344, - .shift = 16, - .mask = 0xff, - .def = 0x1a, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 30, + }, + .la = { + .reg = 0x344, + .shift = 16, + .mask = 0xff, + .def = 0x1a, + }, }, }, { .id = 0x1f, .name = "satar", .swgroup = TEGRA_SWGROUP_SATA, - .smmu = { - .reg = 0x228, - .bit = 31, - }, - .la = { - .reg = 0x350, - .shift = 0, - .mask = 0xff, - .def = 0x65, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 31, + }, + .la = { + .reg = 0x350, + .shift = 0, + .mask = 0xff, + .def = 0x65, + }, }, }, { .id = 0x22, .name = "vdebsevr", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 2, - }, - .la = { - .reg = 0x354, - .shift = 0, - .mask = 0xff, - .def = 0x4f, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 2, + }, + .la = { + .reg = 0x354, + .shift = 0, + .mask = 0xff, + .def = 0x4f, + }, }, }, { .id = 0x23, .name = "vdember", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 3, - }, - .la = { - .reg = 0x354, - .shift = 16, - .mask = 0xff, - .def = 0x3d, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 3, + }, + .la = { + .reg = 0x354, + .shift = 16, + .mask = 0xff, + .def = 0x3d, + }, }, }, { .id = 0x24, .name = "vdemcer", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 4, - }, - .la = { - .reg = 0x358, - .shift = 0, - .mask = 0xff, - .def = 0x66, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 4, + }, + .la = { + .reg = 0x358, + .shift = 0, + .mask = 0xff, + .def = 0x66, + }, }, }, { .id = 0x25, .name = "vdetper", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 5, - }, - .la = { - .reg = 0x358, - .shift = 16, - .mask = 0xff, - .def = 0xa5, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 5, + }, + .la = { + .reg = 0x358, + .shift = 16, + .mask = 0xff, + .def = 0xa5, + }, }, }, { .id = 0x26, .name = "mpcorelpr", .swgroup = TEGRA_SWGROUP_MPCORELP, - .la = { - .reg = 0x324, - .shift = 0, - .mask = 0xff, - .def = 0x04, + .regs = { + .la = { + .reg = 0x324, + .shift = 0, + .mask = 0xff, + .def = 0x04, + }, }, }, { .id = 0x27, .name = "mpcorer", .swgroup = TEGRA_SWGROUP_MPCORE, - .la = { - .reg = 0x320, - .shift = 0, - .mask = 0xff, - .def = 0x04, + .regs = { + .la = { + .reg = 0x320, + .shift = 0, + .mask = 0xff, + .def = 0x04, + }, }, }, { .id = 0x2b, .name = "msencswr", .swgroup = TEGRA_SWGROUP_MSENC, - .smmu = { - .reg = 0x22c, - .bit = 11, - }, - .la = { - .reg = 0x328, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 11, + }, + .la = { + .reg = 0x328, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x31, .name = "afiw", .swgroup = TEGRA_SWGROUP_AFI, - .smmu = { - .reg = 0x22c, - .bit = 17, - }, - .la = { - .reg = 0x2e0, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 17, + }, + .la = { + .reg = 0x2e0, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x32, .name = "avpcarm7w", .swgroup = TEGRA_SWGROUP_AVPC, - .smmu = { - .reg = 0x22c, - .bit = 18, - }, - .la = { - .reg = 0x2e4, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 18, + }, + .la = { + .reg = 0x2e4, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x35, .name = "hdaw", .swgroup = TEGRA_SWGROUP_HDA, - .smmu = { - .reg = 0x22c, - .bit = 21, - }, - .la = { - .reg = 0x318, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 21, + }, + .la = { + .reg = 0x318, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x36, .name = "host1xw", .swgroup = TEGRA_SWGROUP_HC, - .smmu = { - .reg = 0x22c, - .bit = 22, - }, - .la = { - .reg = 0x314, - .shift = 0, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 22, + }, + .la = { + .reg = 0x314, + .shift = 0, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x38, .name = "mpcorelpw", .swgroup = TEGRA_SWGROUP_MPCORELP, - .la = { - .reg = 0x324, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .la = { + .reg = 0x324, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x39, .name = "mpcorew", .swgroup = TEGRA_SWGROUP_MPCORE, - .la = { - .reg = 0x320, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .la = { + .reg = 0x320, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x3b, .name = "ppcsahbdmaw", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x22c, - .bit = 27, - }, - .la = { - .reg = 0x348, - .shift = 0, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 27, + }, + .la = { + .reg = 0x348, + .shift = 0, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x3c, .name = "ppcsahbslvw", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x22c, - .bit = 28, - }, - .la = { - .reg = 0x348, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 28, + }, + .la = { + .reg = 0x348, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x3d, .name = "sataw", .swgroup = TEGRA_SWGROUP_SATA, - .smmu = { - .reg = 0x22c, - .bit = 29, - }, - .la = { - .reg = 0x350, - .shift = 16, - .mask = 0xff, - .def = 0x65, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 29, + }, + .la = { + .reg = 0x350, + .shift = 16, + .mask = 0xff, + .def = 0x65, + }, }, }, { .id = 0x3e, .name = "vdebsevw", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 30, - }, - .la = { - .reg = 0x35c, - .shift = 0, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 30, + }, + .la = { + .reg = 0x35c, + .shift = 0, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x3f, .name = "vdedbgw", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 31, - }, - .la = { - .reg = 0x35c, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 31, + }, + .la = { + .reg = 0x35c, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x40, .name = "vdembew", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x230, - .bit = 0, - }, - .la = { - .reg = 0x360, - .shift = 0, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 0, + }, + .la = { + .reg = 0x360, + .shift = 0, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x41, .name = "vdetpmw", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x230, - .bit = 1, - }, - .la = { - .reg = 0x360, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 1, + }, + .la = { + .reg = 0x360, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x44, .name = "ispra", .swgroup = TEGRA_SWGROUP_ISP2, - .smmu = { - .reg = 0x230, - .bit = 4, - }, - .la = { - .reg = 0x370, - .shift = 0, - .mask = 0xff, - .def = 0x18, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 4, + }, + .la = { + .reg = 0x370, + .shift = 0, + .mask = 0xff, + .def = 0x18, + }, }, }, { .id = 0x46, .name = "ispwa", .swgroup = TEGRA_SWGROUP_ISP2, - .smmu = { - .reg = 0x230, - .bit = 6, - }, - .la = { - .reg = 0x374, - .shift = 0, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 6, + }, + .la = { + .reg = 0x374, + .shift = 0, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x47, .name = "ispwb", .swgroup = TEGRA_SWGROUP_ISP2, - .smmu = { - .reg = 0x230, - .bit = 7, - }, - .la = { - .reg = 0x374, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 7, + }, + .la = { + .reg = 0x374, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x4a, .name = "xusb_hostr", .swgroup = TEGRA_SWGROUP_XUSB_HOST, - .smmu = { - .reg = 0x230, - .bit = 10, - }, - .la = { - .reg = 0x37c, - .shift = 0, - .mask = 0xff, - .def = 0x39, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 10, + }, + .la = { + .reg = 0x37c, + .shift = 0, + .mask = 0xff, + .def = 0x39, + }, }, }, { .id = 0x4b, .name = "xusb_hostw", .swgroup = TEGRA_SWGROUP_XUSB_HOST, - .smmu = { - .reg = 0x230, - .bit = 11, - }, - .la = { - .reg = 0x37c, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 11, + }, + .la = { + .reg = 0x37c, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x4c, .name = "xusb_devr", .swgroup = TEGRA_SWGROUP_XUSB_DEV, - .smmu = { - .reg = 0x230, - .bit = 12, - }, - .la = { - .reg = 0x380, - .shift = 0, - .mask = 0xff, - .def = 0x39, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 12, + }, + .la = { + .reg = 0x380, + .shift = 0, + .mask = 0xff, + .def = 0x39, + }, }, }, { .id = 0x4d, .name = "xusb_devw", .swgroup = TEGRA_SWGROUP_XUSB_DEV, - .smmu = { - .reg = 0x230, - .bit = 13, - }, - .la = { - .reg = 0x380, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 13, + }, + .la = { + .reg = 0x380, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x4e, .name = "isprab", .swgroup = TEGRA_SWGROUP_ISP2B, - .smmu = { - .reg = 0x230, - .bit = 14, - }, - .la = { - .reg = 0x384, - .shift = 0, - .mask = 0xff, - .def = 0x18, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 14, + }, + .la = { + .reg = 0x384, + .shift = 0, + .mask = 0xff, + .def = 0x18, + }, }, }, { .id = 0x50, .name = "ispwab", .swgroup = TEGRA_SWGROUP_ISP2B, - .smmu = { - .reg = 0x230, - .bit = 16, - }, - .la = { - .reg = 0x388, - .shift = 0, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 16, + }, + .la = { + .reg = 0x388, + .shift = 0, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x51, .name = "ispwbb", .swgroup = TEGRA_SWGROUP_ISP2B, - .smmu = { - .reg = 0x230, - .bit = 17, - }, - .la = { - .reg = 0x388, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 17, + }, + .la = { + .reg = 0x388, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x54, .name = "tsecsrd", .swgroup = TEGRA_SWGROUP_TSEC, - .smmu = { - .reg = 0x230, - .bit = 20, - }, - .la = { - .reg = 0x390, - .shift = 0, - .mask = 0xff, - .def = 0x9b, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 20, + }, + .la = { + .reg = 0x390, + .shift = 0, + .mask = 0xff, + .def = 0x9b, + }, }, }, { .id = 0x55, .name = "tsecswr", .swgroup = TEGRA_SWGROUP_TSEC, - .smmu = { - .reg = 0x230, - .bit = 21, - }, - .la = { - .reg = 0x390, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 21, + }, + .la = { + .reg = 0x390, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x56, .name = "a9avpscr", .swgroup = TEGRA_SWGROUP_A9AVP, - .smmu = { - .reg = 0x230, - .bit = 22, - }, - .la = { - .reg = 0x3a4, - .shift = 0, - .mask = 0xff, - .def = 0x04, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 22, + }, + .la = { + .reg = 0x3a4, + .shift = 0, + .mask = 0xff, + .def = 0x04, + }, }, }, { .id = 0x57, .name = "a9avpscw", .swgroup = TEGRA_SWGROUP_A9AVP, - .smmu = { - .reg = 0x230, - .bit = 23, - }, - .la = { - .reg = 0x3a4, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 23, + }, + .la = { + .reg = 0x3a4, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x58, .name = "gpusrd", .swgroup = TEGRA_SWGROUP_GPU, - .smmu = { - /* read-only */ - .reg = 0x230, - .bit = 24, - }, - .la = { - .reg = 0x3c8, - .shift = 0, - .mask = 0xff, - .def = 0x1a, + .regs = { + .smmu = { + /* read-only */ + .reg = 0x230, + .bit = 24, + }, + .la = { + .reg = 0x3c8, + .shift = 0, + .mask = 0xff, + .def = 0x1a, + }, }, }, { .id = 0x59, .name = "gpuswr", .swgroup = TEGRA_SWGROUP_GPU, - .smmu = { - /* read-only */ - .reg = 0x230, - .bit = 25, - }, - .la = { - .reg = 0x3c8, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + /* read-only */ + .reg = 0x230, + .bit = 25, + }, + .la = { + .reg = 0x3c8, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x5a, .name = "displayt", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x230, - .bit = 26, - }, - .la = { - .reg = 0x2f0, - .shift = 16, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 26, + }, + .la = { + .reg = 0x2f0, + .shift = 16, + .mask = 0xff, + .def = 0x50, + }, }, }, { .id = 0x60, .name = "sdmmcra", .swgroup = TEGRA_SWGROUP_SDMMC1A, - .smmu = { - .reg = 0x234, - .bit = 0, - }, - .la = { - .reg = 0x3b8, - .shift = 0, - .mask = 0xff, - .def = 0x49, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 0, + }, + .la = { + .reg = 0x3b8, + .shift = 0, + .mask = 0xff, + .def = 0x49, + }, }, }, { .id = 0x61, .name = "sdmmcraa", .swgroup = TEGRA_SWGROUP_SDMMC2A, - .smmu = { - .reg = 0x234, - .bit = 1, - }, - .la = { - .reg = 0x3bc, - .shift = 0, - .mask = 0xff, - .def = 0x49, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 1, + }, + .la = { + .reg = 0x3bc, + .shift = 0, + .mask = 0xff, + .def = 0x49, + }, }, }, { .id = 0x62, .name = "sdmmcr", .swgroup = TEGRA_SWGROUP_SDMMC3A, - .smmu = { - .reg = 0x234, - .bit = 2, - }, - .la = { - .reg = 0x3c0, - .shift = 0, - .mask = 0xff, - .def = 0x49, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 2, + }, + .la = { + .reg = 0x3c0, + .shift = 0, + .mask = 0xff, + .def = 0x49, + }, }, }, { .id = 0x63, .swgroup = TEGRA_SWGROUP_SDMMC4A, .name = "sdmmcrab", - .smmu = { - .reg = 0x234, - .bit = 3, - }, - .la = { - .reg = 0x3c4, - .shift = 0, - .mask = 0xff, - .def = 0x49, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 3, + }, + .la = { + .reg = 0x3c4, + .shift = 0, + .mask = 0xff, + .def = 0x49, + }, }, }, { .id = 0x64, .name = "sdmmcwa", .swgroup = TEGRA_SWGROUP_SDMMC1A, - .smmu = { - .reg = 0x234, - .bit = 4, - }, - .la = { - .reg = 0x3b8, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 4, + }, + .la = { + .reg = 0x3b8, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x65, .name = "sdmmcwaa", .swgroup = TEGRA_SWGROUP_SDMMC2A, - .smmu = { - .reg = 0x234, - .bit = 5, - }, - .la = { - .reg = 0x3bc, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 5, + }, + .la = { + .reg = 0x3bc, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x66, .name = "sdmmcw", .swgroup = TEGRA_SWGROUP_SDMMC3A, - .smmu = { - .reg = 0x234, - .bit = 6, - }, - .la = { - .reg = 0x3c0, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 6, + }, + .la = { + .reg = 0x3c0, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x67, .name = "sdmmcwab", .swgroup = TEGRA_SWGROUP_SDMMC4A, - .smmu = { - .reg = 0x234, - .bit = 7, - }, - .la = { - .reg = 0x3c4, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 7, + }, + .la = { + .reg = 0x3c4, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x6c, .name = "vicsrd", .swgroup = TEGRA_SWGROUP_VIC, - .smmu = { - .reg = 0x234, - .bit = 12, - }, - .la = { - .reg = 0x394, - .shift = 0, - .mask = 0xff, - .def = 0x1a, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 12, + }, + .la = { + .reg = 0x394, + .shift = 0, + .mask = 0xff, + .def = 0x1a, + }, }, }, { .id = 0x6d, .name = "vicswr", .swgroup = TEGRA_SWGROUP_VIC, - .smmu = { - .reg = 0x234, - .bit = 13, - }, - .la = { - .reg = 0x394, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 13, + }, + .la = { + .reg = 0x394, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x72, .name = "viw", .swgroup = TEGRA_SWGROUP_VI, - .smmu = { - .reg = 0x234, - .bit = 18, - }, - .la = { - .reg = 0x398, - .shift = 0, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 18, + }, + .la = { + .reg = 0x398, + .shift = 0, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x73, .name = "displayd", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x234, - .bit = 19, - }, - .la = { - .reg = 0x3c8, - .shift = 0, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 19, + }, + .la = { + .reg = 0x3c8, + .shift = 0, + .mask = 0xff, + .def = 0x50, + }, }, }, }; diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index b3bbc5a05ba1..08f3a08cd743 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -16,1005 +16,1149 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .id = 0x01, .name = "display0a", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 1, - }, - .la = { - .reg = 0x2e8, - .shift = 0, - .mask = 0xff, - .def = 0x1e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 1, + }, + .la = { + .reg = 0x2e8, + .shift = 0, + .mask = 0xff, + .def = 0x1e, + }, }, }, { .id = 0x02, .name = "display0ab", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 2, - }, - .la = { - .reg = 0x2f4, - .shift = 0, - .mask = 0xff, - .def = 0x1e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 2, + }, + .la = { + .reg = 0x2f4, + .shift = 0, + .mask = 0xff, + .def = 0x1e, + }, }, }, { .id = 0x03, .name = "display0b", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 3, - }, - .la = { - .reg = 0x2e8, - .shift = 16, - .mask = 0xff, - .def = 0x1e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 3, + }, + .la = { + .reg = 0x2e8, + .shift = 16, + .mask = 0xff, + .def = 0x1e, + }, }, }, { .id = 0x04, .name = "display0bb", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 4, - }, - .la = { - .reg = 0x2f4, - .shift = 16, - .mask = 0xff, - .def = 0x1e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 4, + }, + .la = { + .reg = 0x2f4, + .shift = 16, + .mask = 0xff, + .def = 0x1e, + }, }, }, { .id = 0x05, .name = "display0c", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 5, - }, - .la = { - .reg = 0x2ec, - .shift = 0, - .mask = 0xff, - .def = 0x1e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 5, + }, + .la = { + .reg = 0x2ec, + .shift = 0, + .mask = 0xff, + .def = 0x1e, + }, }, }, { .id = 0x06, .name = "display0cb", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 6, - }, - .la = { - .reg = 0x2f8, - .shift = 0, - .mask = 0xff, - .def = 0x1e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 6, + }, + .la = { + .reg = 0x2f8, + .shift = 0, + .mask = 0xff, + .def = 0x1e, + }, }, }, { .id = 0x0e, .name = "afir", .swgroup = TEGRA_SWGROUP_AFI, - .smmu = { - .reg = 0x228, - .bit = 14, - }, - .la = { - .reg = 0x2e0, - .shift = 0, - .mask = 0xff, - .def = 0x2e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 14, + }, + .la = { + .reg = 0x2e0, + .shift = 0, + .mask = 0xff, + .def = 0x2e, + }, }, }, { .id = 0x0f, .name = "avpcarm7r", .swgroup = TEGRA_SWGROUP_AVPC, - .smmu = { - .reg = 0x228, - .bit = 15, - }, - .la = { - .reg = 0x2e4, - .shift = 0, - .mask = 0xff, - .def = 0x04, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 15, + }, + .la = { + .reg = 0x2e4, + .shift = 0, + .mask = 0xff, + .def = 0x04, + }, }, }, { .id = 0x10, .name = "displayhc", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 16, - }, - .la = { - .reg = 0x2f0, - .shift = 0, - .mask = 0xff, - .def = 0x1e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 16, + }, + .la = { + .reg = 0x2f0, + .shift = 0, + .mask = 0xff, + .def = 0x1e, + }, }, }, { .id = 0x11, .name = "displayhcb", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 17, - }, - .la = { - .reg = 0x2fc, - .shift = 0, - .mask = 0xff, - .def = 0x1e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 17, + }, + .la = { + .reg = 0x2fc, + .shift = 0, + .mask = 0xff, + .def = 0x1e, + }, }, }, { .id = 0x15, .name = "hdar", .swgroup = TEGRA_SWGROUP_HDA, - .smmu = { - .reg = 0x228, - .bit = 21, - }, - .la = { - .reg = 0x318, - .shift = 0, - .mask = 0xff, - .def = 0x24, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 21, + }, + .la = { + .reg = 0x318, + .shift = 0, + .mask = 0xff, + .def = 0x24, + }, }, }, { .id = 0x16, .name = "host1xdmar", .swgroup = TEGRA_SWGROUP_HC, - .smmu = { - .reg = 0x228, - .bit = 22, - }, - .la = { - .reg = 0x310, - .shift = 0, - .mask = 0xff, - .def = 0x1e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 22, + }, + .la = { + .reg = 0x310, + .shift = 0, + .mask = 0xff, + .def = 0x1e, + }, }, }, { .id = 0x17, .name = "host1xr", .swgroup = TEGRA_SWGROUP_HC, - .smmu = { - .reg = 0x228, - .bit = 23, - }, - .la = { - .reg = 0x310, - .shift = 16, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 23, + }, + .la = { + .reg = 0x310, + .shift = 16, + .mask = 0xff, + .def = 0x50, + }, }, }, { .id = 0x1c, .name = "nvencsrd", .swgroup = TEGRA_SWGROUP_NVENC, - .smmu = { - .reg = 0x228, - .bit = 28, - }, - .la = { - .reg = 0x328, - .shift = 0, - .mask = 0xff, - .def = 0x23, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 28, + }, + .la = { + .reg = 0x328, + .shift = 0, + .mask = 0xff, + .def = 0x23, + }, }, }, { .id = 0x1d, .name = "ppcsahbdmar", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x228, - .bit = 29, - }, - .la = { - .reg = 0x344, - .shift = 0, - .mask = 0xff, - .def = 0x49, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 29, + }, + .la = { + .reg = 0x344, + .shift = 0, + .mask = 0xff, + .def = 0x49, + }, }, }, { .id = 0x1e, .name = "ppcsahbslvr", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x228, - .bit = 30, - }, - .la = { - .reg = 0x344, - .shift = 16, - .mask = 0xff, - .def = 0x1a, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 30, + }, + .la = { + .reg = 0x344, + .shift = 16, + .mask = 0xff, + .def = 0x1a, + }, }, }, { .id = 0x1f, .name = "satar", .swgroup = TEGRA_SWGROUP_SATA, - .smmu = { - .reg = 0x228, - .bit = 31, - }, - .la = { - .reg = 0x350, - .shift = 0, - .mask = 0xff, - .def = 0x65, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 31, + }, + .la = { + .reg = 0x350, + .shift = 0, + .mask = 0xff, + .def = 0x65, + }, }, }, { .id = 0x27, .name = "mpcorer", .swgroup = TEGRA_SWGROUP_MPCORE, - .la = { - .reg = 0x320, - .shift = 0, - .mask = 0xff, - .def = 0x04, + .regs = { + .la = { + .reg = 0x320, + .shift = 0, + .mask = 0xff, + .def = 0x04, + }, }, }, { .id = 0x2b, .name = "nvencswr", .swgroup = TEGRA_SWGROUP_NVENC, - .smmu = { - .reg = 0x22c, - .bit = 11, - }, - .la = { - .reg = 0x328, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 11, + }, + .la = { + .reg = 0x328, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x31, .name = "afiw", .swgroup = TEGRA_SWGROUP_AFI, - .smmu = { - .reg = 0x22c, - .bit = 17, - }, - .la = { - .reg = 0x2e0, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 17, + }, + .la = { + .reg = 0x2e0, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x32, .name = "avpcarm7w", .swgroup = TEGRA_SWGROUP_AVPC, - .smmu = { - .reg = 0x22c, - .bit = 18, - }, - .la = { - .reg = 0x2e4, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 18, + }, + .la = { + .reg = 0x2e4, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x35, .name = "hdaw", .swgroup = TEGRA_SWGROUP_HDA, - .smmu = { - .reg = 0x22c, - .bit = 21, - }, - .la = { - .reg = 0x318, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 21, + }, + .la = { + .reg = 0x318, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x36, .name = "host1xw", .swgroup = TEGRA_SWGROUP_HC, - .smmu = { - .reg = 0x22c, - .bit = 22, - }, - .la = { - .reg = 0x314, - .shift = 0, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 22, + }, + .la = { + .reg = 0x314, + .shift = 0, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x39, .name = "mpcorew", .swgroup = TEGRA_SWGROUP_MPCORE, - .la = { - .reg = 0x320, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .la = { + .reg = 0x320, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x3b, .name = "ppcsahbdmaw", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x22c, - .bit = 27, - }, - .la = { - .reg = 0x348, - .shift = 0, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 27, + }, + .la = { + .reg = 0x348, + .shift = 0, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x3c, .name = "ppcsahbslvw", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x22c, - .bit = 28, - }, - .la = { - .reg = 0x348, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 28, + }, + .la = { + .reg = 0x348, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x3d, .name = "sataw", .swgroup = TEGRA_SWGROUP_SATA, - .smmu = { - .reg = 0x22c, - .bit = 29, - }, - .la = { - .reg = 0x350, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 29, + }, + .la = { + .reg = 0x350, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x44, .name = "ispra", .swgroup = TEGRA_SWGROUP_ISP2, - .smmu = { - .reg = 0x230, - .bit = 4, - }, - .la = { - .reg = 0x370, - .shift = 0, - .mask = 0xff, - .def = 0x18, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 4, + }, + .la = { + .reg = 0x370, + .shift = 0, + .mask = 0xff, + .def = 0x18, + }, }, }, { .id = 0x46, .name = "ispwa", .swgroup = TEGRA_SWGROUP_ISP2, - .smmu = { - .reg = 0x230, - .bit = 6, - }, - .la = { - .reg = 0x374, - .shift = 0, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 6, + }, + .la = { + .reg = 0x374, + .shift = 0, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x47, .name = "ispwb", .swgroup = TEGRA_SWGROUP_ISP2, - .smmu = { - .reg = 0x230, - .bit = 7, - }, - .la = { - .reg = 0x374, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 7, + }, + .la = { + .reg = 0x374, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x4a, .name = "xusb_hostr", .swgroup = TEGRA_SWGROUP_XUSB_HOST, - .smmu = { - .reg = 0x230, - .bit = 10, - }, - .la = { - .reg = 0x37c, - .shift = 0, - .mask = 0xff, - .def = 0x7a, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 10, + }, + .la = { + .reg = 0x37c, + .shift = 0, + .mask = 0xff, + .def = 0x7a, + }, }, }, { .id = 0x4b, .name = "xusb_hostw", .swgroup = TEGRA_SWGROUP_XUSB_HOST, - .smmu = { - .reg = 0x230, - .bit = 11, - }, - .la = { - .reg = 0x37c, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 11, + }, + .la = { + .reg = 0x37c, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x4c, .name = "xusb_devr", .swgroup = TEGRA_SWGROUP_XUSB_DEV, - .smmu = { - .reg = 0x230, - .bit = 12, - }, - .la = { - .reg = 0x380, - .shift = 0, - .mask = 0xff, - .def = 0x39, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 12, + }, + .la = { + .reg = 0x380, + .shift = 0, + .mask = 0xff, + .def = 0x39, + }, }, }, { .id = 0x4d, .name = "xusb_devw", .swgroup = TEGRA_SWGROUP_XUSB_DEV, - .smmu = { - .reg = 0x230, - .bit = 13, - }, - .la = { - .reg = 0x380, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 13, + }, + .la = { + .reg = 0x380, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x4e, .name = "isprab", .swgroup = TEGRA_SWGROUP_ISP2B, - .smmu = { - .reg = 0x230, - .bit = 14, - }, - .la = { - .reg = 0x384, - .shift = 0, - .mask = 0xff, - .def = 0x18, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 14, + }, + .la = { + .reg = 0x384, + .shift = 0, + .mask = 0xff, + .def = 0x18, + }, }, }, { .id = 0x50, .name = "ispwab", .swgroup = TEGRA_SWGROUP_ISP2B, - .smmu = { - .reg = 0x230, - .bit = 16, - }, - .la = { - .reg = 0x388, - .shift = 0, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 16, + }, + .la = { + .reg = 0x388, + .shift = 0, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x51, .name = "ispwbb", .swgroup = TEGRA_SWGROUP_ISP2B, - .smmu = { - .reg = 0x230, - .bit = 17, - }, - .la = { - .reg = 0x388, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 17, + }, + .la = { + .reg = 0x388, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x54, .name = "tsecsrd", .swgroup = TEGRA_SWGROUP_TSEC, - .smmu = { - .reg = 0x230, - .bit = 20, - }, - .la = { - .reg = 0x390, - .shift = 0, - .mask = 0xff, - .def = 0x9b, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 20, + }, + .la = { + .reg = 0x390, + .shift = 0, + .mask = 0xff, + .def = 0x9b, + }, }, }, { .id = 0x55, .name = "tsecswr", .swgroup = TEGRA_SWGROUP_TSEC, - .smmu = { - .reg = 0x230, - .bit = 21, - }, - .la = { - .reg = 0x390, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 21, + }, + .la = { + .reg = 0x390, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x56, .name = "a9avpscr", .swgroup = TEGRA_SWGROUP_A9AVP, - .smmu = { - .reg = 0x230, - .bit = 22, - }, - .la = { - .reg = 0x3a4, - .shift = 0, - .mask = 0xff, - .def = 0x04, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 22, + }, + .la = { + .reg = 0x3a4, + .shift = 0, + .mask = 0xff, + .def = 0x04, + }, }, }, { .id = 0x57, .name = "a9avpscw", .swgroup = TEGRA_SWGROUP_A9AVP, - .smmu = { - .reg = 0x230, - .bit = 23, - }, - .la = { - .reg = 0x3a4, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 23, + }, + .la = { + .reg = 0x3a4, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x58, .name = "gpusrd", .swgroup = TEGRA_SWGROUP_GPU, - .smmu = { - /* read-only */ - .reg = 0x230, - .bit = 24, - }, - .la = { - .reg = 0x3c8, - .shift = 0, - .mask = 0xff, - .def = 0x1a, + .regs = { + .smmu = { + /* read-only */ + .reg = 0x230, + .bit = 24, + }, + .la = { + .reg = 0x3c8, + .shift = 0, + .mask = 0xff, + .def = 0x1a, + }, }, }, { .id = 0x59, .name = "gpuswr", .swgroup = TEGRA_SWGROUP_GPU, - .smmu = { - /* read-only */ - .reg = 0x230, - .bit = 25, - }, - .la = { - .reg = 0x3c8, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + /* read-only */ + .reg = 0x230, + .bit = 25, + }, + .la = { + .reg = 0x3c8, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x5a, .name = "displayt", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x230, - .bit = 26, - }, - .la = { - .reg = 0x2f0, - .shift = 16, - .mask = 0xff, - .def = 0x1e, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 26, + }, + .la = { + .reg = 0x2f0, + .shift = 16, + .mask = 0xff, + .def = 0x1e, + }, }, }, { .id = 0x60, .name = "sdmmcra", .swgroup = TEGRA_SWGROUP_SDMMC1A, - .smmu = { - .reg = 0x234, - .bit = 0, - }, - .la = { - .reg = 0x3b8, - .shift = 0, - .mask = 0xff, - .def = 0x49, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 0, + }, + .la = { + .reg = 0x3b8, + .shift = 0, + .mask = 0xff, + .def = 0x49, + }, }, }, { .id = 0x61, .name = "sdmmcraa", .swgroup = TEGRA_SWGROUP_SDMMC2A, - .smmu = { - .reg = 0x234, - .bit = 1, - }, - .la = { - .reg = 0x3bc, - .shift = 0, - .mask = 0xff, - .def = 0x5a, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 1, + }, + .la = { + .reg = 0x3bc, + .shift = 0, + .mask = 0xff, + .def = 0x5a, + }, }, }, { .id = 0x62, .name = "sdmmcr", .swgroup = TEGRA_SWGROUP_SDMMC3A, - .smmu = { - .reg = 0x234, - .bit = 2, - }, - .la = { - .reg = 0x3c0, - .shift = 0, - .mask = 0xff, - .def = 0x49, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 2, + }, + .la = { + .reg = 0x3c0, + .shift = 0, + .mask = 0xff, + .def = 0x49, + }, }, }, { .id = 0x63, .swgroup = TEGRA_SWGROUP_SDMMC4A, .name = "sdmmcrab", - .smmu = { - .reg = 0x234, - .bit = 3, - }, - .la = { - .reg = 0x3c4, - .shift = 0, - .mask = 0xff, - .def = 0x5a, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 3, + }, + .la = { + .reg = 0x3c4, + .shift = 0, + .mask = 0xff, + .def = 0x5a, + }, }, }, { .id = 0x64, .name = "sdmmcwa", .swgroup = TEGRA_SWGROUP_SDMMC1A, - .smmu = { - .reg = 0x234, - .bit = 4, - }, - .la = { - .reg = 0x3b8, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 4, + }, + .la = { + .reg = 0x3b8, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x65, .name = "sdmmcwaa", .swgroup = TEGRA_SWGROUP_SDMMC2A, - .smmu = { - .reg = 0x234, - .bit = 5, - }, - .la = { - .reg = 0x3bc, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 5, + }, + .la = { + .reg = 0x3bc, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x66, .name = "sdmmcw", .swgroup = TEGRA_SWGROUP_SDMMC3A, - .smmu = { - .reg = 0x234, - .bit = 6, - }, - .la = { - .reg = 0x3c0, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 6, + }, + .la = { + .reg = 0x3c0, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x67, .name = "sdmmcwab", .swgroup = TEGRA_SWGROUP_SDMMC4A, - .smmu = { - .reg = 0x234, - .bit = 7, - }, - .la = { - .reg = 0x3c4, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 7, + }, + .la = { + .reg = 0x3c4, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x6c, .name = "vicsrd", .swgroup = TEGRA_SWGROUP_VIC, - .smmu = { - .reg = 0x234, - .bit = 12, - }, - .la = { - .reg = 0x394, - .shift = 0, - .mask = 0xff, - .def = 0x1a, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 12, + }, + .la = { + .reg = 0x394, + .shift = 0, + .mask = 0xff, + .def = 0x1a, + }, }, }, { .id = 0x6d, .name = "vicswr", .swgroup = TEGRA_SWGROUP_VIC, - .smmu = { - .reg = 0x234, - .bit = 13, - }, - .la = { - .reg = 0x394, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 13, + }, + .la = { + .reg = 0x394, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x72, .name = "viw", .swgroup = TEGRA_SWGROUP_VI, - .smmu = { - .reg = 0x234, - .bit = 18, - }, - .la = { - .reg = 0x398, - .shift = 0, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 18, + }, + .la = { + .reg = 0x398, + .shift = 0, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x73, .name = "displayd", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x234, - .bit = 19, - }, - .la = { - .reg = 0x3c8, - .shift = 0, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 19, + }, + .la = { + .reg = 0x3c8, + .shift = 0, + .mask = 0xff, + .def = 0x50, + }, }, }, { .id = 0x78, .name = "nvdecsrd", .swgroup = TEGRA_SWGROUP_NVDEC, - .smmu = { - .reg = 0x234, - .bit = 24, - }, - .la = { - .reg = 0x3d8, - .shift = 0, - .mask = 0xff, - .def = 0x23, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 24, + }, + .la = { + .reg = 0x3d8, + .shift = 0, + .mask = 0xff, + .def = 0x23, + }, }, }, { .id = 0x79, .name = "nvdecswr", .swgroup = TEGRA_SWGROUP_NVDEC, - .smmu = { - .reg = 0x234, - .bit = 25, - }, - .la = { - .reg = 0x3d8, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 25, + }, + .la = { + .reg = 0x3d8, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x7a, .name = "aper", .swgroup = TEGRA_SWGROUP_APE, - .smmu = { - .reg = 0x234, - .bit = 26, - }, - .la = { - .reg = 0x3dc, - .shift = 0, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 26, + }, + .la = { + .reg = 0x3dc, + .shift = 0, + .mask = 0xff, + .def = 0xff, + }, }, }, { .id = 0x7b, .name = "apew", .swgroup = TEGRA_SWGROUP_APE, - .smmu = { - .reg = 0x234, - .bit = 27, - }, - .la = { - .reg = 0x3dc, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 27, + }, + .la = { + .reg = 0x3dc, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x7e, .name = "nvjpgsrd", .swgroup = TEGRA_SWGROUP_NVJPG, - .smmu = { - .reg = 0x234, - .bit = 30, - }, - .la = { - .reg = 0x3e4, - .shift = 0, - .mask = 0xff, - .def = 0x23, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 30, + }, + .la = { + .reg = 0x3e4, + .shift = 0, + .mask = 0xff, + .def = 0x23, + }, }, }, { .id = 0x7f, .name = "nvjpgswr", .swgroup = TEGRA_SWGROUP_NVJPG, - .smmu = { - .reg = 0x234, - .bit = 31, - }, - .la = { - .reg = 0x3e4, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x234, + .bit = 31, + }, + .la = { + .reg = 0x3e4, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x80, .name = "sesrd", .swgroup = TEGRA_SWGROUP_SE, - .smmu = { - .reg = 0xb98, - .bit = 0, - }, - .la = { - .reg = 0x3e0, - .shift = 0, - .mask = 0xff, - .def = 0x2e, + .regs = { + .smmu = { + .reg = 0xb98, + .bit = 0, + }, + .la = { + .reg = 0x3e0, + .shift = 0, + .mask = 0xff, + .def = 0x2e, + }, }, }, { .id = 0x81, .name = "seswr", .swgroup = TEGRA_SWGROUP_SE, - .smmu = { - .reg = 0xb98, - .bit = 1, - }, - .la = { - .reg = 0x3e0, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0xb98, + .bit = 1, + }, + .la = { + .reg = 0x3e0, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x82, .name = "axiapr", .swgroup = TEGRA_SWGROUP_AXIAP, - .smmu = { - .reg = 0xb98, - .bit = 2, - }, - .la = { - .reg = 0x3a0, - .shift = 0, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0xb98, + .bit = 2, + }, + .la = { + .reg = 0x3a0, + .shift = 0, + .mask = 0xff, + .def = 0xff, + }, }, }, { .id = 0x83, .name = "axiapw", .swgroup = TEGRA_SWGROUP_AXIAP, - .smmu = { - .reg = 0xb98, - .bit = 3, - }, - .la = { - .reg = 0x3a0, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0xb98, + .bit = 3, + }, + .la = { + .reg = 0x3a0, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x84, .name = "etrr", .swgroup = TEGRA_SWGROUP_ETR, - .smmu = { - .reg = 0xb98, - .bit = 4, - }, - .la = { - .reg = 0x3ec, - .shift = 0, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0xb98, + .bit = 4, + }, + .la = { + .reg = 0x3ec, + .shift = 0, + .mask = 0xff, + .def = 0xff, + }, }, }, { .id = 0x85, .name = "etrw", .swgroup = TEGRA_SWGROUP_ETR, - .smmu = { - .reg = 0xb98, - .bit = 5, - }, - .la = { - .reg = 0x3ec, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0xb98, + .bit = 5, + }, + .la = { + .reg = 0x3ec, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x86, .name = "tsecsrdb", .swgroup = TEGRA_SWGROUP_TSECB, - .smmu = { - .reg = 0xb98, - .bit = 6, - }, - .la = { - .reg = 0x3f0, - .shift = 0, - .mask = 0xff, - .def = 0x9b, + .regs = { + .smmu = { + .reg = 0xb98, + .bit = 6, + }, + .la = { + .reg = 0x3f0, + .shift = 0, + .mask = 0xff, + .def = 0x9b, + }, }, }, { .id = 0x87, .name = "tsecswrb", .swgroup = TEGRA_SWGROUP_TSECB, - .smmu = { - .reg = 0xb98, - .bit = 7, - }, - .la = { - .reg = 0x3f0, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0xb98, + .bit = 7, + }, + .la = { + .reg = 0x3f0, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, { .id = 0x88, .name = "gpusrd2", .swgroup = TEGRA_SWGROUP_GPU, - .smmu = { - /* read-only */ - .reg = 0xb98, - .bit = 8, - }, - .la = { - .reg = 0x3e8, - .shift = 0, - .mask = 0xff, - .def = 0x1a, + .regs = { + .smmu = { + /* read-only */ + .reg = 0xb98, + .bit = 8, + }, + .la = { + .reg = 0x3e8, + .shift = 0, + .mask = 0xff, + .def = 0x1a, + }, }, }, { .id = 0x89, .name = "gpuswr2", .swgroup = TEGRA_SWGROUP_GPU, - .smmu = { - /* read-only */ - .reg = 0xb98, - .bit = 9, - }, - .la = { - .reg = 0x3e8, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + /* read-only */ + .reg = 0xb98, + .bit = 9, + }, + .la = { + .reg = 0x3e8, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, }, }; diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index ea849003014b..1922ab64e686 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -37,970 +37,1102 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .id = 0x00, .name = "ptcr", .swgroup = TEGRA_SWGROUP_PTC, - .la = { - .reg = 0x34c, - .shift = 0, - .mask = 0xff, - .def = 0x0, + .regs = { + .la = { + .reg = 0x34c, + .shift = 0, + .mask = 0xff, + .def = 0x0, + }, }, .fifo_size = 16 * 2, }, { .id = 0x01, .name = "display0a", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 1, - }, - .la = { - .reg = 0x2e8, - .shift = 0, - .mask = 0xff, - .def = 0x4e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 1, + }, + .la = { + .reg = 0x2e8, + .shift = 0, + .mask = 0xff, + .def = 0x4e, + }, }, .fifo_size = 16 * 128, }, { .id = 0x02, .name = "display0ab", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 2, - }, - .la = { - .reg = 0x2f4, - .shift = 0, - .mask = 0xff, - .def = 0x4e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 2, + }, + .la = { + .reg = 0x2f4, + .shift = 0, + .mask = 0xff, + .def = 0x4e, + }, }, .fifo_size = 16 * 128, }, { .id = 0x03, .name = "display0b", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 3, - }, - .la = { - .reg = 0x2e8, - .shift = 16, - .mask = 0xff, - .def = 0x4e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 3, + }, + .la = { + .reg = 0x2e8, + .shift = 16, + .mask = 0xff, + .def = 0x4e, + }, }, .fifo_size = 16 * 64, }, { .id = 0x04, .name = "display0bb", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 4, - }, - .la = { - .reg = 0x2f4, - .shift = 16, - .mask = 0xff, - .def = 0x4e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 4, + }, + .la = { + .reg = 0x2f4, + .shift = 16, + .mask = 0xff, + .def = 0x4e, + }, }, .fifo_size = 16 * 64, }, { .id = 0x05, .name = "display0c", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 5, - }, - .la = { - .reg = 0x2ec, - .shift = 0, - .mask = 0xff, - .def = 0x4e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 5, + }, + .la = { + .reg = 0x2ec, + .shift = 0, + .mask = 0xff, + .def = 0x4e, + }, }, .fifo_size = 16 * 128, }, { .id = 0x06, .name = "display0cb", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 6, - }, - .la = { - .reg = 0x2f8, - .shift = 0, - .mask = 0xff, - .def = 0x4e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 6, + }, + .la = { + .reg = 0x2f8, + .shift = 0, + .mask = 0xff, + .def = 0x4e, + }, }, .fifo_size = 16 * 128, }, { .id = 0x07, .name = "display1b", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 7, - }, - .la = { - .reg = 0x2ec, - .shift = 16, - .mask = 0xff, - .def = 0x4e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 7, + }, + .la = { + .reg = 0x2ec, + .shift = 16, + .mask = 0xff, + .def = 0x4e, + }, }, .fifo_size = 16 * 64, }, { .id = 0x08, .name = "display1bb", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 8, - }, - .la = { - .reg = 0x2f8, - .shift = 16, - .mask = 0xff, - .def = 0x4e, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 8, + }, + .la = { + .reg = 0x2f8, + .shift = 16, + .mask = 0xff, + .def = 0x4e, + }, }, .fifo_size = 16 * 64, }, { .id = 0x09, .name = "eppup", .swgroup = TEGRA_SWGROUP_EPP, - .smmu = { - .reg = 0x228, - .bit = 9, - }, - .la = { - .reg = 0x300, - .shift = 0, - .mask = 0xff, - .def = 0x17, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 9, + }, + .la = { + .reg = 0x300, + .shift = 0, + .mask = 0xff, + .def = 0x17, + }, }, .fifo_size = 16 * 8, }, { .id = 0x0a, .name = "g2pr", .swgroup = TEGRA_SWGROUP_G2, - .smmu = { - .reg = 0x228, - .bit = 10, - }, - .la = { - .reg = 0x308, - .shift = 0, - .mask = 0xff, - .def = 0x09, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 10, + }, + .la = { + .reg = 0x308, + .shift = 0, + .mask = 0xff, + .def = 0x09, + }, }, .fifo_size = 16 * 64, }, { .id = 0x0b, .name = "g2sr", .swgroup = TEGRA_SWGROUP_G2, - .smmu = { - .reg = 0x228, - .bit = 11, - }, - .la = { - .reg = 0x308, - .shift = 16, - .mask = 0xff, - .def = 0x09, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 11, + }, + .la = { + .reg = 0x308, + .shift = 16, + .mask = 0xff, + .def = 0x09, + }, }, .fifo_size = 16 * 64, }, { .id = 0x0c, .name = "mpeunifbr", .swgroup = TEGRA_SWGROUP_MPE, - .smmu = { - .reg = 0x228, - .bit = 12, - }, - .la = { - .reg = 0x328, - .shift = 0, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 12, + }, + .la = { + .reg = 0x328, + .shift = 0, + .mask = 0xff, + .def = 0x50, + }, }, .fifo_size = 16 * 8, }, { .id = 0x0d, .name = "viruv", .swgroup = TEGRA_SWGROUP_VI, - .smmu = { - .reg = 0x228, - .bit = 13, - }, - .la = { - .reg = 0x364, - .shift = 0, - .mask = 0xff, - .def = 0x2c, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 13, + }, + .la = { + .reg = 0x364, + .shift = 0, + .mask = 0xff, + .def = 0x2c, + }, }, .fifo_size = 16 * 8, }, { .id = 0x0e, .name = "afir", .swgroup = TEGRA_SWGROUP_AFI, - .smmu = { - .reg = 0x228, - .bit = 14, - }, - .la = { - .reg = 0x2e0, - .shift = 0, - .mask = 0xff, - .def = 0x10, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 14, + }, + .la = { + .reg = 0x2e0, + .shift = 0, + .mask = 0xff, + .def = 0x10, + }, }, .fifo_size = 16 * 32, }, { .id = 0x0f, .name = "avpcarm7r", .swgroup = TEGRA_SWGROUP_AVPC, - .smmu = { - .reg = 0x228, - .bit = 15, - }, - .la = { - .reg = 0x2e4, - .shift = 0, - .mask = 0xff, - .def = 0x04, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 15, + }, + .la = { + .reg = 0x2e4, + .shift = 0, + .mask = 0xff, + .def = 0x04, + }, }, .fifo_size = 16 * 2, }, { .id = 0x10, .name = "displayhc", .swgroup = TEGRA_SWGROUP_DC, - .smmu = { - .reg = 0x228, - .bit = 16, - }, - .la = { - .reg = 0x2f0, - .shift = 0, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 16, + }, + .la = { + .reg = 0x2f0, + .shift = 0, + .mask = 0xff, + .def = 0xff, + }, }, .fifo_size = 16 * 2, }, { .id = 0x11, .name = "displayhcb", .swgroup = TEGRA_SWGROUP_DCB, - .smmu = { - .reg = 0x228, - .bit = 17, - }, - .la = { - .reg = 0x2fc, - .shift = 0, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 17, + }, + .la = { + .reg = 0x2fc, + .shift = 0, + .mask = 0xff, + .def = 0xff, + }, }, .fifo_size = 16 * 2, }, { .id = 0x12, .name = "fdcdrd", .swgroup = TEGRA_SWGROUP_NV, - .smmu = { - .reg = 0x228, - .bit = 18, - }, - .la = { - .reg = 0x334, - .shift = 0, - .mask = 0xff, - .def = 0x0a, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 18, + }, + .la = { + .reg = 0x334, + .shift = 0, + .mask = 0xff, + .def = 0x0a, + }, }, .fifo_size = 16 * 48, }, { .id = 0x13, .name = "fdcdrd2", .swgroup = TEGRA_SWGROUP_NV2, - .smmu = { - .reg = 0x228, - .bit = 19, - }, - .la = { - .reg = 0x33c, - .shift = 0, - .mask = 0xff, - .def = 0x0a, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 19, + }, + .la = { + .reg = 0x33c, + .shift = 0, + .mask = 0xff, + .def = 0x0a, + }, }, .fifo_size = 16 * 48, }, { .id = 0x14, .name = "g2dr", .swgroup = TEGRA_SWGROUP_G2, - .smmu = { - .reg = 0x228, - .bit = 20, - }, - .la = { - .reg = 0x30c, - .shift = 0, - .mask = 0xff, - .def = 0x0a, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 20, + }, + .la = { + .reg = 0x30c, + .shift = 0, + .mask = 0xff, + .def = 0x0a, + }, }, .fifo_size = 16 * 48, }, { .id = 0x15, .name = "hdar", .swgroup = TEGRA_SWGROUP_HDA, - .smmu = { - .reg = 0x228, - .bit = 21, - }, - .la = { - .reg = 0x318, - .shift = 0, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 21, + }, + .la = { + .reg = 0x318, + .shift = 0, + .mask = 0xff, + .def = 0xff, + }, }, .fifo_size = 16 * 16, }, { .id = 0x16, .name = "host1xdmar", .swgroup = TEGRA_SWGROUP_HC, - .smmu = { - .reg = 0x228, - .bit = 22, - }, - .la = { - .reg = 0x310, - .shift = 0, - .mask = 0xff, - .def = 0x05, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 22, + }, + .la = { + .reg = 0x310, + .shift = 0, + .mask = 0xff, + .def = 0x05, + }, }, .fifo_size = 16 * 16, }, { .id = 0x17, .name = "host1xr", .swgroup = TEGRA_SWGROUP_HC, - .smmu = { - .reg = 0x228, - .bit = 23, - }, - .la = { - .reg = 0x310, - .shift = 16, - .mask = 0xff, - .def = 0x50, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 23, + }, + .la = { + .reg = 0x310, + .shift = 16, + .mask = 0xff, + .def = 0x50, + }, }, .fifo_size = 16 * 8, }, { .id = 0x18, .name = "idxsrd", .swgroup = TEGRA_SWGROUP_NV, - .smmu = { - .reg = 0x228, - .bit = 24, - }, - .la = { - .reg = 0x334, - .shift = 16, - .mask = 0xff, - .def = 0x13, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 24, + }, + .la = { + .reg = 0x334, + .shift = 16, + .mask = 0xff, + .def = 0x13, + }, }, .fifo_size = 16 * 64, }, { .id = 0x19, .name = "idxsrd2", .swgroup = TEGRA_SWGROUP_NV2, - .smmu = { - .reg = 0x228, - .bit = 25, - }, - .la = { - .reg = 0x33c, - .shift = 16, - .mask = 0xff, - .def = 0x13, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 25, + }, + .la = { + .reg = 0x33c, + .shift = 16, + .mask = 0xff, + .def = 0x13, + }, }, .fifo_size = 16 * 64, }, { .id = 0x1a, .name = "mpe_ipred", .swgroup = TEGRA_SWGROUP_MPE, - .smmu = { - .reg = 0x228, - .bit = 26, - }, - .la = { - .reg = 0x328, - .shift = 16, - .mask = 0xff, - .def = 0x80, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 26, + }, + .la = { + .reg = 0x328, + .shift = 16, + .mask = 0xff, + .def = 0x80, + }, }, .fifo_size = 16 * 2, }, { .id = 0x1b, .name = "mpeamemrd", .swgroup = TEGRA_SWGROUP_MPE, - .smmu = { - .reg = 0x228, - .bit = 27, - }, - .la = { - .reg = 0x32c, - .shift = 0, - .mask = 0xff, - .def = 0x42, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 27, + }, + .la = { + .reg = 0x32c, + .shift = 0, + .mask = 0xff, + .def = 0x42, + }, }, .fifo_size = 16 * 64, }, { .id = 0x1c, .name = "mpecsrd", .swgroup = TEGRA_SWGROUP_MPE, - .smmu = { - .reg = 0x228, - .bit = 28, - }, - .la = { - .reg = 0x32c, - .shift = 16, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 28, + }, + .la = { + .reg = 0x32c, + .shift = 16, + .mask = 0xff, + .def = 0xff, + }, }, .fifo_size = 16 * 8, }, { .id = 0x1d, .name = "ppcsahbdmar", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x228, - .bit = 29, - }, - .la = { - .reg = 0x344, - .shift = 0, - .mask = 0xff, - .def = 0x10, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 29, + }, + .la = { + .reg = 0x344, + .shift = 0, + .mask = 0xff, + .def = 0x10, + }, }, .fifo_size = 16 * 2, }, { .id = 0x1e, .name = "ppcsahbslvr", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x228, - .bit = 30, - }, - .la = { - .reg = 0x344, - .shift = 16, - .mask = 0xff, - .def = 0x12, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 30, + }, + .la = { + .reg = 0x344, + .shift = 16, + .mask = 0xff, + .def = 0x12, + }, }, .fifo_size = 16 * 8, }, { .id = 0x1f, .name = "satar", .swgroup = TEGRA_SWGROUP_SATA, - .smmu = { - .reg = 0x228, - .bit = 31, - }, - .la = { - .reg = 0x350, - .shift = 0, - .mask = 0xff, - .def = 0x33, + .regs = { + .smmu = { + .reg = 0x228, + .bit = 31, + }, + .la = { + .reg = 0x350, + .shift = 0, + .mask = 0xff, + .def = 0x33, + }, }, .fifo_size = 16 * 32, }, { .id = 0x20, .name = "texsrd", .swgroup = TEGRA_SWGROUP_NV, - .smmu = { - .reg = 0x22c, - .bit = 0, - }, - .la = { - .reg = 0x338, - .shift = 0, - .mask = 0xff, - .def = 0x13, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 0, + }, + .la = { + .reg = 0x338, + .shift = 0, + .mask = 0xff, + .def = 0x13, + }, }, .fifo_size = 16 * 64, }, { .id = 0x21, .name = "texsrd2", .swgroup = TEGRA_SWGROUP_NV2, - .smmu = { - .reg = 0x22c, - .bit = 1, - }, - .la = { - .reg = 0x340, - .shift = 0, - .mask = 0xff, - .def = 0x13, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 1, + }, + .la = { + .reg = 0x340, + .shift = 0, + .mask = 0xff, + .def = 0x13, + }, }, .fifo_size = 16 * 64, }, { .id = 0x22, .name = "vdebsevr", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 2, - }, - .la = { - .reg = 0x354, - .shift = 0, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 2, + }, + .la = { + .reg = 0x354, + .shift = 0, + .mask = 0xff, + .def = 0xff, + }, }, .fifo_size = 16 * 8, }, { .id = 0x23, .name = "vdember", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 3, - }, - .la = { - .reg = 0x354, - .shift = 16, - .mask = 0xff, - .def = 0xd0, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 3, + }, + .la = { + .reg = 0x354, + .shift = 16, + .mask = 0xff, + .def = 0xd0, + }, }, .fifo_size = 16 * 4, }, { .id = 0x24, .name = "vdemcer", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 4, - }, - .la = { - .reg = 0x358, - .shift = 0, - .mask = 0xff, - .def = 0x2a, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 4, + }, + .la = { + .reg = 0x358, + .shift = 0, + .mask = 0xff, + .def = 0x2a, + }, }, .fifo_size = 16 * 16, }, { .id = 0x25, .name = "vdetper", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 5, - }, - .la = { - .reg = 0x358, - .shift = 16, - .mask = 0xff, - .def = 0x74, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 5, + }, + .la = { + .reg = 0x358, + .shift = 16, + .mask = 0xff, + .def = 0x74, + }, }, .fifo_size = 16 * 16, }, { .id = 0x26, .name = "mpcorelpr", .swgroup = TEGRA_SWGROUP_MPCORELP, - .la = { - .reg = 0x324, - .shift = 0, - .mask = 0xff, - .def = 0x04, + .regs = { + .la = { + .reg = 0x324, + .shift = 0, + .mask = 0xff, + .def = 0x04, + }, }, .fifo_size = 16 * 14, }, { .id = 0x27, .name = "mpcorer", .swgroup = TEGRA_SWGROUP_MPCORE, - .la = { - .reg = 0x320, - .shift = 0, - .mask = 0xff, - .def = 0x04, + .regs = { + .la = { + .reg = 0x320, + .shift = 0, + .mask = 0xff, + .def = 0x04, + }, }, .fifo_size = 16 * 14, }, { .id = 0x28, .name = "eppu", .swgroup = TEGRA_SWGROUP_EPP, - .smmu = { - .reg = 0x22c, - .bit = 8, - }, - .la = { - .reg = 0x300, - .shift = 16, - .mask = 0xff, - .def = 0x6c, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 8, + }, + .la = { + .reg = 0x300, + .shift = 16, + .mask = 0xff, + .def = 0x6c, + }, }, .fifo_size = 16 * 64, }, { .id = 0x29, .name = "eppv", .swgroup = TEGRA_SWGROUP_EPP, - .smmu = { - .reg = 0x22c, - .bit = 9, - }, - .la = { - .reg = 0x304, - .shift = 0, - .mask = 0xff, - .def = 0x6c, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 9, + }, + .la = { + .reg = 0x304, + .shift = 0, + .mask = 0xff, + .def = 0x6c, + }, }, .fifo_size = 16 * 64, }, { .id = 0x2a, .name = "eppy", .swgroup = TEGRA_SWGROUP_EPP, - .smmu = { - .reg = 0x22c, - .bit = 10, - }, - .la = { - .reg = 0x304, - .shift = 16, - .mask = 0xff, - .def = 0x6c, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 10, + }, + .la = { + .reg = 0x304, + .shift = 16, + .mask = 0xff, + .def = 0x6c, + }, }, .fifo_size = 16 * 64, }, { .id = 0x2b, .name = "mpeunifbw", .swgroup = TEGRA_SWGROUP_MPE, - .smmu = { - .reg = 0x22c, - .bit = 11, - }, - .la = { - .reg = 0x330, - .shift = 0, - .mask = 0xff, - .def = 0x13, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 11, + }, + .la = { + .reg = 0x330, + .shift = 0, + .mask = 0xff, + .def = 0x13, + }, }, .fifo_size = 16 * 8, }, { .id = 0x2c, .name = "viwsb", .swgroup = TEGRA_SWGROUP_VI, - .smmu = { - .reg = 0x22c, - .bit = 12, - }, - .la = { - .reg = 0x364, - .shift = 16, - .mask = 0xff, - .def = 0x12, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 12, + }, + .la = { + .reg = 0x364, + .shift = 16, + .mask = 0xff, + .def = 0x12, + }, }, .fifo_size = 16 * 64, }, { .id = 0x2d, .name = "viwu", .swgroup = TEGRA_SWGROUP_VI, - .smmu = { - .reg = 0x22c, - .bit = 13, - }, - .la = { - .reg = 0x368, - .shift = 0, - .mask = 0xff, - .def = 0xb2, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 13, + }, + .la = { + .reg = 0x368, + .shift = 0, + .mask = 0xff, + .def = 0xb2, + }, }, .fifo_size = 16 * 64, }, { .id = 0x2e, .name = "viwv", .swgroup = TEGRA_SWGROUP_VI, - .smmu = { - .reg = 0x22c, - .bit = 14, - }, - .la = { - .reg = 0x368, - .shift = 16, - .mask = 0xff, - .def = 0xb2, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 14, + }, + .la = { + .reg = 0x368, + .shift = 16, + .mask = 0xff, + .def = 0xb2, + }, }, .fifo_size = 16 * 64, }, { .id = 0x2f, .name = "viwy", .swgroup = TEGRA_SWGROUP_VI, - .smmu = { - .reg = 0x22c, - .bit = 15, - }, - .la = { - .reg = 0x36c, - .shift = 0, - .mask = 0xff, - .def = 0x12, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 15, + }, + .la = { + .reg = 0x36c, + .shift = 0, + .mask = 0xff, + .def = 0x12, + }, }, .fifo_size = 16 * 64, }, { .id = 0x30, .name = "g2dw", .swgroup = TEGRA_SWGROUP_G2, - .smmu = { - .reg = 0x22c, - .bit = 16, - }, - .la = { - .reg = 0x30c, - .shift = 16, - .mask = 0xff, - .def = 0x9, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 16, + }, + .la = { + .reg = 0x30c, + .shift = 16, + .mask = 0xff, + .def = 0x9, + }, }, .fifo_size = 16 * 128, }, { .id = 0x31, .name = "afiw", .swgroup = TEGRA_SWGROUP_AFI, - .smmu = { - .reg = 0x22c, - .bit = 17, - }, - .la = { - .reg = 0x2e0, - .shift = 16, - .mask = 0xff, - .def = 0x0c, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 17, + }, + .la = { + .reg = 0x2e0, + .shift = 16, + .mask = 0xff, + .def = 0x0c, + }, }, .fifo_size = 16 * 32, }, { .id = 0x32, .name = "avpcarm7w", .swgroup = TEGRA_SWGROUP_AVPC, - .smmu = { - .reg = 0x22c, - .bit = 18, - }, - .la = { - .reg = 0x2e4, - .shift = 16, - .mask = 0xff, - .def = 0x0e, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 18, + }, + .la = { + .reg = 0x2e4, + .shift = 16, + .mask = 0xff, + .def = 0x0e, + }, }, .fifo_size = 16 * 2, }, { .id = 0x33, .name = "fdcdwr", .swgroup = TEGRA_SWGROUP_NV, - .smmu = { - .reg = 0x22c, - .bit = 19, - }, - .la = { - .reg = 0x338, - .shift = 16, - .mask = 0xff, - .def = 0x0a, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 19, + }, + .la = { + .reg = 0x338, + .shift = 16, + .mask = 0xff, + .def = 0x0a, + }, }, .fifo_size = 16 * 48, }, { .id = 0x34, .name = "fdcdwr2", .swgroup = TEGRA_SWGROUP_NV2, - .smmu = { - .reg = 0x22c, - .bit = 20, - }, - .la = { - .reg = 0x340, - .shift = 16, - .mask = 0xff, - .def = 0x0a, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 20, + }, + .la = { + .reg = 0x340, + .shift = 16, + .mask = 0xff, + .def = 0x0a, + }, }, .fifo_size = 16 * 48, }, { .id = 0x35, .name = "hdaw", .swgroup = TEGRA_SWGROUP_HDA, - .smmu = { - .reg = 0x22c, - .bit = 21, - }, - .la = { - .reg = 0x318, - .shift = 16, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 21, + }, + .la = { + .reg = 0x318, + .shift = 16, + .mask = 0xff, + .def = 0xff, + }, }, .fifo_size = 16 * 16, }, { .id = 0x36, .name = "host1xw", .swgroup = TEGRA_SWGROUP_HC, - .smmu = { - .reg = 0x22c, - .bit = 22, - }, - .la = { - .reg = 0x314, - .shift = 0, - .mask = 0xff, - .def = 0x10, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 22, + }, + .la = { + .reg = 0x314, + .shift = 0, + .mask = 0xff, + .def = 0x10, + }, }, .fifo_size = 16 * 32, }, { .id = 0x37, .name = "ispw", .swgroup = TEGRA_SWGROUP_ISP, - .smmu = { - .reg = 0x22c, - .bit = 23, - }, - .la = { - .reg = 0x31c, - .shift = 0, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 23, + }, + .la = { + .reg = 0x31c, + .shift = 0, + .mask = 0xff, + .def = 0xff, + }, }, .fifo_size = 16 * 64, }, { .id = 0x38, .name = "mpcorelpw", .swgroup = TEGRA_SWGROUP_MPCORELP, - .la = { - .reg = 0x324, - .shift = 16, - .mask = 0xff, - .def = 0x0e, + .regs = { + .la = { + .reg = 0x324, + .shift = 16, + .mask = 0xff, + .def = 0x0e, + }, }, .fifo_size = 16 * 24, }, { .id = 0x39, .name = "mpcorew", .swgroup = TEGRA_SWGROUP_MPCORE, - .la = { - .reg = 0x320, - .shift = 16, - .mask = 0xff, - .def = 0x0e, + .regs = { + .la = { + .reg = 0x320, + .shift = 16, + .mask = 0xff, + .def = 0x0e, + }, }, .fifo_size = 16 * 24, }, { .id = 0x3a, .name = "mpecswr", .swgroup = TEGRA_SWGROUP_MPE, - .smmu = { - .reg = 0x22c, - .bit = 26, - }, - .la = { - .reg = 0x330, - .shift = 16, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 26, + }, + .la = { + .reg = 0x330, + .shift = 16, + .mask = 0xff, + .def = 0xff, + }, }, .fifo_size = 16 * 8, }, { .id = 0x3b, .name = "ppcsahbdmaw", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x22c, - .bit = 27, - }, - .la = { - .reg = 0x348, - .shift = 0, - .mask = 0xff, - .def = 0x10, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 27, + }, + .la = { + .reg = 0x348, + .shift = 0, + .mask = 0xff, + .def = 0x10, + }, }, .fifo_size = 16 * 2, }, { .id = 0x3c, .name = "ppcsahbslvw", .swgroup = TEGRA_SWGROUP_PPCS, - .smmu = { - .reg = 0x22c, - .bit = 28, - }, - .la = { - .reg = 0x348, - .shift = 16, - .mask = 0xff, - .def = 0x06, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 28, + }, + .la = { + .reg = 0x348, + .shift = 16, + .mask = 0xff, + .def = 0x06, + }, }, .fifo_size = 16 * 4, }, { .id = 0x3d, .name = "sataw", .swgroup = TEGRA_SWGROUP_SATA, - .smmu = { - .reg = 0x22c, - .bit = 29, - }, - .la = { - .reg = 0x350, - .shift = 16, - .mask = 0xff, - .def = 0x33, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 29, + }, + .la = { + .reg = 0x350, + .shift = 16, + .mask = 0xff, + .def = 0x33, + }, }, .fifo_size = 16 * 32, }, { .id = 0x3e, .name = "vdebsevw", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 30, - }, - .la = { - .reg = 0x35c, - .shift = 0, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 30, + }, + .la = { + .reg = 0x35c, + .shift = 0, + .mask = 0xff, + .def = 0xff, + }, }, .fifo_size = 16 * 4, }, { .id = 0x3f, .name = "vdedbgw", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x22c, - .bit = 31, - }, - .la = { - .reg = 0x35c, - .shift = 16, - .mask = 0xff, - .def = 0xff, + .regs = { + .smmu = { + .reg = 0x22c, + .bit = 31, + }, + .la = { + .reg = 0x35c, + .shift = 16, + .mask = 0xff, + .def = 0xff, + }, }, .fifo_size = 16 * 16, }, { .id = 0x40, .name = "vdembew", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x230, - .bit = 0, - }, - .la = { - .reg = 0x360, - .shift = 0, - .mask = 0xff, - .def = 0x42, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 0, + }, + .la = { + .reg = 0x360, + .shift = 0, + .mask = 0xff, + .def = 0x42, + }, }, .fifo_size = 16 * 2, }, { .id = 0x41, .name = "vdetpmw", .swgroup = TEGRA_SWGROUP_VDE, - .smmu = { - .reg = 0x230, - .bit = 1, - }, - .la = { - .reg = 0x360, - .shift = 16, - .mask = 0xff, - .def = 0x2a, + .regs = { + .smmu = { + .reg = 0x230, + .bit = 1, + }, + .la = { + .reg = 0x360, + .shift = 16, + .mask = 0xff, + .def = 0x2a, + }, }, .fifo_size = 16 * 16, }, @@ -1089,7 +1221,6 @@ static void tegra30_mc_tune_client_latency(struct tegra_mc *mc, unsigned int bandwidth_mbytes_sec) { u32 arb_tolerance_compensation_nsec, arb_tolerance_compensation_div; - const struct tegra_mc_la *la = &client->la; unsigned int fifo_size = client->fifo_size; u32 arb_nsec, la_ticks, value; @@ -1149,12 +1280,12 @@ static void tegra30_mc_tune_client_latency(struct tegra_mc *mc, * request. */ la_ticks = arb_nsec / mc->tick; - la_ticks = min(la_ticks, la->mask); + la_ticks = min(la_ticks, client->regs.la.mask); - value = mc_readl(mc, la->reg); - value &= ~(la->mask << la->shift); - value |= la_ticks << la->shift; - mc_writel(mc, value, la->reg); + value = mc_readl(mc, client->regs.la.reg); + value &= ~(client->regs.la.mask << client->regs.la.shift); + value |= la_ticks << client->regs.la.shift; + mc_writel(mc, value, client->regs.la.reg); } static int tegra30_mc_icc_set(struct icc_node *src, struct icc_node *dst) diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index d2fbe6a8b25b..dd26505464c2 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -17,25 +17,12 @@ struct clk; struct device; struct page; -struct tegra_smmu_enable { - unsigned int reg; - unsigned int bit; -}; - struct tegra_mc_timing { unsigned long rate; u32 *emem_data; }; -/* latency allowance */ -struct tegra_mc_la { - unsigned int reg; - unsigned int shift; - unsigned int mask; - unsigned int def; -}; - struct tegra_mc_client { unsigned int id; const char *name; @@ -43,8 +30,21 @@ struct tegra_mc_client { unsigned int fifo_size; - struct tegra_smmu_enable smmu; - struct tegra_mc_la la; + struct { + /* Tegra SMMU enable */ + struct { + unsigned int reg; + unsigned int bit; + } smmu; + + /* latency allowance */ + struct { + unsigned int reg; + unsigned int shift; + unsigned int mask; + unsigned int def; + } la; + } regs; }; struct tegra_smmu_swgroup { -- cgit v1.2.3 From e899993845e60cc24d8e667a312eaa03a05d21ec Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 2 Jun 2021 18:32:52 +0200 Subject: memory: tegra: Unify struct tegra_mc across SoC generations As another step towards unifying both the Tegra210 (and earlier) and Tegra186 (and later) memory controller drivers, unify the structures that are used to represent them. Note that this comes at a slight space penalty since some fields are not used on all generations, but the benefits of unifying the driver outweigh the downsides. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210602163302.120041-3-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra186.c | 1281 +++++++++++++++++++++++++-------------- include/soc/tegra/mc.h | 18 +- 2 files changed, 852 insertions(+), 447 deletions(-) (limited to 'include') diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index e25c954dde2e..8e77567d1378 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -9,6 +9,8 @@ #include #include +#include + #if defined(CONFIG_ARCH_TEGRA_186_SOC) #include #endif @@ -17,47 +19,26 @@ #include #endif -struct tegra186_mc_client { - const char *name; - unsigned int sid; - struct { - unsigned int override; - unsigned int security; - } regs; -}; - -struct tegra186_mc_soc { - const struct tegra186_mc_client *clients; - unsigned int num_clients; -}; - -struct tegra186_mc { - struct device *dev; - void __iomem *regs; - - const struct tegra186_mc_soc *soc; -}; - -static void tegra186_mc_program_sid(struct tegra186_mc *mc) +static void tegra186_mc_program_sid(struct tegra_mc *mc) { unsigned int i; for (i = 0; i < mc->soc->num_clients; i++) { - const struct tegra186_mc_client *client = &mc->soc->clients[i]; + const struct tegra_mc_client *client = &mc->soc->clients[i]; u32 override, security; - override = readl(mc->regs + client->regs.override); - security = readl(mc->regs + client->regs.security); + override = readl(mc->regs + client->regs.sid.override); + security = readl(mc->regs + client->regs.sid.security); dev_dbg(mc->dev, "client %s: override: %x security: %x\n", client->name, override, security); dev_dbg(mc->dev, "setting SID %u for %s\n", client->sid, client->name); - writel(client->sid, mc->regs + client->regs.override); + writel(client->sid, mc->regs + client->regs.sid.override); - override = readl(mc->regs + client->regs.override); - security = readl(mc->regs + client->regs.security); + override = readl(mc->regs + client->regs.sid.override); + security = readl(mc->regs + client->regs.sid.security); dev_dbg(mc->dev, "client %s: override: %x security: %x\n", client->name, override, security); @@ -65,1457 +46,1867 @@ static void tegra186_mc_program_sid(struct tegra186_mc *mc) } #if defined(CONFIG_ARCH_TEGRA_186_SOC) -static const struct tegra186_mc_client tegra186_mc_clients[] = { +static const struct tegra_mc_client tegra186_mc_clients[] = { { .name = "ptcr", .sid = TEGRA186_SID_PASSTHROUGH, .regs = { - .override = 0x000, - .security = 0x004, + .sid = { + .override = 0x000, + .security = 0x004, + }, }, }, { .name = "afir", .sid = TEGRA186_SID_AFI, .regs = { - .override = 0x070, - .security = 0x074, + .sid = { + .override = 0x070, + .security = 0x074, + }, }, }, { .name = "hdar", .sid = TEGRA186_SID_HDA, .regs = { - .override = 0x0a8, - .security = 0x0ac, + .sid = { + .override = 0x0a8, + .security = 0x0ac, + }, }, }, { .name = "host1xdmar", .sid = TEGRA186_SID_HOST1X, .regs = { - .override = 0x0b0, - .security = 0x0b4, + .sid = { + .override = 0x0b0, + .security = 0x0b4, + }, }, }, { .name = "nvencsrd", .sid = TEGRA186_SID_NVENC, .regs = { - .override = 0x0e0, - .security = 0x0e4, + .sid = { + .override = 0x0e0, + .security = 0x0e4, + }, }, }, { .name = "satar", .sid = TEGRA186_SID_SATA, .regs = { - .override = 0x0f8, - .security = 0x0fc, + .sid = { + .override = 0x0f8, + .security = 0x0fc, + }, }, }, { .name = "mpcorer", .sid = TEGRA186_SID_PASSTHROUGH, .regs = { - .override = 0x138, - .security = 0x13c, + .sid = { + .override = 0x138, + .security = 0x13c, + }, }, }, { .name = "nvencswr", .sid = TEGRA186_SID_NVENC, .regs = { - .override = 0x158, - .security = 0x15c, + .sid = { + .override = 0x158, + .security = 0x15c, + }, }, }, { .name = "afiw", .sid = TEGRA186_SID_AFI, .regs = { - .override = 0x188, - .security = 0x18c, + .sid = { + .override = 0x188, + .security = 0x18c, + }, }, }, { .name = "hdaw", .sid = TEGRA186_SID_HDA, .regs = { - .override = 0x1a8, - .security = 0x1ac, + .sid = { + .override = 0x1a8, + .security = 0x1ac, + }, }, }, { .name = "mpcorew", .sid = TEGRA186_SID_PASSTHROUGH, .regs = { - .override = 0x1c8, - .security = 0x1cc, + .sid = { + .override = 0x1c8, + .security = 0x1cc, + }, }, }, { .name = "sataw", .sid = TEGRA186_SID_SATA, .regs = { - .override = 0x1e8, - .security = 0x1ec, + .sid = { + .override = 0x1e8, + .security = 0x1ec, + }, }, }, { .name = "ispra", .sid = TEGRA186_SID_ISP, .regs = { - .override = 0x220, - .security = 0x224, + .sid = { + .override = 0x220, + .security = 0x224, + }, }, }, { .name = "ispwa", .sid = TEGRA186_SID_ISP, .regs = { - .override = 0x230, - .security = 0x234, + .sid = { + .override = 0x230, + .security = 0x234, + }, }, }, { .name = "ispwb", .sid = TEGRA186_SID_ISP, .regs = { - .override = 0x238, - .security = 0x23c, + .sid = { + .override = 0x238, + .security = 0x23c, + }, }, }, { .name = "xusb_hostr", .sid = TEGRA186_SID_XUSB_HOST, .regs = { - .override = 0x250, - .security = 0x254, + .sid = { + .override = 0x250, + .security = 0x254, + }, }, }, { .name = "xusb_hostw", .sid = TEGRA186_SID_XUSB_HOST, .regs = { - .override = 0x258, - .security = 0x25c, + .sid = { + .override = 0x258, + .security = 0x25c, + }, }, }, { .name = "xusb_devr", .sid = TEGRA186_SID_XUSB_DEV, .regs = { - .override = 0x260, - .security = 0x264, + .sid = { + .override = 0x260, + .security = 0x264, + }, }, }, { .name = "xusb_devw", .sid = TEGRA186_SID_XUSB_DEV, .regs = { - .override = 0x268, - .security = 0x26c, + .sid = { + .override = 0x268, + .security = 0x26c, + }, }, }, { .name = "tsecsrd", .sid = TEGRA186_SID_TSEC, .regs = { - .override = 0x2a0, - .security = 0x2a4, + .sid = { + .override = 0x2a0, + .security = 0x2a4, + }, }, }, { .name = "tsecswr", .sid = TEGRA186_SID_TSEC, .regs = { - .override = 0x2a8, - .security = 0x2ac, + .sid = { + .override = 0x2a8, + .security = 0x2ac, + }, }, }, { .name = "gpusrd", .sid = TEGRA186_SID_GPU, .regs = { - .override = 0x2c0, - .security = 0x2c4, + .sid = { + .override = 0x2c0, + .security = 0x2c4, + }, }, }, { .name = "gpuswr", .sid = TEGRA186_SID_GPU, .regs = { - .override = 0x2c8, - .security = 0x2cc, + .sid = { + .override = 0x2c8, + .security = 0x2cc, + }, }, }, { .name = "sdmmcra", .sid = TEGRA186_SID_SDMMC1, .regs = { - .override = 0x300, - .security = 0x304, + .sid = { + .override = 0x300, + .security = 0x304, + }, }, }, { .name = "sdmmcraa", .sid = TEGRA186_SID_SDMMC2, .regs = { - .override = 0x308, - .security = 0x30c, + .sid = { + .override = 0x308, + .security = 0x30c, + }, }, }, { .name = "sdmmcr", .sid = TEGRA186_SID_SDMMC3, .regs = { - .override = 0x310, - .security = 0x314, + .sid = { + .override = 0x310, + .security = 0x314, + }, }, }, { .name = "sdmmcrab", .sid = TEGRA186_SID_SDMMC4, .regs = { - .override = 0x318, - .security = 0x31c, + .sid = { + .override = 0x318, + .security = 0x31c, + }, }, }, { .name = "sdmmcwa", .sid = TEGRA186_SID_SDMMC1, .regs = { - .override = 0x320, - .security = 0x324, + .sid = { + .override = 0x320, + .security = 0x324, + }, }, }, { .name = "sdmmcwaa", .sid = TEGRA186_SID_SDMMC2, .regs = { - .override = 0x328, - .security = 0x32c, + .sid = { + .override = 0x328, + .security = 0x32c, + }, }, }, { .name = "sdmmcw", .sid = TEGRA186_SID_SDMMC3, .regs = { - .override = 0x330, - .security = 0x334, + .sid = { + .override = 0x330, + .security = 0x334, + }, }, }, { .name = "sdmmcwab", .sid = TEGRA186_SID_SDMMC4, .regs = { - .override = 0x338, - .security = 0x33c, + .sid = { + .override = 0x338, + .security = 0x33c, + }, }, }, { .name = "vicsrd", .sid = TEGRA186_SID_VIC, .regs = { - .override = 0x360, - .security = 0x364, + .sid = { + .override = 0x360, + .security = 0x364, + }, }, }, { .name = "vicswr", .sid = TEGRA186_SID_VIC, .regs = { - .override = 0x368, - .security = 0x36c, + .sid = { + .override = 0x368, + .security = 0x36c, + }, }, }, { .name = "viw", .sid = TEGRA186_SID_VI, .regs = { - .override = 0x390, - .security = 0x394, + .sid = { + .override = 0x390, + .security = 0x394, + }, }, }, { .name = "nvdecsrd", .sid = TEGRA186_SID_NVDEC, .regs = { - .override = 0x3c0, - .security = 0x3c4, + .sid = { + .override = 0x3c0, + .security = 0x3c4, + }, }, }, { .name = "nvdecswr", .sid = TEGRA186_SID_NVDEC, .regs = { - .override = 0x3c8, - .security = 0x3cc, + .sid = { + .override = 0x3c8, + .security = 0x3cc, + }, }, }, { .name = "aper", .sid = TEGRA186_SID_APE, .regs = { - .override = 0x3d0, - .security = 0x3d4, + .sid = { + .override = 0x3d0, + .security = 0x3d4, + }, }, }, { .name = "apew", .sid = TEGRA186_SID_APE, .regs = { - .override = 0x3d8, - .security = 0x3dc, + .sid = { + .override = 0x3d8, + .security = 0x3dc, + }, }, }, { .name = "nvjpgsrd", .sid = TEGRA186_SID_NVJPG, .regs = { - .override = 0x3f0, - .security = 0x3f4, + .sid = { + .override = 0x3f0, + .security = 0x3f4, + }, }, }, { .name = "nvjpgswr", .sid = TEGRA186_SID_NVJPG, .regs = { - .override = 0x3f8, - .security = 0x3fc, + .sid = { + .override = 0x3f8, + .security = 0x3fc, + }, }, }, { .name = "sesrd", .sid = TEGRA186_SID_SE, .regs = { - .override = 0x400, - .security = 0x404, + .sid = { + .override = 0x400, + .security = 0x404, + }, }, }, { .name = "seswr", .sid = TEGRA186_SID_SE, .regs = { - .override = 0x408, - .security = 0x40c, + .sid = { + .override = 0x408, + .security = 0x40c, + }, }, }, { .name = "etrr", .sid = TEGRA186_SID_ETR, .regs = { - .override = 0x420, - .security = 0x424, + .sid = { + .override = 0x420, + .security = 0x424, + }, }, }, { .name = "etrw", .sid = TEGRA186_SID_ETR, .regs = { - .override = 0x428, - .security = 0x42c, + .sid = { + .override = 0x428, + .security = 0x42c, + }, }, }, { .name = "tsecsrdb", .sid = TEGRA186_SID_TSECB, .regs = { - .override = 0x430, - .security = 0x434, + .sid = { + .override = 0x430, + .security = 0x434, + }, }, }, { .name = "tsecswrb", .sid = TEGRA186_SID_TSECB, .regs = { - .override = 0x438, - .security = 0x43c, + .sid = { + .override = 0x438, + .security = 0x43c, + }, }, }, { .name = "gpusrd2", .sid = TEGRA186_SID_GPU, .regs = { - .override = 0x440, - .security = 0x444, + .sid = { + .override = 0x440, + .security = 0x444, + }, }, }, { .name = "gpuswr2", .sid = TEGRA186_SID_GPU, .regs = { - .override = 0x448, - .security = 0x44c, + .sid = { + .override = 0x448, + .security = 0x44c, + }, }, }, { .name = "axisr", .sid = TEGRA186_SID_GPCDMA_0, .regs = { - .override = 0x460, - .security = 0x464, + .sid = { + .override = 0x460, + .security = 0x464, + }, }, }, { .name = "axisw", .sid = TEGRA186_SID_GPCDMA_0, .regs = { - .override = 0x468, - .security = 0x46c, + .sid = { + .override = 0x468, + .security = 0x46c, + }, }, }, { .name = "eqosr", .sid = TEGRA186_SID_EQOS, .regs = { - .override = 0x470, - .security = 0x474, + .sid = { + .override = 0x470, + .security = 0x474, + }, }, }, { .name = "eqosw", .sid = TEGRA186_SID_EQOS, .regs = { - .override = 0x478, - .security = 0x47c, + .sid = { + .override = 0x478, + .security = 0x47c, + }, }, }, { .name = "ufshcr", .sid = TEGRA186_SID_UFSHC, .regs = { - .override = 0x480, - .security = 0x484, + .sid = { + .override = 0x480, + .security = 0x484, + }, }, }, { .name = "ufshcw", .sid = TEGRA186_SID_UFSHC, .regs = { - .override = 0x488, - .security = 0x48c, + .sid = { + .override = 0x488, + .security = 0x48c, + }, }, }, { .name = "nvdisplayr", .sid = TEGRA186_SID_NVDISPLAY, .regs = { - .override = 0x490, - .security = 0x494, + .sid = { + .override = 0x490, + .security = 0x494, + }, }, }, { .name = "bpmpr", .sid = TEGRA186_SID_BPMP, .regs = { - .override = 0x498, - .security = 0x49c, + .sid = { + .override = 0x498, + .security = 0x49c, + }, }, }, { .name = "bpmpw", .sid = TEGRA186_SID_BPMP, .regs = { - .override = 0x4a0, - .security = 0x4a4, + .sid = { + .override = 0x4a0, + .security = 0x4a4, + }, }, }, { .name = "bpmpdmar", .sid = TEGRA186_SID_BPMP, .regs = { - .override = 0x4a8, - .security = 0x4ac, + .sid = { + .override = 0x4a8, + .security = 0x4ac, + }, }, }, { .name = "bpmpdmaw", .sid = TEGRA186_SID_BPMP, .regs = { - .override = 0x4b0, - .security = 0x4b4, + .sid = { + .override = 0x4b0, + .security = 0x4b4, + }, }, }, { .name = "aonr", .sid = TEGRA186_SID_AON, .regs = { - .override = 0x4b8, - .security = 0x4bc, + .sid = { + .override = 0x4b8, + .security = 0x4bc, + }, }, }, { .name = "aonw", .sid = TEGRA186_SID_AON, .regs = { - .override = 0x4c0, - .security = 0x4c4, + .sid = { + .override = 0x4c0, + .security = 0x4c4, + }, }, }, { .name = "aondmar", .sid = TEGRA186_SID_AON, .regs = { - .override = 0x4c8, - .security = 0x4cc, + .sid = { + .override = 0x4c8, + .security = 0x4cc, + }, }, }, { .name = "aondmaw", .sid = TEGRA186_SID_AON, .regs = { - .override = 0x4d0, - .security = 0x4d4, + .sid = { + .override = 0x4d0, + .security = 0x4d4, + }, }, }, { .name = "scer", .sid = TEGRA186_SID_SCE, .regs = { - .override = 0x4d8, - .security = 0x4dc, + .sid = { + .override = 0x4d8, + .security = 0x4dc, + }, }, }, { .name = "scew", .sid = TEGRA186_SID_SCE, .regs = { - .override = 0x4e0, - .security = 0x4e4, + .sid = { + .override = 0x4e0, + .security = 0x4e4, + }, }, }, { .name = "scedmar", .sid = TEGRA186_SID_SCE, .regs = { - .override = 0x4e8, - .security = 0x4ec, + .sid = { + .override = 0x4e8, + .security = 0x4ec, + }, }, }, { .name = "scedmaw", .sid = TEGRA186_SID_SCE, .regs = { - .override = 0x4f0, - .security = 0x4f4, + .sid = { + .override = 0x4f0, + .security = 0x4f4, + }, }, }, { .name = "apedmar", .sid = TEGRA186_SID_APE, .regs = { - .override = 0x4f8, - .security = 0x4fc, + .sid = { + .override = 0x4f8, + .security = 0x4fc, + }, }, }, { .name = "apedmaw", .sid = TEGRA186_SID_APE, .regs = { - .override = 0x500, - .security = 0x504, + .sid = { + .override = 0x500, + .security = 0x504, + }, }, }, { .name = "nvdisplayr1", .sid = TEGRA186_SID_NVDISPLAY, .regs = { - .override = 0x508, - .security = 0x50c, + .sid = { + .override = 0x508, + .security = 0x50c, + }, }, }, { .name = "vicsrd1", .sid = TEGRA186_SID_VIC, .regs = { - .override = 0x510, - .security = 0x514, + .sid = { + .override = 0x510, + .security = 0x514, + }, }, }, { .name = "nvdecsrd1", .sid = TEGRA186_SID_NVDEC, .regs = { - .override = 0x518, - .security = 0x51c, + .sid = { + .override = 0x518, + .security = 0x51c, + }, }, }, }; -static const struct tegra186_mc_soc tegra186_mc_soc = { +static const struct tegra_mc_soc tegra186_mc_soc = { .num_clients = ARRAY_SIZE(tegra186_mc_clients), .clients = tegra186_mc_clients, }; #endif #if defined(CONFIG_ARCH_TEGRA_194_SOC) -static const struct tegra186_mc_client tegra194_mc_clients[] = { +static const struct tegra_mc_client tegra194_mc_clients[] = { { .name = "ptcr", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x000, - .security = 0x004, + .sid = { + .override = 0x000, + .security = 0x004, + }, }, }, { .name = "miu7r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x008, - .security = 0x00c, + .sid = { + .override = 0x008, + .security = 0x00c, + }, }, }, { .name = "miu7w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x010, - .security = 0x014, + .sid = { + .override = 0x010, + .security = 0x014, + }, }, }, { .name = "hdar", .sid = TEGRA194_SID_HDA, .regs = { - .override = 0x0a8, - .security = 0x0ac, + .sid = { + .override = 0x0a8, + .security = 0x0ac, + }, }, }, { .name = "host1xdmar", .sid = TEGRA194_SID_HOST1X, .regs = { - .override = 0x0b0, - .security = 0x0b4, + .sid = { + .override = 0x0b0, + .security = 0x0b4, + }, }, }, { .name = "nvencsrd", .sid = TEGRA194_SID_NVENC, .regs = { - .override = 0x0e0, - .security = 0x0e4, + .sid = { + .override = 0x0e0, + .security = 0x0e4, + }, }, }, { .name = "satar", .sid = TEGRA194_SID_SATA, .regs = { - .override = 0x0f8, - .security = 0x0fc, + .sid = { + .override = 0x0f8, + .security = 0x0fc, + }, }, }, { .name = "mpcorer", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x138, - .security = 0x13c, + .sid = { + .override = 0x138, + .security = 0x13c, + }, }, }, { .name = "nvencswr", .sid = TEGRA194_SID_NVENC, .regs = { - .override = 0x158, - .security = 0x15c, + .sid = { + .override = 0x158, + .security = 0x15c, + }, }, }, { .name = "hdaw", .sid = TEGRA194_SID_HDA, .regs = { - .override = 0x1a8, - .security = 0x1ac, + .sid = { + .override = 0x1a8, + .security = 0x1ac, + }, }, }, { .name = "mpcorew", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x1c8, - .security = 0x1cc, + .sid = { + .override = 0x1c8, + .security = 0x1cc, + }, }, }, { .name = "sataw", .sid = TEGRA194_SID_SATA, .regs = { - .override = 0x1e8, - .security = 0x1ec, + .sid = { + .override = 0x1e8, + .security = 0x1ec, + }, }, }, { .name = "ispra", .sid = TEGRA194_SID_ISP, .regs = { - .override = 0x220, - .security = 0x224, + .sid = { + .override = 0x220, + .security = 0x224, + }, }, }, { .name = "ispfalr", .sid = TEGRA194_SID_ISP_FALCON, .regs = { - .override = 0x228, - .security = 0x22c, + .sid = { + .override = 0x228, + .security = 0x22c, + }, }, }, { .name = "ispwa", .sid = TEGRA194_SID_ISP, .regs = { - .override = 0x230, - .security = 0x234, + .sid = { + .override = 0x230, + .security = 0x234, + }, }, }, { .name = "ispwb", .sid = TEGRA194_SID_ISP, .regs = { - .override = 0x238, - .security = 0x23c, + .sid = { + .override = 0x238, + .security = 0x23c, + }, }, }, { .name = "xusb_hostr", .sid = TEGRA194_SID_XUSB_HOST, .regs = { - .override = 0x250, - .security = 0x254, + .sid = { + .override = 0x250, + .security = 0x254, + }, }, }, { .name = "xusb_hostw", .sid = TEGRA194_SID_XUSB_HOST, .regs = { - .override = 0x258, - .security = 0x25c, + .sid = { + .override = 0x258, + .security = 0x25c, + }, }, }, { .name = "xusb_devr", .sid = TEGRA194_SID_XUSB_DEV, .regs = { - .override = 0x260, - .security = 0x264, + .sid = { + .override = 0x260, + .security = 0x264, + }, }, }, { .name = "xusb_devw", .sid = TEGRA194_SID_XUSB_DEV, .regs = { - .override = 0x268, - .security = 0x26c, + .sid = { + .override = 0x268, + .security = 0x26c, + }, }, }, { .name = "sdmmcra", .sid = TEGRA194_SID_SDMMC1, .regs = { - .override = 0x300, - .security = 0x304, + .sid = { + .override = 0x300, + .security = 0x304, + }, }, }, { .name = "sdmmcr", .sid = TEGRA194_SID_SDMMC3, .regs = { - .override = 0x310, - .security = 0x314, + .sid = { + .override = 0x310, + .security = 0x314, + }, }, }, { .name = "sdmmcrab", .sid = TEGRA194_SID_SDMMC4, .regs = { - .override = 0x318, - .security = 0x31c, + .sid = { + .override = 0x318, + .security = 0x31c, + }, }, }, { .name = "sdmmcwa", .sid = TEGRA194_SID_SDMMC1, .regs = { - .override = 0x320, - .security = 0x324, + .sid = { + .override = 0x320, + .security = 0x324, + }, }, }, { .name = "sdmmcw", .sid = TEGRA194_SID_SDMMC3, .regs = { - .override = 0x330, - .security = 0x334, + .sid = { + .override = 0x330, + .security = 0x334, + }, }, }, { .name = "sdmmcwab", .sid = TEGRA194_SID_SDMMC4, .regs = { - .override = 0x338, - .security = 0x33c, + .sid = { + .override = 0x338, + .security = 0x33c, + }, }, }, { .name = "vicsrd", .sid = TEGRA194_SID_VIC, .regs = { - .override = 0x360, - .security = 0x364, + .sid = { + .override = 0x360, + .security = 0x364, + }, }, }, { .name = "vicswr", .sid = TEGRA194_SID_VIC, .regs = { - .override = 0x368, - .security = 0x36c, + .sid = { + .override = 0x368, + .security = 0x36c, + }, }, }, { .name = "viw", .sid = TEGRA194_SID_VI, .regs = { - .override = 0x390, - .security = 0x394, + .sid = { + .override = 0x390, + .security = 0x394, + }, }, }, { .name = "nvdecsrd", .sid = TEGRA194_SID_NVDEC, .regs = { - .override = 0x3c0, - .security = 0x3c4, + .sid = { + .override = 0x3c0, + .security = 0x3c4, + }, }, }, { .name = "nvdecswr", .sid = TEGRA194_SID_NVDEC, .regs = { - .override = 0x3c8, - .security = 0x3cc, + .sid = { + .override = 0x3c8, + .security = 0x3cc, + }, }, }, { .name = "aper", .sid = TEGRA194_SID_APE, .regs = { - .override = 0x3c0, - .security = 0x3c4, + .sid = { + .override = 0x3c0, + .security = 0x3c4, + }, }, }, { .name = "apew", .sid = TEGRA194_SID_APE, .regs = { - .override = 0x3d0, - .security = 0x3d4, + .sid = { + .override = 0x3d0, + .security = 0x3d4, + }, }, }, { .name = "nvjpgsrd", .sid = TEGRA194_SID_NVJPG, .regs = { - .override = 0x3f0, - .security = 0x3f4, + .sid = { + .override = 0x3f0, + .security = 0x3f4, + }, }, }, { .name = "nvjpgswr", .sid = TEGRA194_SID_NVJPG, .regs = { - .override = 0x3f0, - .security = 0x3f4, + .sid = { + .override = 0x3f0, + .security = 0x3f4, + }, }, }, { .name = "axiapr", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x410, - .security = 0x414, + .sid = { + .override = 0x410, + .security = 0x414, + }, }, }, { .name = "axiapw", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x418, - .security = 0x41c, + .sid = { + .override = 0x418, + .security = 0x41c, + }, }, }, { .name = "etrr", .sid = TEGRA194_SID_ETR, .regs = { - .override = 0x420, - .security = 0x424, + .sid = { + .override = 0x420, + .security = 0x424, + }, }, }, { .name = "etrw", .sid = TEGRA194_SID_ETR, .regs = { - .override = 0x428, - .security = 0x42c, + .sid = { + .override = 0x428, + .security = 0x42c, + }, }, }, { .name = "axisr", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x460, - .security = 0x464, + .sid = { + .override = 0x460, + .security = 0x464, + }, }, }, { .name = "axisw", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x468, - .security = 0x46c, + .sid = { + .override = 0x468, + .security = 0x46c, + }, }, }, { .name = "eqosr", .sid = TEGRA194_SID_EQOS, .regs = { - .override = 0x470, - .security = 0x474, + .sid = { + .override = 0x470, + .security = 0x474, + }, }, }, { .name = "eqosw", .sid = TEGRA194_SID_EQOS, .regs = { - .override = 0x478, - .security = 0x47c, + .sid = { + .override = 0x478, + .security = 0x47c, + }, }, }, { .name = "ufshcr", .sid = TEGRA194_SID_UFSHC, .regs = { - .override = 0x480, - .security = 0x484, + .sid = { + .override = 0x480, + .security = 0x484, + }, }, }, { .name = "ufshcw", .sid = TEGRA194_SID_UFSHC, .regs = { - .override = 0x488, - .security = 0x48c, + .sid = { + .override = 0x488, + .security = 0x48c, + }, }, }, { .name = "nvdisplayr", .sid = TEGRA194_SID_NVDISPLAY, .regs = { - .override = 0x490, - .security = 0x494, + .sid = { + .override = 0x490, + .security = 0x494, + }, }, }, { .name = "bpmpr", .sid = TEGRA194_SID_BPMP, .regs = { - .override = 0x498, - .security = 0x49c, + .sid = { + .override = 0x498, + .security = 0x49c, + }, }, }, { .name = "bpmpw", .sid = TEGRA194_SID_BPMP, .regs = { - .override = 0x4a0, - .security = 0x4a4, + .sid = { + .override = 0x4a0, + .security = 0x4a4, + }, }, }, { .name = "bpmpdmar", .sid = TEGRA194_SID_BPMP, .regs = { - .override = 0x4a8, - .security = 0x4ac, + .sid = { + .override = 0x4a8, + .security = 0x4ac, + }, }, }, { .name = "bpmpdmaw", .sid = TEGRA194_SID_BPMP, .regs = { - .override = 0x4b0, - .security = 0x4b4, + .sid = { + .override = 0x4b0, + .security = 0x4b4, + }, }, }, { .name = "aonr", .sid = TEGRA194_SID_AON, .regs = { - .override = 0x4b8, - .security = 0x4bc, + .sid = { + .override = 0x4b8, + .security = 0x4bc, + }, }, }, { .name = "aonw", .sid = TEGRA194_SID_AON, .regs = { - .override = 0x4c0, - .security = 0x4c4, + .sid = { + .override = 0x4c0, + .security = 0x4c4, + }, }, }, { .name = "aondmar", .sid = TEGRA194_SID_AON, .regs = { - .override = 0x4c8, - .security = 0x4cc, + .sid = { + .override = 0x4c8, + .security = 0x4cc, + }, }, }, { .name = "aondmaw", .sid = TEGRA194_SID_AON, .regs = { - .override = 0x4d0, - .security = 0x4d4, + .sid = { + .override = 0x4d0, + .security = 0x4d4, + }, }, }, { .name = "scer", .sid = TEGRA194_SID_SCE, .regs = { - .override = 0x4d8, - .security = 0x4dc, + .sid = { + .override = 0x4d8, + .security = 0x4dc, + }, }, }, { .name = "scew", .sid = TEGRA194_SID_SCE, .regs = { - .override = 0x4e0, - .security = 0x4e4, + .sid = { + .override = 0x4e0, + .security = 0x4e4, + }, }, }, { .name = "scedmar", .sid = TEGRA194_SID_SCE, .regs = { - .override = 0x4e8, - .security = 0x4ec, + .sid = { + .override = 0x4e8, + .security = 0x4ec, + }, }, }, { .name = "scedmaw", .sid = TEGRA194_SID_SCE, .regs = { - .override = 0x4f0, - .security = 0x4f4, + .sid = { + .override = 0x4f0, + .security = 0x4f4, + }, }, }, { .name = "apedmar", .sid = TEGRA194_SID_APE, .regs = { - .override = 0x4f8, - .security = 0x4fc, + .sid = { + .override = 0x4f8, + .security = 0x4fc, + }, }, }, { .name = "apedmaw", .sid = TEGRA194_SID_APE, .regs = { - .override = 0x500, - .security = 0x504, + .sid = { + .override = 0x500, + .security = 0x504, + }, }, }, { .name = "nvdisplayr1", .sid = TEGRA194_SID_NVDISPLAY, .regs = { - .override = 0x508, - .security = 0x50c, + .sid = { + .override = 0x508, + .security = 0x50c, + }, }, }, { .name = "vicsrd1", .sid = TEGRA194_SID_VIC, .regs = { - .override = 0x510, - .security = 0x514, + .sid = { + .override = 0x510, + .security = 0x514, + }, }, }, { .name = "nvdecsrd1", .sid = TEGRA194_SID_NVDEC, .regs = { - .override = 0x518, - .security = 0x51c, + .sid = { + .override = 0x518, + .security = 0x51c, + }, }, }, { .name = "miu0r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x530, - .security = 0x534, + .sid = { + .override = 0x530, + .security = 0x534, + }, }, }, { .name = "miu0w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x538, - .security = 0x53c, + .sid = { + .override = 0x538, + .security = 0x53c, + }, }, }, { .name = "miu1r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x540, - .security = 0x544, + .sid = { + .override = 0x540, + .security = 0x544, + }, }, }, { .name = "miu1w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x548, - .security = 0x54c, + .sid = { + .override = 0x548, + .security = 0x54c, + }, }, }, { .name = "miu2r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x570, - .security = 0x574, + .sid = { + .override = 0x570, + .security = 0x574, + }, }, }, { .name = "miu2w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x578, - .security = 0x57c, + .sid = { + .override = 0x578, + .security = 0x57c, + }, }, }, { .name = "miu3r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x580, - .security = 0x584, + .sid = { + .override = 0x580, + .security = 0x584, + }, }, }, { .name = "miu3w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x588, - .security = 0x58c, + .sid = { + .override = 0x588, + .security = 0x58c, + }, }, }, { .name = "miu4r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x590, - .security = 0x594, + .sid = { + .override = 0x590, + .security = 0x594, + }, }, }, { .name = "miu4w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x598, - .security = 0x59c, + .sid = { + .override = 0x598, + .security = 0x59c, + }, }, }, { .name = "dpmur", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x598, - .security = 0x59c, + .sid = { + .override = 0x598, + .security = 0x59c, + }, }, }, { .name = "vifalr", .sid = TEGRA194_SID_VI_FALCON, .regs = { - .override = 0x5e0, - .security = 0x5e4, + .sid = { + .override = 0x5e0, + .security = 0x5e4, + }, }, }, { .name = "vifalw", .sid = TEGRA194_SID_VI_FALCON, .regs = { - .override = 0x5e8, - .security = 0x5ec, + .sid = { + .override = 0x5e8, + .security = 0x5ec, + }, }, }, { .name = "dla0rda", .sid = TEGRA194_SID_NVDLA0, .regs = { - .override = 0x5f0, - .security = 0x5f4, + .sid = { + .override = 0x5f0, + .security = 0x5f4, + }, }, }, { .name = "dla0falrdb", .sid = TEGRA194_SID_NVDLA0, .regs = { - .override = 0x5f8, - .security = 0x5fc, + .sid = { + .override = 0x5f8, + .security = 0x5fc, + }, }, }, { .name = "dla0wra", .sid = TEGRA194_SID_NVDLA0, .regs = { - .override = 0x600, - .security = 0x604, + .sid = { + .override = 0x600, + .security = 0x604, + }, }, }, { .name = "dla0falwrb", .sid = TEGRA194_SID_NVDLA0, .regs = { - .override = 0x608, - .security = 0x60c, + .sid = { + .override = 0x608, + .security = 0x60c, + }, }, }, { .name = "dla1rda", .sid = TEGRA194_SID_NVDLA1, .regs = { - .override = 0x610, - .security = 0x614, + .sid = { + .override = 0x610, + .security = 0x614, + }, }, }, { .name = "dla1falrdb", .sid = TEGRA194_SID_NVDLA1, .regs = { - .override = 0x618, - .security = 0x61c, + .sid = { + .override = 0x618, + .security = 0x61c, + }, }, }, { .name = "dla1wra", .sid = TEGRA194_SID_NVDLA1, .regs = { - .override = 0x620, - .security = 0x624, + .sid = { + .override = 0x620, + .security = 0x624, + }, }, }, { .name = "dla1falwrb", .sid = TEGRA194_SID_NVDLA1, .regs = { - .override = 0x628, - .security = 0x62c, + .sid = { + .override = 0x628, + .security = 0x62c, + }, }, }, { .name = "pva0rda", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x630, - .security = 0x634, + .sid = { + .override = 0x630, + .security = 0x634, + }, }, }, { .name = "pva0rdb", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x638, - .security = 0x63c, + .sid = { + .override = 0x638, + .security = 0x63c, + }, }, }, { .name = "pva0rdc", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x640, - .security = 0x644, + .sid = { + .override = 0x640, + .security = 0x644, + }, }, }, { .name = "pva0wra", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x648, - .security = 0x64c, + .sid = { + .override = 0x648, + .security = 0x64c, + }, }, }, { .name = "pva0wrb", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x650, - .security = 0x654, + .sid = { + .override = 0x650, + .security = 0x654, + }, }, }, { .name = "pva0wrc", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x658, - .security = 0x65c, + .sid = { + .override = 0x658, + .security = 0x65c, + }, }, }, { .name = "pva1rda", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x660, - .security = 0x664, + .sid = { + .override = 0x660, + .security = 0x664, + }, }, }, { .name = "pva1rdb", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x668, - .security = 0x66c, + .sid = { + .override = 0x668, + .security = 0x66c, + }, }, }, { .name = "pva1rdc", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x670, - .security = 0x674, + .sid = { + .override = 0x670, + .security = 0x674, + }, }, }, { .name = "pva1wra", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x678, - .security = 0x67c, + .sid = { + .override = 0x678, + .security = 0x67c, + }, }, }, { .name = "pva1wrb", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x680, - .security = 0x684, + .sid = { + .override = 0x680, + .security = 0x684, + }, }, }, { .name = "pva1wrc", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x688, - .security = 0x68c, + .sid = { + .override = 0x688, + .security = 0x68c, + }, }, }, { .name = "rcer", .sid = TEGRA194_SID_RCE, .regs = { - .override = 0x690, - .security = 0x694, + .sid = { + .override = 0x690, + .security = 0x694, + }, }, }, { .name = "rcew", .sid = TEGRA194_SID_RCE, .regs = { - .override = 0x698, - .security = 0x69c, + .sid = { + .override = 0x698, + .security = 0x69c, + }, }, }, { .name = "rcedmar", .sid = TEGRA194_SID_RCE, .regs = { - .override = 0x6a0, - .security = 0x6a4, + .sid = { + .override = 0x6a0, + .security = 0x6a4, + }, }, }, { .name = "rcedmaw", .sid = TEGRA194_SID_RCE, .regs = { - .override = 0x6a8, - .security = 0x6ac, + .sid = { + .override = 0x6a8, + .security = 0x6ac, + }, }, }, { .name = "nvenc1srd", .sid = TEGRA194_SID_NVENC1, .regs = { - .override = 0x6b0, - .security = 0x6b4, + .sid = { + .override = 0x6b0, + .security = 0x6b4, + }, }, }, { .name = "nvenc1swr", .sid = TEGRA194_SID_NVENC1, .regs = { - .override = 0x6b8, - .security = 0x6bc, + .sid = { + .override = 0x6b8, + .security = 0x6bc, + }, }, }, { .name = "pcie0r", .sid = TEGRA194_SID_PCIE0, .regs = { - .override = 0x6c0, - .security = 0x6c4, + .sid = { + .override = 0x6c0, + .security = 0x6c4, + }, }, }, { .name = "pcie0w", .sid = TEGRA194_SID_PCIE0, .regs = { - .override = 0x6c8, - .security = 0x6cc, + .sid = { + .override = 0x6c8, + .security = 0x6cc, + }, }, }, { .name = "pcie1r", .sid = TEGRA194_SID_PCIE1, .regs = { - .override = 0x6d0, - .security = 0x6d4, + .sid = { + .override = 0x6d0, + .security = 0x6d4, + }, }, }, { .name = "pcie1w", .sid = TEGRA194_SID_PCIE1, .regs = { - .override = 0x6d8, - .security = 0x6dc, + .sid = { + .override = 0x6d8, + .security = 0x6dc, + }, }, }, { .name = "pcie2ar", .sid = TEGRA194_SID_PCIE2, .regs = { - .override = 0x6e0, - .security = 0x6e4, + .sid = { + .override = 0x6e0, + .security = 0x6e4, + }, }, }, { .name = "pcie2aw", .sid = TEGRA194_SID_PCIE2, .regs = { - .override = 0x6e8, - .security = 0x6ec, + .sid = { + .override = 0x6e8, + .security = 0x6ec, + }, }, }, { .name = "pcie3r", .sid = TEGRA194_SID_PCIE3, .regs = { - .override = 0x6f0, - .security = 0x6f4, + .sid = { + .override = 0x6f0, + .security = 0x6f4, + }, }, }, { .name = "pcie3w", .sid = TEGRA194_SID_PCIE3, .regs = { - .override = 0x6f8, - .security = 0x6fc, + .sid = { + .override = 0x6f8, + .security = 0x6fc, + }, }, }, { .name = "pcie4r", .sid = TEGRA194_SID_PCIE4, .regs = { - .override = 0x700, - .security = 0x704, + .sid = { + .override = 0x700, + .security = 0x704, + }, }, }, { .name = "pcie4w", .sid = TEGRA194_SID_PCIE4, .regs = { - .override = 0x708, - .security = 0x70c, + .sid = { + .override = 0x708, + .security = 0x70c, + }, }, }, { .name = "pcie5r", .sid = TEGRA194_SID_PCIE5, .regs = { - .override = 0x710, - .security = 0x714, + .sid = { + .override = 0x710, + .security = 0x714, + }, }, }, { .name = "pcie5w", .sid = TEGRA194_SID_PCIE5, .regs = { - .override = 0x718, - .security = 0x71c, + .sid = { + .override = 0x718, + .security = 0x71c, + }, }, }, { .name = "ispfalw", .sid = TEGRA194_SID_ISP_FALCON, .regs = { - .override = 0x720, - .security = 0x724, + .sid = { + .override = 0x720, + .security = 0x724, + }, }, }, { .name = "dla0rda1", .sid = TEGRA194_SID_NVDLA0, .regs = { - .override = 0x748, - .security = 0x74c, + .sid = { + .override = 0x748, + .security = 0x74c, + }, }, }, { .name = "dla1rda1", .sid = TEGRA194_SID_NVDLA1, .regs = { - .override = 0x750, - .security = 0x754, + .sid = { + .override = 0x750, + .security = 0x754, + }, }, }, { .name = "pva0rda1", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x758, - .security = 0x75c, + .sid = { + .override = 0x758, + .security = 0x75c, + }, }, }, { .name = "pva0rdb1", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x760, - .security = 0x764, + .sid = { + .override = 0x760, + .security = 0x764, + }, }, }, { .name = "pva1rda1", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x768, - .security = 0x76c, + .sid = { + .override = 0x768, + .security = 0x76c, + }, }, }, { .name = "pva1rdb1", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x770, - .security = 0x774, + .sid = { + .override = 0x770, + .security = 0x774, + }, }, }, { .name = "pcie5r1", .sid = TEGRA194_SID_PCIE5, .regs = { - .override = 0x778, - .security = 0x77c, + .sid = { + .override = 0x778, + .security = 0x77c, + }, }, }, { .name = "nvencsrd1", .sid = TEGRA194_SID_NVENC, .regs = { - .override = 0x780, - .security = 0x784, + .sid = { + .override = 0x780, + .security = 0x784, + }, }, }, { .name = "nvenc1srd1", .sid = TEGRA194_SID_NVENC1, .regs = { - .override = 0x788, - .security = 0x78c, + .sid = { + .override = 0x788, + .security = 0x78c, + }, }, }, { .name = "ispra1", .sid = TEGRA194_SID_ISP, .regs = { - .override = 0x790, - .security = 0x794, + .sid = { + .override = 0x790, + .security = 0x794, + }, }, }, { .name = "pcie0r1", .sid = TEGRA194_SID_PCIE0, .regs = { - .override = 0x798, - .security = 0x79c, + .sid = { + .override = 0x798, + .security = 0x79c, + }, }, }, { .name = "nvdec1srd", .sid = TEGRA194_SID_NVDEC1, .regs = { - .override = 0x7c8, - .security = 0x7cc, + .sid = { + .override = 0x7c8, + .security = 0x7cc, + }, }, }, { .name = "nvdec1srd1", .sid = TEGRA194_SID_NVDEC1, .regs = { - .override = 0x7d0, - .security = 0x7d4, + .sid = { + .override = 0x7d0, + .security = 0x7d4, + }, }, }, { .name = "nvdec1swr", .sid = TEGRA194_SID_NVDEC1, .regs = { - .override = 0x7d8, - .security = 0x7dc, + .sid = { + .override = 0x7d8, + .security = 0x7dc, + }, }, }, { .name = "miu5r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x7e0, - .security = 0x7e4, + .sid = { + .override = 0x7e0, + .security = 0x7e4, + }, }, }, { .name = "miu5w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x7e8, - .security = 0x7ec, + .sid = { + .override = 0x7e8, + .security = 0x7ec, + }, }, }, { .name = "miu6r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x7f0, - .security = 0x7f4, + .sid = { + .override = 0x7f0, + .security = 0x7f4, + }, }, }, { .name = "miu6w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x7f8, - .security = 0x7fc, + .sid = { + .override = 0x7f8, + .security = 0x7fc, + }, }, }, }; -static const struct tegra186_mc_soc tegra194_mc_soc = { +static const struct tegra_mc_soc tegra194_mc_soc = { .num_clients = ARRAY_SIZE(tegra194_mc_clients), .clients = tegra194_mc_clients, }; @@ -1523,8 +1914,8 @@ static const struct tegra186_mc_soc tegra194_mc_soc = { static int tegra186_mc_probe(struct platform_device *pdev) { - struct tegra186_mc *mc; struct resource *res; + struct tegra_mc *mc; int err; mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); @@ -1552,7 +1943,7 @@ static int tegra186_mc_probe(struct platform_device *pdev) static int tegra186_mc_remove(struct platform_device *pdev) { - struct tegra186_mc *mc = platform_get_drvdata(pdev); + struct tegra_mc *mc = platform_get_drvdata(pdev); of_platform_depopulate(mc->dev); @@ -1577,7 +1968,7 @@ static int __maybe_unused tegra186_mc_suspend(struct device *dev) static int __maybe_unused tegra186_mc_resume(struct device *dev) { - struct tegra186_mc *mc = dev_get_drvdata(dev); + struct tegra_mc *mc = dev_get_drvdata(dev); tegra186_mc_program_sid(mc); diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index dd26505464c2..9da4ef52ce30 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -26,12 +26,20 @@ struct tegra_mc_timing { struct tegra_mc_client { unsigned int id; const char *name; - unsigned int swgroup; + /* + * For Tegra210 and earlier, this is the SWGROUP ID used for IOVA translations in the + * Tegra SMMU, whereas on Tegra186 and later this is the ID used to override the ARM SMMU + * stream ID used for IOVA translations for the given memory client. + */ + union { + unsigned int swgroup; + unsigned int sid; + }; unsigned int fifo_size; struct { - /* Tegra SMMU enable */ + /* Tegra SMMU enable (Tegra210 and earlier) */ struct { unsigned int reg; unsigned int bit; @@ -44,6 +52,12 @@ struct tegra_mc_client { unsigned int mask; unsigned int def; } la; + + /* stream ID overrides (Tegra186 and later) */ + struct { + unsigned int override; + unsigned int security; + } sid; } regs; }; -- cgit v1.2.3 From 6cc884c1c7fe5ae9362180d4f7d4091774921a0c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 2 Jun 2021 18:32:53 +0200 Subject: memory: tegra: Introduce struct tegra_mc_ops Subsequent patches will introduce further callbacks, so create a new struct tegra_mc_ops to collect all of them in a single place. Move the existing ->init() callback into the new structure. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210602163302.120041-4-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/mc.c | 4 ++-- drivers/memory/tegra/tegra20.c | 6 +++++- include/soc/tegra/mc.h | 7 +++++-- 3 files changed, 12 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index b7e104bf6614..559ae1ef5633 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -829,8 +829,8 @@ static int tegra_mc_probe(struct platform_device *pdev) mc->debugfs.root = debugfs_create_dir("mc", NULL); - if (mc->soc->init) { - err = mc->soc->init(mc); + if (mc->soc->ops && mc->soc->ops->init) { + err = mc->soc->ops->init(mc); if (err < 0) dev_err(&pdev->dev, "failed to initialize SoC driver: %d\n", err); diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index 2db68a913b7a..3b7b93b96480 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -687,6 +687,10 @@ static int tegra20_mc_init(struct tegra_mc *mc) return 0; } +static const struct tegra_mc_ops tegra20_mc_ops = { + .init = tegra20_mc_init, +}; + const struct tegra_mc_soc tegra20_mc_soc = { .clients = tegra20_mc_clients, .num_clients = ARRAY_SIZE(tegra20_mc_clients), @@ -698,5 +702,5 @@ const struct tegra_mc_soc tegra20_mc_soc = { .resets = tegra20_mc_resets, .num_resets = ARRAY_SIZE(tegra20_mc_resets), .icc_ops = &tegra20_mc_icc_ops, - .init = tegra20_mc_init, + .ops = &tegra20_mc_ops, }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 9da4ef52ce30..4f88da907a02 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -169,6 +169,10 @@ struct tegra_mc_icc_ops { void *data); }; +struct tegra_mc_ops { + int (*init)(struct tegra_mc *mc); +}; + struct tegra_mc_soc { const struct tegra_mc_client *clients; unsigned int num_clients; @@ -190,8 +194,7 @@ struct tegra_mc_soc { unsigned int num_resets; const struct tegra_mc_icc_ops *icc_ops; - - int (*init)(struct tegra_mc *mc); + const struct tegra_mc_ops *ops; }; struct tegra_mc { -- cgit v1.2.3 From 5c9016f0a8a3ba30c6593d2cb0d067164dd41846 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 2 Jun 2021 18:32:54 +0200 Subject: memory: tegra: Push suspend/resume into SoC drivers Continuing the scheme of unification, push suspend/resume callbacks into per-SoC driver so that they can be properly parameterized. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210602163302.120041-5-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/mc.c | 23 +++++++---------------- drivers/memory/tegra/tegra186.c | 27 +++++++++++++++++++++++---- drivers/memory/tegra/tegra20.c | 28 ++++++++++++++++++++++++++++ include/soc/tegra/mc.h | 2 ++ 4 files changed, 60 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 559ae1ef5633..a3b7ba33b7f9 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -867,37 +867,28 @@ static int tegra_mc_probe(struct platform_device *pdev) return 0; } -static int tegra_mc_suspend(struct device *dev) +static int __maybe_unused tegra_mc_suspend(struct device *dev) { struct tegra_mc *mc = dev_get_drvdata(dev); - int err; - if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { - err = tegra_gart_suspend(mc->gart); - if (err) - return err; - } + if (mc->soc->ops && mc->soc->ops->suspend) + return mc->soc->ops->suspend(mc); return 0; } -static int tegra_mc_resume(struct device *dev) +static int __maybe_unused tegra_mc_resume(struct device *dev) { struct tegra_mc *mc = dev_get_drvdata(dev); - int err; - if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { - err = tegra_gart_resume(mc->gart); - if (err) - return err; - } + if (mc->soc->ops && mc->soc->ops->resume) + return mc->soc->ops->resume(mc); return 0; } static const struct dev_pm_ops tegra_mc_pm_ops = { - .suspend = tegra_mc_suspend, - .resume = tegra_mc_resume, + SET_SYSTEM_SLEEP_PM_OPS(tegra_mc_suspend, tegra_mc_resume) }; static struct platform_driver tegra_mc_driver = { diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 8e77567d1378..9d3fdb609d55 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -45,6 +45,17 @@ static void tegra186_mc_program_sid(struct tegra_mc *mc) } } +static int tegra186_mc_resume(struct tegra_mc *mc) +{ + tegra186_mc_program_sid(mc); + + return 0; +} + +static const struct tegra_mc_ops tegra186_mc_ops = { + .resume = tegra186_mc_resume, +}; + #if defined(CONFIG_ARCH_TEGRA_186_SOC) static const struct tegra_mc_client tegra186_mc_clients[] = { { @@ -701,6 +712,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { static const struct tegra_mc_soc tegra186_mc_soc = { .num_clients = ARRAY_SIZE(tegra186_mc_clients), .clients = tegra186_mc_clients, + .ops = &tegra186_mc_ops, }; #endif @@ -1909,6 +1921,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { static const struct tegra_mc_soc tegra194_mc_soc = { .num_clients = ARRAY_SIZE(tegra194_mc_clients), .clients = tegra194_mc_clients, + .ops = &tegra186_mc_ops, }; #endif @@ -1961,22 +1974,28 @@ static const struct of_device_id tegra186_mc_of_match[] = { }; MODULE_DEVICE_TABLE(of, tegra186_mc_of_match); -static int __maybe_unused tegra186_mc_suspend(struct device *dev) +static int __maybe_unused tegra_mc_suspend(struct device *dev) { + struct tegra_mc *mc = dev_get_drvdata(dev); + + if (mc->soc->ops && mc->soc->ops->suspend) + return mc->soc->ops->suspend(mc); + return 0; } -static int __maybe_unused tegra186_mc_resume(struct device *dev) +static int __maybe_unused tegra_mc_resume(struct device *dev) { struct tegra_mc *mc = dev_get_drvdata(dev); - tegra186_mc_program_sid(mc); + if (mc->soc->ops && mc->soc->ops->resume) + return mc->soc->ops->resume(mc); return 0; } static const struct dev_pm_ops tegra186_mc_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(tegra186_mc_suspend, tegra186_mc_resume) + SET_SYSTEM_SLEEP_PM_OPS(tegra_mc_suspend, tegra_mc_resume) }; static struct platform_driver tegra186_mc_driver = { diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index 3b7b93b96480..a3335ad20f4d 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -687,8 +687,36 @@ static int tegra20_mc_init(struct tegra_mc *mc) return 0; } +static int tegra20_mc_suspend(struct tegra_mc *mc) +{ + int err; + + if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { + err = tegra_gart_suspend(mc->gart); + if (err < 0) + return err; + } + + return 0; +} + +static int tegra20_mc_resume(struct tegra_mc *mc) +{ + int err; + + if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { + err = tegra_gart_resume(mc->gart); + if (err < 0) + return err; + } + + return 0; +} + static const struct tegra_mc_ops tegra20_mc_ops = { .init = tegra20_mc_init, + .suspend = tegra20_mc_suspend, + .resume = tegra20_mc_resume, }; const struct tegra_mc_soc tegra20_mc_soc = { diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 4f88da907a02..7c49f75087c3 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -171,6 +171,8 @@ struct tegra_mc_icc_ops { struct tegra_mc_ops { int (*init)(struct tegra_mc *mc); + int (*suspend)(struct tegra_mc *mc); + int (*resume)(struct tegra_mc *mc); }; struct tegra_mc_soc { -- cgit v1.2.3 From c64738e949940bea2bb426b104b4de0aa42a8f48 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 2 Jun 2021 18:32:55 +0200 Subject: memory: tegra: Make per-SoC setup more generic The current per-SoC setup code runs at a fairly arbitrary point during probe, thereby making it less flexible for other SoC generations. Move the call around slightly (after only the very basic, common setup that applies to all SoC generations has been performed), which will allow it to be used for other implementations. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210602163302.120041-6-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/mc.c | 17 ++++++++--------- drivers/memory/tegra/tegra20.c | 4 ++-- include/soc/tegra/mc.h | 6 +++++- 3 files changed, 15 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index a3b7ba33b7f9..ea2142ba720a 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -784,6 +784,14 @@ static int tegra_mc_probe(struct platform_device *pdev) return PTR_ERR(mc->clk); } + mc->debugfs.root = debugfs_create_dir("mc", NULL); + + if (mc->soc->ops && mc->soc->ops->probe) { + err = mc->soc->ops->probe(mc); + if (err < 0) + return err; + } + #ifdef CONFIG_ARCH_TEGRA_2x_SOC if (mc->soc == &tegra20_mc_soc) { isr = tegra20_mc_irq; @@ -827,15 +835,6 @@ static int tegra_mc_probe(struct platform_device *pdev) return err; } - mc->debugfs.root = debugfs_create_dir("mc", NULL); - - if (mc->soc->ops && mc->soc->ops->init) { - err = mc->soc->ops->init(mc); - if (err < 0) - dev_err(&pdev->dev, "failed to initialize SoC driver: %d\n", - err); - } - err = tegra_mc_reset_setup(mc); if (err < 0) dev_err(&pdev->dev, "failed to register reset controller: %d\n", diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index a3335ad20f4d..2c86c0d70d59 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -679,7 +679,7 @@ static int tegra20_mc_stats_show(struct seq_file *s, void *unused) return 0; } -static int tegra20_mc_init(struct tegra_mc *mc) +static int tegra20_mc_probe(struct tegra_mc *mc) { debugfs_create_devm_seqfile(mc->dev, "stats", mc->debugfs.root, tegra20_mc_stats_show); @@ -714,7 +714,7 @@ static int tegra20_mc_resume(struct tegra_mc *mc) } static const struct tegra_mc_ops tegra20_mc_ops = { - .init = tegra20_mc_init, + .probe = tegra20_mc_probe, .suspend = tegra20_mc_suspend, .resume = tegra20_mc_resume, }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 7c49f75087c3..00d16c356db8 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -170,7 +170,11 @@ struct tegra_mc_icc_ops { }; struct tegra_mc_ops { - int (*init)(struct tegra_mc *mc); + /* + * @probe: Callback to set up SoC-specific bits of the memory controller. This is called + * after basic, common set up that is done by the SoC-agnostic bits. + */ + int (*probe)(struct tegra_mc *mc); int (*suspend)(struct tegra_mc *mc); int (*resume)(struct tegra_mc *mc); }; -- cgit v1.2.3 From 1079a66bc32ff04eaab792152a9ed9c7585b5efc Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 2 Jun 2021 18:32:57 +0200 Subject: memory: tegra: Parameterize interrupt handler Tegra20 requires a slightly different interrupt handler than Tegra30 and later, so parameterize the handler, so that each SoC implementation can provide its own. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210602163302.120041-8-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/mc.c | 136 ++++++++--------------------------------- drivers/memory/tegra/mc.h | 3 + drivers/memory/tegra/tegra20.c | 74 ++++++++++++++++++++++ include/soc/tegra/mc.h | 2 + 4 files changed, 106 insertions(+), 109 deletions(-) (limited to 'include') diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index edb3c4a25365..e6c928633b12 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -492,32 +492,7 @@ int tegra30_mc_probe(struct tegra_mc *mc) return 0; } -const struct tegra_mc_ops tegra30_mc_ops = { - .probe = tegra30_mc_probe, -}; -#endif - -static const char *const status_names[32] = { - [ 1] = "External interrupt", - [ 6] = "EMEM address decode error", - [ 7] = "GART page fault", - [ 8] = "Security violation", - [ 9] = "EMEM arbitration error", - [10] = "Page fault", - [11] = "Invalid APB ASID update", - [12] = "VPR violation", - [13] = "Secure carveout violation", - [16] = "MTS carveout violation", -}; - -static const char *const error_names[8] = { - [2] = "EMEM decode error", - [3] = "TrustZone violation", - [4] = "Carveout violation", - [6] = "SMMU translation error", -}; - -static irqreturn_t tegra_mc_irq(int irq, void *data) +static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) { struct tegra_mc *mc = data; unsigned long status; @@ -529,7 +504,7 @@ static irqreturn_t tegra_mc_irq(int irq, void *data) return IRQ_NONE; for_each_set_bit(bit, &status, 32) { - const char *error = status_names[bit] ?: "unknown"; + const char *error = tegra_mc_status_names[bit] ?: "unknown"; const char *client = "unknown", *desc; const char *direction, *secure; phys_addr_t addr = 0; @@ -569,7 +544,7 @@ static irqreturn_t tegra_mc_irq(int irq, void *data) type = (value & MC_ERR_STATUS_TYPE_MASK) >> MC_ERR_STATUS_TYPE_SHIFT; - desc = error_names[type]; + desc = tegra_mc_error_names[type]; switch (value & MC_ERR_STATUS_TYPE_MASK) { case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: @@ -614,78 +589,31 @@ static irqreturn_t tegra_mc_irq(int irq, void *data) return IRQ_HANDLED; } -static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data) -{ - struct tegra_mc *mc = data; - unsigned long status; - unsigned int bit; - - /* mask all interrupts to avoid flooding */ - status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; - if (!status) - return IRQ_NONE; - - for_each_set_bit(bit, &status, 32) { - const char *direction = "read", *secure = ""; - const char *error = status_names[bit]; - const char *client, *desc; - phys_addr_t addr; - u32 value, reg; - u8 id, type; - - switch (BIT(bit)) { - case MC_INT_DECERR_EMEM: - reg = MC_DECERR_EMEM_OTHERS_STATUS; - value = mc_readl(mc, reg); - - id = value & mc->soc->client_id_mask; - desc = error_names[2]; - - if (value & BIT(31)) - direction = "write"; - break; - - case MC_INT_INVALID_GART_PAGE: - reg = MC_GART_ERROR_REQ; - value = mc_readl(mc, reg); - - id = (value >> 1) & mc->soc->client_id_mask; - desc = error_names[2]; - - if (value & BIT(0)) - direction = "write"; - break; - - case MC_INT_SECURITY_VIOLATION: - reg = MC_SECURITY_VIOLATION_STATUS; - value = mc_readl(mc, reg); - - id = value & mc->soc->client_id_mask; - type = (value & BIT(30)) ? 4 : 3; - desc = error_names[type]; - secure = "secure "; - - if (value & BIT(31)) - direction = "write"; - break; - - default: - continue; - } - - client = mc->soc->clients[id].name; - addr = mc_readl(mc, reg + sizeof(u32)); - - dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n", - client, secure, direction, &addr, error, - desc); - } +const struct tegra_mc_ops tegra30_mc_ops = { + .probe = tegra30_mc_probe, + .handle_irq = tegra30_mc_handle_irq, +}; +#endif - /* clear interrupts */ - mc_writel(mc, status, MC_INTSTATUS); +const char *const tegra_mc_status_names[32] = { + [ 1] = "External interrupt", + [ 6] = "EMEM address decode error", + [ 7] = "GART page fault", + [ 8] = "Security violation", + [ 9] = "EMEM arbitration error", + [10] = "Page fault", + [11] = "Invalid APB ASID update", + [12] = "VPR violation", + [13] = "Secure carveout violation", + [16] = "MTS carveout violation", +}; - return IRQ_HANDLED; -} +const char *const tegra_mc_error_names[8] = { + [2] = "EMEM decode error", + [3] = "TrustZone violation", + [4] = "Carveout violation", + [6] = "SMMU translation error", +}; /* * Memory Controller (MC) has few Memory Clients that are issuing memory @@ -786,7 +714,6 @@ static int tegra_mc_probe(struct platform_device *pdev) { struct resource *res; struct tegra_mc *mc; - void *isr; u64 mask; int err; @@ -823,15 +750,6 @@ static int tegra_mc_probe(struct platform_device *pdev) return err; } -#ifdef CONFIG_ARCH_TEGRA_2x_SOC - if (mc->soc == &tegra20_mc_soc) { - isr = tegra20_mc_irq; - } else -#endif - { - isr = tegra_mc_irq; - } - mc->irq = platform_get_irq(pdev, 0); if (mc->irq < 0) return mc->irq; @@ -840,7 +758,7 @@ static int tegra_mc_probe(struct platform_device *pdev) mc_writel(mc, mc->soc->intmask, MC_INTMASK); - err = devm_request_irq(&pdev->dev, mc->irq, isr, 0, + err = devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, 0, dev_name(&pdev->dev), mc); if (err < 0) { dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 731896169cf3..83c605e42e9a 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -138,6 +138,9 @@ int tegra30_mc_probe(struct tegra_mc *mc); extern const struct tegra_mc_ops tegra30_mc_ops; #endif +extern const char * const tegra_mc_status_names[32]; +extern const char * const tegra_mc_error_names[8]; + /* * These IDs are for internal use of Tegra ICC drivers. The ID numbers are * chosen such that they don't conflict with the device-tree ICC node IDs. diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index 2c86c0d70d59..fcd7738fcb53 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -713,10 +713,84 @@ static int tegra20_mc_resume(struct tegra_mc *mc) return 0; } +static irqreturn_t tegra20_mc_handle_irq(int irq, void *data) +{ + struct tegra_mc *mc = data; + unsigned long status; + unsigned int bit; + + /* mask all interrupts to avoid flooding */ + status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; + if (!status) + return IRQ_NONE; + + for_each_set_bit(bit, &status, 32) { + const char *error = tegra_mc_status_names[bit]; + const char *direction = "read", *secure = ""; + const char *client, *desc; + phys_addr_t addr; + u32 value, reg; + u8 id, type; + + switch (BIT(bit)) { + case MC_INT_DECERR_EMEM: + reg = MC_DECERR_EMEM_OTHERS_STATUS; + value = mc_readl(mc, reg); + + id = value & mc->soc->client_id_mask; + desc = tegra_mc_error_names[2]; + + if (value & BIT(31)) + direction = "write"; + break; + + case MC_INT_INVALID_GART_PAGE: + reg = MC_GART_ERROR_REQ; + value = mc_readl(mc, reg); + + id = (value >> 1) & mc->soc->client_id_mask; + desc = tegra_mc_error_names[2]; + + if (value & BIT(0)) + direction = "write"; + break; + + case MC_INT_SECURITY_VIOLATION: + reg = MC_SECURITY_VIOLATION_STATUS; + value = mc_readl(mc, reg); + + id = value & mc->soc->client_id_mask; + type = (value & BIT(30)) ? 4 : 3; + desc = tegra_mc_error_names[type]; + secure = "secure "; + + if (value & BIT(31)) + direction = "write"; + break; + + default: + continue; + } + + client = mc->soc->clients[id].name; + addr = mc_readl(mc, reg + sizeof(u32)); + + dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n", + client, secure, direction, &addr, error, + desc); + } + + /* clear interrupts */ + mc_writel(mc, status, MC_INTSTATUS); + + return IRQ_HANDLED; +} + static const struct tegra_mc_ops tegra20_mc_ops = { .probe = tegra20_mc_probe, .suspend = tegra20_mc_suspend, .resume = tegra20_mc_resume, + .handle_irq = tegra20_mc_handle_irq, }; const struct tegra_mc_soc tegra20_mc_soc = { diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 00d16c356db8..87668ebab2a1 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -177,6 +178,7 @@ struct tegra_mc_ops { int (*probe)(struct tegra_mc *mc); int (*suspend)(struct tegra_mc *mc); int (*resume)(struct tegra_mc *mc); + irqreturn_t (*handle_irq)(int irq, void *data); }; struct tegra_mc_soc { -- cgit v1.2.3 From 7355c7b9ae0d45923bac088bc1faebd5e9a66164 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 2 Jun 2021 18:33:00 +0200 Subject: memory: tegra: Unify drivers The Tegra210 (and earlier) driver now supports all the functionality that the Tegra186 (and later) driver does, so they can be unified. Note that previously the Tegra186 (and later) driver could be unloaded, even if that was perhaps not very useful. Older chips don't support that yet, but once they do this code can be reenabled. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210602163302.120041-11-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/Makefile | 6 ++- drivers/memory/tegra/mc.c | 8 ++- drivers/memory/tegra/mc.h | 8 +++ drivers/memory/tegra/tegra186.c | 117 +++++++++------------------------------- include/soc/tegra/mc.h | 1 + 5 files changed, 45 insertions(+), 95 deletions(-) (limited to 'include') diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile index 6c1a2ecc6628..1af0fefacdda 100644 --- a/drivers/memory/tegra/Makefile +++ b/drivers/memory/tegra/Makefile @@ -7,6 +7,8 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o +tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o +tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o obj-$(CONFIG_TEGRA_MC) += tegra-mc.o @@ -15,7 +17,7 @@ obj-$(CONFIG_TEGRA30_EMC) += tegra30-emc.o obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o obj-$(CONFIG_TEGRA210_EMC_TABLE) += tegra210-emc-table.o obj-$(CONFIG_TEGRA210_EMC) += tegra210-emc.o -obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o tegra186-emc.o -obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra186-emc.o +obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-emc.o +obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186-emc.o tegra210-emc-y := tegra210-emc-core.o tegra210-emc-cc-r21021.o diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 4aa17bdd6392..11b83de9361c 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -39,7 +39,13 @@ static const struct of_device_id tegra_mc_of_match[] = { #ifdef CONFIG_ARCH_TEGRA_210_SOC { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc }, #endif - { } +#ifdef CONFIG_ARCH_TEGRA_186_SOC + { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, +#endif +#ifdef CONFIG_ARCH_TEGRA_194_SOC + { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc }, +#endif + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, tegra_mc_of_match); diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 83c605e42e9a..24f95e06d18a 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -129,6 +129,14 @@ extern const struct tegra_mc_soc tegra132_mc_soc; extern const struct tegra_mc_soc tegra210_mc_soc; #endif +#ifdef CONFIG_ARCH_TEGRA_186_SOC +extern const struct tegra_mc_soc tegra186_mc_soc; +#endif + +#ifdef CONFIG_ARCH_TEGRA_194_SOC +extern const struct tegra_mc_soc tegra194_mc_soc; +#endif + #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ defined(CONFIG_ARCH_TEGRA_114_SOC) || \ defined(CONFIG_ARCH_TEGRA_124_SOC) || \ diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 9d3fdb609d55..20efbbea587b 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved. */ #include @@ -45,6 +45,24 @@ static void tegra186_mc_program_sid(struct tegra_mc *mc) } } +static int tegra186_mc_probe(struct tegra_mc *mc) +{ + int err; + + err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev); + if (err < 0) + return err; + + tegra186_mc_program_sid(mc); + + return 0; +} + +static void tegra186_mc_remove(struct tegra_mc *mc) +{ + of_platform_depopulate(mc->dev); +} + static int tegra186_mc_resume(struct tegra_mc *mc) { tegra186_mc_program_sid(mc); @@ -53,6 +71,8 @@ static int tegra186_mc_resume(struct tegra_mc *mc) } static const struct tegra_mc_ops tegra186_mc_ops = { + .probe = tegra186_mc_probe, + .remove = tegra186_mc_remove, .resume = tegra186_mc_resume, }; @@ -709,9 +729,10 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }; -static const struct tegra_mc_soc tegra186_mc_soc = { +const struct tegra_mc_soc tegra186_mc_soc = { .num_clients = ARRAY_SIZE(tegra186_mc_clients), .clients = tegra186_mc_clients, + .num_address_bits = 40, .ops = &tegra186_mc_ops, }; #endif @@ -1918,98 +1939,10 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }; -static const struct tegra_mc_soc tegra194_mc_soc = { +const struct tegra_mc_soc tegra194_mc_soc = { .num_clients = ARRAY_SIZE(tegra194_mc_clients), .clients = tegra194_mc_clients, + .num_address_bits = 40, .ops = &tegra186_mc_ops, }; #endif - -static int tegra186_mc_probe(struct platform_device *pdev) -{ - struct resource *res; - struct tegra_mc *mc; - int err; - - mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); - if (!mc) - return -ENOMEM; - - mc->soc = of_device_get_match_data(&pdev->dev); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mc->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(mc->regs)) - return PTR_ERR(mc->regs); - - mc->dev = &pdev->dev; - - err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); - if (err < 0) - return err; - - platform_set_drvdata(pdev, mc); - tegra186_mc_program_sid(mc); - - return 0; -} - -static int tegra186_mc_remove(struct platform_device *pdev) -{ - struct tegra_mc *mc = platform_get_drvdata(pdev); - - of_platform_depopulate(mc->dev); - - return 0; -} - -static const struct of_device_id tegra186_mc_of_match[] = { -#if defined(CONFIG_ARCH_TEGRA_186_SOC) - { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, -#endif -#if defined(CONFIG_ARCH_TEGRA_194_SOC) - { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc }, -#endif - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, tegra186_mc_of_match); - -static int __maybe_unused tegra_mc_suspend(struct device *dev) -{ - struct tegra_mc *mc = dev_get_drvdata(dev); - - if (mc->soc->ops && mc->soc->ops->suspend) - return mc->soc->ops->suspend(mc); - - return 0; -} - -static int __maybe_unused tegra_mc_resume(struct device *dev) -{ - struct tegra_mc *mc = dev_get_drvdata(dev); - - if (mc->soc->ops && mc->soc->ops->resume) - return mc->soc->ops->resume(mc); - - return 0; -} - -static const struct dev_pm_ops tegra186_mc_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(tegra_mc_suspend, tegra_mc_resume) -}; - -static struct platform_driver tegra186_mc_driver = { - .driver = { - .name = "tegra186-mc", - .of_match_table = tegra186_mc_of_match, - .pm = &tegra186_mc_pm_ops, - .suppress_bind_attrs = true, - }, - .probe = tegra186_mc_probe, - .remove = tegra186_mc_remove, -}; -module_platform_driver(tegra186_mc_driver); - -MODULE_AUTHOR("Thierry Reding "); -MODULE_DESCRIPTION("NVIDIA Tegra186 Memory Controller driver"); -MODULE_LICENSE("GPL v2"); diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 87668ebab2a1..1bd5aed81868 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -176,6 +176,7 @@ struct tegra_mc_ops { * after basic, common set up that is done by the SoC-agnostic bits. */ int (*probe)(struct tegra_mc *mc); + void (*remove)(struct tegra_mc *mc); int (*suspend)(struct tegra_mc *mc); int (*resume)(struct tegra_mc *mc); irqreturn_t (*handle_irq)(int irq, void *data); -- cgit v1.2.3 From 393d66fd2cacba3e6aa95d7bb38790bfb7b1cc3a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 3 Jun 2021 18:46:24 +0200 Subject: memory: tegra: Implement SID override programming Instead of programming all SID overrides during early boot, perform the operation on-demand after the SMMU translations have been set up for a device. This reuses data from device tree to match memory clients for a device and programs the SID specified in device tree, which corresponds to the SID used for the SMMU context banks for the device. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210603164632.1000458-2-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/mc.c | 9 ++++++ drivers/memory/tegra/tegra186.c | 72 +++++++++++++++++++++++++++++++++++++++++ include/soc/tegra/mc.h | 3 ++ 3 files changed, 84 insertions(+) (limited to 'include') diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 11b83de9361c..3c5aae7abf35 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -97,6 +97,15 @@ struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev) } EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get); +int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev) +{ + if (mc->soc->ops && mc->soc->ops->probe_device) + return mc->soc->ops->probe_device(mc, dev); + + return 0; +} +EXPORT_SYMBOL_GPL(tegra_mc_probe_device); + static int tegra_mc_block_dma_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 1f87915ccd62..e65eac5764d4 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -15,6 +16,10 @@ #include #endif +#define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0) +#define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16) +#define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8) + static void tegra186_mc_program_sid(struct tegra_mc *mc) { unsigned int i; @@ -66,10 +71,77 @@ static int tegra186_mc_resume(struct tegra_mc *mc) return 0; } +static void tegra186_mc_client_sid_override(struct tegra_mc *mc, + const struct tegra_mc_client *client, + unsigned int sid) +{ + u32 value, old; + + value = readl(mc->regs + client->regs.sid.security); + if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) { + /* + * If the secure firmware has locked this down the override + * for this memory client, there's nothing we can do here. + */ + if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED) + return; + + /* + * Otherwise, try to set the override itself. Typically the + * secure firmware will never have set this configuration. + * Instead, it will either have disabled write access to + * this field, or it will already have set an explicit + * override itself. + */ + WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0); + + value |= MC_SID_STREAMID_SECURITY_OVERRIDE; + writel(value, mc->regs + client->regs.sid.security); + } + + value = readl(mc->regs + client->regs.sid.override); + old = value & MC_SID_STREAMID_OVERRIDE_MASK; + + if (old != sid) { + dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old, + client->name, sid); + writel(sid, mc->regs + client->regs.sid.override); + } +} + +static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) +{ +#if IS_ENABLED(CONFIG_IOMMU_API) + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct of_phandle_args args; + unsigned int i, index = 0; + + while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells", + index, &args)) { + if (args.np == mc->dev->of_node && args.args_count != 0) { + for (i = 0; i < mc->soc->num_clients; i++) { + const struct tegra_mc_client *client = &mc->soc->clients[i]; + + if (client->id == args.args[0]) { + u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK; + + tegra186_mc_client_sid_override(mc, client, sid); + } + } + } + + index++; + } +#endif + + return 0; +} + const struct tegra_mc_ops tegra186_mc_ops = { .probe = tegra186_mc_probe, .remove = tegra186_mc_remove, .resume = tegra186_mc_resume, + .probe_device = tegra186_mc_probe_device, }; #if defined(CONFIG_ARCH_TEGRA_186_SOC) diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 1bd5aed81868..e19c2504a14b 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -180,6 +180,7 @@ struct tegra_mc_ops { int (*suspend)(struct tegra_mc *mc); int (*resume)(struct tegra_mc *mc); irqreturn_t (*handle_irq)(int irq, void *data); + int (*probe_device)(struct tegra_mc *mc, struct device *dev); }; struct tegra_mc_soc { @@ -244,4 +245,6 @@ devm_tegra_memory_controller_get(struct device *dev) } #endif +int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev); + #endif /* __SOC_TEGRA_MC_H__ */ -- cgit v1.2.3 From 48a74b1147f7db4623eaed591cc01eb740b871c0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 9 Jun 2021 13:28:06 +0200 Subject: reset: Add compile-test stubs Add stubs for the reset controller registration functions to allow building reset controller provider drivers with the COMPILE_TEST Kconfig option enabled. Reported-by: Krzysztof Kozlowski Suggested-by: Dmitry Osipenko Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210609112806.3565057-3-thierry.reding@gmail.com Signed-off-by: Philipp Zabel --- include/linux/reset-controller.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'include') diff --git a/include/linux/reset-controller.h b/include/linux/reset-controller.h index ec35814e0bbb..0fa4f60e1186 100644 --- a/include/linux/reset-controller.h +++ b/include/linux/reset-controller.h @@ -79,6 +79,7 @@ struct reset_controller_dev { unsigned int nr_resets; }; +#if IS_ENABLED(CONFIG_RESET_CONTROLLER) int reset_controller_register(struct reset_controller_dev *rcdev); void reset_controller_unregister(struct reset_controller_dev *rcdev); @@ -88,5 +89,26 @@ int devm_reset_controller_register(struct device *dev, void reset_controller_add_lookup(struct reset_control_lookup *lookup, unsigned int num_entries); +#else +static inline int reset_controller_register(struct reset_controller_dev *rcdev) +{ + return 0; +} + +static inline void reset_controller_unregister(struct reset_controller_dev *rcdev) +{ +} + +static inline int devm_reset_controller_register(struct device *dev, + struct reset_controller_dev *rcdev) +{ + return 0; +} + +static inline void reset_controller_add_lookup(struct reset_control_lookup *lookup, + unsigned int num_entries) +{ +} +#endif #endif -- cgit v1.2.3 From af32011f76b759d68a6e3005d450ef7b82e1479a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 31 Jan 2021 02:32:32 +0100 Subject: soc: qcom: rpmpd: Add MDM9607 RPM Power Domains This SoC while being from 8916 era, makes use of the newer-style, floor-level management, instead of the older floor-corner. Acked-by: Rob Herring Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013233.54666-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/power/qcom,rpmpd.yaml | 1 + drivers/soc/qcom/rpmpd.c | 22 ++++++++++++++++++++++ include/dt-bindings/power/qcom-rpmpd.h | 8 ++++++++ 3 files changed, 31 insertions(+) (limited to 'include') diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index c01bb5f0d6ea..4807b560f00d 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - qcom,mdm9607-rpmpd - qcom,msm8916-rpmpd - qcom,msm8939-rpmpd - qcom,msm8976-rpmpd diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 27733b0e7fca..0b532a892d60 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -118,6 +118,27 @@ struct rpmpd_desc { static DEFINE_MUTEX(rpmpd_lock); +/* mdm9607 RPM Power Domains */ +DEFINE_RPMPD_PAIR(mdm9607, vddcx, vddcx_ao, SMPA, LEVEL, 3); +DEFINE_RPMPD_VFL(mdm9607, vddcx_vfl, SMPA, 3); + +DEFINE_RPMPD_PAIR(mdm9607, vddmx, vddmx_ao, LDOA, LEVEL, 12); +DEFINE_RPMPD_VFL(mdm9607, vddmx_vfl, LDOA, 12); +static struct rpmpd *mdm9607_rpmpds[] = { + [MDM9607_VDDCX] = &mdm9607_vddcx, + [MDM9607_VDDCX_AO] = &mdm9607_vddcx_ao, + [MDM9607_VDDCX_VFL] = &mdm9607_vddcx_vfl, + [MDM9607_VDDMX] = &mdm9607_vddmx, + [MDM9607_VDDMX_AO] = &mdm9607_vddmx_ao, + [MDM9607_VDDMX_VFL] = &mdm9607_vddmx_vfl, +}; + +static const struct rpmpd_desc mdm9607_desc = { + .rpmpds = mdm9607_rpmpds, + .num_pds = ARRAY_SIZE(mdm9607_rpmpds), + .max_state = RPM_SMD_LEVEL_TURBO, +}; + /* msm8939 RPM Power Domains */ DEFINE_RPMPD_PAIR(msm8939, vddmd, vddmd_ao, SMPA, CORNER, 1); DEFINE_RPMPD_VFC(msm8939, vddmd_vfc, SMPA, 1); @@ -326,6 +347,7 @@ static const struct rpmpd_desc sdm660_desc = { }; static const struct of_device_id rpmpd_match_table[] = { + { .compatible = "qcom,mdm9607-rpmpd", .data = &mdm9607_desc }, { .compatible = "qcom,msm8916-rpmpd", .data = &msm8916_desc }, { .compatible = "qcom,msm8939-rpmpd", .data = &msm8939_desc }, { .compatible = "qcom,msm8976-rpmpd", .data = &msm8976_desc }, diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 93c134f3724d..8b5708bb9671 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -108,6 +108,14 @@ #define RPMH_REGULATOR_LEVEL_TURBO 384 #define RPMH_REGULATOR_LEVEL_TURBO_L1 416 +/* MDM9607 Power Domains */ +#define MDM9607_VDDCX 0 +#define MDM9607_VDDCX_AO 1 +#define MDM9607_VDDCX_VFL 2 +#define MDM9607_VDDMX 3 +#define MDM9607_VDDMX_AO 4 +#define MDM9607_VDDMX_VFL 5 + /* MSM8939 Power Domains */ #define MSM8939_VDDMDCX 0 #define MSM8939_VDDMDCX_AO 1 -- cgit v1.2.3 From 212c1242a9ac3f9e94a6c6edef2c09bf39650a16 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 24 May 2021 20:07:28 -0500 Subject: dt-bindings: add defines for i.MX8MN power domains The i.MX8M Nano has a similar power domain controller to that of the mini, but it isn't fully compatible, so it needs a separate binding and power domain tables. Add the bindings and tables. Signed-off-by: Adam Ford Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/power/fsl,imx-gpcv2.yaml | 1 + include/dt-bindings/power/imx8mn-power.h | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 include/dt-bindings/power/imx8mn-power.h (limited to 'include') diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml index cac2869af3d0..b6f4c586049d 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml @@ -25,6 +25,7 @@ properties: compatible: enum: - fsl,imx7d-gpc + - fsl,imx8mn-gpc - fsl,imx8mq-gpc - fsl,imx8mm-gpc diff --git a/include/dt-bindings/power/imx8mn-power.h b/include/dt-bindings/power/imx8mn-power.h new file mode 100644 index 000000000000..102ee85a9b62 --- /dev/null +++ b/include/dt-bindings/power/imx8mn-power.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Compass Electronics Group, LLC + */ + +#ifndef __DT_BINDINGS_IMX8MN_POWER_H__ +#define __DT_BINDINGS_IMX8MN_POWER_H__ + +#define IMX8MN_POWER_DOMAIN_HSIOMIX 0 +#define IMX8MN_POWER_DOMAIN_OTG1 1 +#define IMX8MN_POWER_DOMAIN_GPUMIX 2 +#define IMX8MN_POWER_DOMAIN_DISPMIX 3 +#define IMX8MN_POWER_DOMAIN_MIPI 4 + +#endif -- cgit v1.2.3