From a4f7ef6db74197898c48236ad01f8e0eccc1e52b Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 27 Sep 2023 17:25:08 +0100 Subject: spi: rzv2m-csi: Add target mode support The CSI IP found inside the Renesas RZ/V2M SoC supports both SPI host and SPI target roles. When working in target mode, the CSI IP has the option of using its Slave Selection (SS) pin to enable TX and RX operations. Since the SPI target cannot control the clock, when working as target it's best not to stop operations during a transfer, as by doing so the IP will not send or receive data, regardless of clock and active level on pin SS. A side effect from not stopping operations is that the RX FIFO needs to be flushed, word by word, when RX data needs to be discarded. Finally, when in target mode timings are tighter, as missing a deadline translates to errors being thrown, resulting in aborting the transfer. In order to speed things up, we can avoid waiting for the TX FIFO to be empty, we can just wait for the RX FIFO to contain at least the number of words that we expect. Add target support to the currently existing CSI driver. Signed-off-by: Fabrizio Castro Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com Signed-off-by: Mark Brown --- drivers/spi/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/spi/Kconfig') diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2c21d5b96fdc..d4ac184bce95 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -862,7 +862,8 @@ config SPI_RZV2M_CSI tristate "Renesas RZ/V2M CSI controller" depends on ARCH_RENESAS || COMPILE_TEST help - SPI driver for Renesas RZ/V2M Clocked Serial Interface (CSI) + SPI driver for Renesas RZ/V2M Clocked Serial Interface (CSI). + CSI supports both SPI host and SPI target roles. config SPI_QCOM_QSPI tristate "QTI QSPI controller" -- cgit v1.2.3