From 376349232a93645624426db782cafe688054e6d6 Mon Sep 17 00:00:00 2001 From: Eugeniy Paltsev Date: Thu, 14 Sep 2017 17:28:42 +0300 Subject: ARC: reset: introduce AXS10x reset driver ARC AXS10x boards support custom IP-block which allows to control reset signals of selected peripherals. For example DW GMAC, etc... This block is controlled via memory-mapped register (AKA CREG) which represents up-to 32 reset lines. This regiter is self-clearing so we don't need to deassert line after reset. As of today only the following lines are used: - DW GMAC - line 5 Signed-off-by: Eugeniy Paltsev Signed-off-by: Philipp Zabel --- drivers/reset/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/reset/Makefile') diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index d368367110e5..7579dba7b185 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_STI) += sti/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o obj-$(CONFIG_RESET_ATH79) += reset-ath79.o +obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o obj-$(CONFIG_RESET_HSDK_V1) += reset-hsdk-v1.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o -- cgit v1.2.3 From 81c22ad0cc7db056408d6089c9303b2f6e486518 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 11 Aug 2017 12:58:43 +0200 Subject: reset: add reset-simple to unify socfpga, stm32, sunxi, and zx2967 Copy reusable parts from the sunxi driver, to add a driver for simple reset controllers with reset lines that can be controlled by toggling bits in exclusive, contiguous register ranges using read-modify-write cycles under a spinlock. The following patches will replace compatible reset drivers with reset-simple, extending it where necessary. Signed-off-by: Philipp Zabel Reviewed-by: Alexandru Gagniuc Reviewed-by: Chen-Yu Tsai --- drivers/reset/Kconfig | 10 ++++ drivers/reset/Makefile | 1 + drivers/reset/reset-simple.c | 134 +++++++++++++++++++++++++++++++++++++++++++ drivers/reset/reset-simple.h | 41 +++++++++++++ 4 files changed, 186 insertions(+) create mode 100644 drivers/reset/reset-simple.c create mode 100644 drivers/reset/reset-simple.h (limited to 'drivers/reset/Makefile') diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 1c88af294724..392e65187cd5 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -75,6 +75,16 @@ config RESET_PISTACHIO help This enables the reset driver for ImgTec Pistachio SoCs. +config RESET_SIMPLE + bool "Simple Reset Controller Driver" if COMPILE_TEST + default ARCH_SUNXI + help + This enables a simple reset controller driver for reset lines that + that can be asserted and deasserted by toggling bits in a contiguous, + exclusive register space. + + Currently this driver supports Allwinner SoCs. + config RESET_SOCFPGA bool "SoCFPGA Reset Driver" if COMPILE_TEST default ARCH_SOCFPGA || ARCH_STRATIX10 diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index af1c15c330b3..ddd3eeb19356 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o +obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_STM32) += reset-stm32.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c new file mode 100644 index 000000000000..a5119457cec6 --- /dev/null +++ b/drivers/reset/reset-simple.c @@ -0,0 +1,134 @@ +/* + * Simple Reset Controller Driver + * + * Copyright (C) 2017 Pengutronix, Philipp Zabel + * + * Based on Allwinner SoCs Reset Controller driver + * + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "reset-simple.h" + +static inline struct reset_simple_data * +to_reset_simple_data(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct reset_simple_data, rcdev); +} + +static int reset_simple_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct reset_simple_data *data = to_reset_simple_data(rcdev); + int reg_width = sizeof(u32); + int bank = id / (reg_width * BITS_PER_BYTE); + int offset = id % (reg_width * BITS_PER_BYTE); + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&data->lock, flags); + + reg = readl(data->membase + (bank * reg_width)); + if (assert ^ data->active_low) + reg |= BIT(offset); + else + reg &= ~BIT(offset); + writel(reg, data->membase + (bank * reg_width)); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int reset_simple_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return reset_simple_update(rcdev, id, true); +} + +static int reset_simple_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return reset_simple_update(rcdev, id, false); +} + +const struct reset_control_ops reset_simple_ops = { + .assert = reset_simple_assert, + .deassert = reset_simple_deassert, +}; + +/** + * struct reset_simple_devdata - simple reset controller properties + * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits + * are set to assert the reset. + */ +struct reset_simple_devdata { + bool active_low; +}; + +static const struct reset_simple_devdata reset_simple_active_low = { + .active_low = true, +}; + +static const struct of_device_id reset_simple_dt_ids[] = { + { .compatible = "allwinner,sun6i-a31-clock-reset", + .data = &reset_simple_active_low }, + { /* sentinel */ }, +}; + +static int reset_simple_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct reset_simple_devdata *devdata; + struct reset_simple_data *data; + void __iomem *membase; + struct resource *res; + + devdata = of_device_get_match_data(dev); + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + membase = devm_ioremap_resource(dev, res); + if (IS_ERR(membase)) + return PTR_ERR(membase); + + spin_lock_init(&data->lock); + data->membase = membase; + data->rcdev.owner = THIS_MODULE; + data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE; + data->rcdev.ops = &reset_simple_ops; + data->rcdev.of_node = dev->of_node; + + if (devdata) + data->active_low = devdata->active_low; + + return devm_reset_controller_register(dev, &data->rcdev); +} + +static struct platform_driver reset_simple_driver = { + .probe = reset_simple_probe, + .driver = { + .name = "simple-reset", + .of_match_table = reset_simple_dt_ids, + }, +}; +builtin_platform_driver(reset_simple_driver); diff --git a/drivers/reset/reset-simple.h b/drivers/reset/reset-simple.h new file mode 100644 index 000000000000..39af2014b5f1 --- /dev/null +++ b/drivers/reset/reset-simple.h @@ -0,0 +1,41 @@ +/* + * Simple Reset Controller ops + * + * Based on Allwinner SoCs Reset Controller driver + * + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __RESET_SIMPLE_H__ +#define __RESET_SIMPLE_H__ + +#include +#include +#include + +/** + * struct reset_simple_data - driver data for simple reset controllers + * @lock: spinlock to protect registers during read-modify-write cycles + * @membase: memory mapped I/O register range + * @rcdev: reset controller device base structure + * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits + * are set to assert the reset. Note that this says nothing about + * the voltage level of the actual reset line. + */ +struct reset_simple_data { + spinlock_t lock; + void __iomem *membase; + struct reset_controller_dev rcdev; + bool active_low; +}; + +extern const struct reset_control_ops reset_simple_ops; + +#endif /* __RESET_SIMPLE_H__ */ -- cgit v1.2.3 From adf20d7ce7c3591e049910c7760edd9c7da4a246 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 11 Aug 2017 13:02:19 +0200 Subject: reset: socfpga: use the reset-simple driver Add reset line status readback, inverted status support, and socfpga device tree quirks to the simple reset driver, and use it to replace the socfpga driver. Signed-off-by: Philipp Zabel --- drivers/reset/Kconfig | 10 +-- drivers/reset/Makefile | 1 - drivers/reset/reset-simple.c | 51 +++++++++++++- drivers/reset/reset-simple.h | 4 ++ drivers/reset/reset-socfpga.c | 157 ------------------------------------------ 5 files changed, 56 insertions(+), 167 deletions(-) delete mode 100644 drivers/reset/reset-socfpga.c (limited to 'drivers/reset/Makefile') diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index a14c0fe49877..2d6770b210ed 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -77,19 +77,13 @@ config RESET_PISTACHIO config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_SUNXI + default ARCH_SOCFPGA || ARCH_STRATIX10 || ARCH_SUNXI help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, exclusive register space. - Currently this driver supports Allwinner SoCs. - -config RESET_SOCFPGA - bool "SoCFPGA Reset Driver" if COMPILE_TEST - default ARCH_SOCFPGA || ARCH_STRATIX10 - help - This enables the reset controller driver for Altera SoCFPGAs. + Currently this driver supports Altera SoCFPGAs and Allwinner SoCs. config RESET_STM32 bool "STM32 Reset Driver" if COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index ddd3eeb19356..3bf3b4e6a9fd 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -13,7 +13,6 @@ obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o -obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_STM32) += reset-stm32.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c index a5119457cec6..1b320c280ca8 100644 --- a/drivers/reset/reset-simple.c +++ b/drivers/reset/reset-simple.c @@ -68,25 +68,58 @@ static int reset_simple_deassert(struct reset_controller_dev *rcdev, return reset_simple_update(rcdev, id, false); } +static int reset_simple_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct reset_simple_data *data = to_reset_simple_data(rcdev); + int reg_width = sizeof(u32); + int bank = id / (reg_width * BITS_PER_BYTE); + int offset = id % (reg_width * BITS_PER_BYTE); + u32 reg; + + reg = readl(data->membase + (bank * reg_width)); + + return !(reg & BIT(offset)) ^ !data->status_active_low; +} + const struct reset_control_ops reset_simple_ops = { .assert = reset_simple_assert, .deassert = reset_simple_deassert, + .status = reset_simple_status, }; /** * struct reset_simple_devdata - simple reset controller properties + * @reg_offset: offset between base address and first reset register. + * @nr_resets: number of resets. If not set, default to resource size in bits. * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits * are set to assert the reset. + * @status_active_low: if true, bits read back as cleared while the reset is + * asserted. Otherwise, bits read back as set while the + * reset is asserted. */ struct reset_simple_devdata { + u32 reg_offset; + u32 nr_resets; bool active_low; + bool status_active_low; +}; + +#define SOCFPGA_NR_BANKS 8 + +static const struct reset_simple_devdata reset_simple_socfpga = { + .reg_offset = 0x10, + .nr_resets = SOCFPGA_NR_BANKS * 32, + .status_active_low = true, }; static const struct reset_simple_devdata reset_simple_active_low = { .active_low = true, + .status_active_low = true, }; static const struct of_device_id reset_simple_dt_ids[] = { + { .compatible = "altr,rst-mgr", .data = &reset_simple_socfpga }, { .compatible = "allwinner,sun6i-a31-clock-reset", .data = &reset_simple_active_low }, { /* sentinel */ }, @@ -99,6 +132,7 @@ static int reset_simple_probe(struct platform_device *pdev) struct reset_simple_data *data; void __iomem *membase; struct resource *res; + u32 reg_offset = 0; devdata = of_device_get_match_data(dev); @@ -118,8 +152,23 @@ static int reset_simple_probe(struct platform_device *pdev) data->rcdev.ops = &reset_simple_ops; data->rcdev.of_node = dev->of_node; - if (devdata) + if (devdata) { + reg_offset = devdata->reg_offset; + if (devdata->nr_resets) + data->rcdev.nr_resets = devdata->nr_resets; data->active_low = devdata->active_low; + data->status_active_low = devdata->status_active_low; + } + + if (of_device_is_compatible(dev->of_node, "altr,rst-mgr") && + of_property_read_u32(dev->of_node, "altr,modrst-offset", + ®_offset)) { + dev_warn(dev, + "missing altr,modrst-offset property, assuming 0x%x!\n", + reg_offset); + } + + data->membase += reg_offset; return devm_reset_controller_register(dev, &data->rcdev); } diff --git a/drivers/reset/reset-simple.h b/drivers/reset/reset-simple.h index 39af2014b5f1..8a496022baef 100644 --- a/drivers/reset/reset-simple.h +++ b/drivers/reset/reset-simple.h @@ -28,12 +28,16 @@ * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits * are set to assert the reset. Note that this says nothing about * the voltage level of the actual reset line. + * @status_active_low: if true, bits read back as cleared while the reset is + * asserted. Otherwise, bits read back as set while the + * reset is asserted. */ struct reset_simple_data { spinlock_t lock; void __iomem *membase; struct reset_controller_dev rcdev; bool active_low; + bool status_active_low; }; extern const struct reset_control_ops reset_simple_ops; diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c deleted file mode 100644 index 3907bbc9c6cf..000000000000 --- a/drivers/reset/reset-socfpga.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Socfpga Reset Controller Driver - * - * Copyright 2014 Steffen Trumtrar - * - * based on - * Allwinner SoCs Reset Controller driver - * - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define BANK_INCREMENT 4 -#define NR_BANKS 8 - -struct socfpga_reset_data { - spinlock_t lock; - void __iomem *membase; - struct reset_controller_dev rcdev; -}; - -static int socfpga_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct socfpga_reset_data *data = container_of(rcdev, - struct socfpga_reset_data, - rcdev); - int reg_width = sizeof(u32); - int bank = id / (reg_width * BITS_PER_BYTE); - int offset = id % (reg_width * BITS_PER_BYTE); - unsigned long flags; - u32 reg; - - spin_lock_irqsave(&data->lock, flags); - - reg = readl(data->membase + (bank * BANK_INCREMENT)); - writel(reg | BIT(offset), data->membase + (bank * BANK_INCREMENT)); - spin_unlock_irqrestore(&data->lock, flags); - - return 0; -} - -static int socfpga_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct socfpga_reset_data *data = container_of(rcdev, - struct socfpga_reset_data, - rcdev); - - int reg_width = sizeof(u32); - int bank = id / (reg_width * BITS_PER_BYTE); - int offset = id % (reg_width * BITS_PER_BYTE); - unsigned long flags; - u32 reg; - - spin_lock_irqsave(&data->lock, flags); - - reg = readl(data->membase + (bank * BANK_INCREMENT)); - writel(reg & ~BIT(offset), data->membase + (bank * BANK_INCREMENT)); - - spin_unlock_irqrestore(&data->lock, flags); - - return 0; -} - -static int socfpga_reset_status(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct socfpga_reset_data *data = container_of(rcdev, - struct socfpga_reset_data, rcdev); - int reg_width = sizeof(u32); - int bank = id / (reg_width * BITS_PER_BYTE); - int offset = id % (reg_width * BITS_PER_BYTE); - u32 reg; - - reg = readl(data->membase + (bank * BANK_INCREMENT)); - - return !(reg & BIT(offset)); -} - -static const struct reset_control_ops socfpga_reset_ops = { - .assert = socfpga_reset_assert, - .deassert = socfpga_reset_deassert, - .status = socfpga_reset_status, -}; - -static int socfpga_reset_probe(struct platform_device *pdev) -{ - struct socfpga_reset_data *data; - struct resource *res; - struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; - u32 modrst_offset; - - /* - * The binding was mainlined without the required property. - * Do not continue, when we encounter an old DT. - */ - if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) { - dev_err(&pdev->dev, "%pOF missing #reset-cells property\n", - pdev->dev.of_node); - return -EINVAL; - } - - data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - data->membase = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(data->membase)) - return PTR_ERR(data->membase); - - if (of_property_read_u32(np, "altr,modrst-offset", &modrst_offset)) { - dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n"); - modrst_offset = 0x10; - } - data->membase += modrst_offset; - - spin_lock_init(&data->lock); - - data->rcdev.owner = THIS_MODULE; - data->rcdev.nr_resets = NR_BANKS * (sizeof(u32) * BITS_PER_BYTE); - data->rcdev.ops = &socfpga_reset_ops; - data->rcdev.of_node = pdev->dev.of_node; - - return devm_reset_controller_register(dev, &data->rcdev); -} - -static const struct of_device_id socfpga_reset_dt_ids[] = { - { .compatible = "altr,rst-mgr", }, - { /* sentinel */ }, -}; - -static struct platform_driver socfpga_reset_driver = { - .probe = socfpga_reset_probe, - .driver = { - .name = "socfpga-reset", - .of_match_table = socfpga_reset_dt_ids, - }, -}; -builtin_platform_driver(socfpga_reset_driver); -- cgit v1.2.3 From 0af8a137361330af644ae9a3475b328a1dfb7945 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 11 Aug 2017 13:02:47 +0200 Subject: reset: stm32: use the reset-simple driver The reset-simple driver can be used without changes. Signed-off-by: Philipp Zabel Acked-by: Gabriel Fernandez --- drivers/reset/Kconfig | 11 ++--- drivers/reset/Makefile | 1 - drivers/reset/reset-simple.c | 1 + drivers/reset/reset-stm32.c | 108 ------------------------------------------- 4 files changed, 4 insertions(+), 117 deletions(-) delete mode 100644 drivers/reset/reset-stm32.c (limited to 'drivers/reset/Makefile') diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 2d6770b210ed..9bdb4fe1b03e 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -77,19 +77,14 @@ config RESET_PISTACHIO config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_SOCFPGA || ARCH_STRATIX10 || ARCH_SUNXI + default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, exclusive register space. - Currently this driver supports Altera SoCFPGAs and Allwinner SoCs. - -config RESET_STM32 - bool "STM32 Reset Driver" if COMPILE_TEST - default ARCH_STM32 - help - This enables the RCC reset controller driver for STM32 MCUs. + Currently this driver supports Altera SoCFPGAs, the RCC reset + controller in STM32 MCUs, and Allwinner SoCs. config RESET_SUNXI bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 3bf3b4e6a9fd..98dd1eccc820 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -13,7 +13,6 @@ obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o -obj-$(CONFIG_RESET_STM32) += reset-stm32.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c index 1b320c280ca8..79c6ae3b743f 100644 --- a/drivers/reset/reset-simple.c +++ b/drivers/reset/reset-simple.c @@ -120,6 +120,7 @@ static const struct reset_simple_devdata reset_simple_active_low = { static const struct of_device_id reset_simple_dt_ids[] = { { .compatible = "altr,rst-mgr", .data = &reset_simple_socfpga }, + { .compatible = "st,stm32-rcc", }, { .compatible = "allwinner,sun6i-a31-clock-reset", .data = &reset_simple_active_low }, { /* sentinel */ }, diff --git a/drivers/reset/reset-stm32.c b/drivers/reset/reset-stm32.c deleted file mode 100644 index 3a7c8527e66a..000000000000 --- a/drivers/reset/reset-stm32.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (C) Maxime Coquelin 2015 - * Author: Maxime Coquelin - * License terms: GNU General Public License (GPL), version 2 - * - * Heavily based on sunxi driver from Maxime Ripard. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct stm32_reset_data { - spinlock_t lock; - void __iomem *membase; - struct reset_controller_dev rcdev; -}; - -static int stm32_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct stm32_reset_data *data = container_of(rcdev, - struct stm32_reset_data, - rcdev); - int bank = id / BITS_PER_LONG; - int offset = id % BITS_PER_LONG; - unsigned long flags; - u32 reg; - - spin_lock_irqsave(&data->lock, flags); - - reg = readl(data->membase + (bank * 4)); - writel(reg | BIT(offset), data->membase + (bank * 4)); - - spin_unlock_irqrestore(&data->lock, flags); - - return 0; -} - -static int stm32_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct stm32_reset_data *data = container_of(rcdev, - struct stm32_reset_data, - rcdev); - int bank = id / BITS_PER_LONG; - int offset = id % BITS_PER_LONG; - unsigned long flags; - u32 reg; - - spin_lock_irqsave(&data->lock, flags); - - reg = readl(data->membase + (bank * 4)); - writel(reg & ~BIT(offset), data->membase + (bank * 4)); - - spin_unlock_irqrestore(&data->lock, flags); - - return 0; -} - -static const struct reset_control_ops stm32_reset_ops = { - .assert = stm32_reset_assert, - .deassert = stm32_reset_deassert, -}; - -static const struct of_device_id stm32_reset_dt_ids[] = { - { .compatible = "st,stm32-rcc", }, - { /* sentinel */ }, -}; - -static int stm32_reset_probe(struct platform_device *pdev) -{ - struct stm32_reset_data *data; - struct resource *res; - - data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - data->membase = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(data->membase)) - return PTR_ERR(data->membase); - - spin_lock_init(&data->lock); - - data->rcdev.owner = THIS_MODULE; - data->rcdev.nr_resets = resource_size(res) * 8; - data->rcdev.ops = &stm32_reset_ops; - data->rcdev.of_node = pdev->dev.of_node; - - return devm_reset_controller_register(&pdev->dev, &data->rcdev); -} - -static struct platform_driver stm32_reset_driver = { - .probe = stm32_reset_probe, - .driver = { - .name = "stm32-rcc-reset", - .of_match_table = stm32_reset_dt_ids, - }, -}; -builtin_platform_driver(stm32_reset_driver); -- cgit v1.2.3 From f0e0ada67dfd8342fd411da6e3bff10ff9bcc97b Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 11 Aug 2017 13:03:05 +0200 Subject: reset: zx2967: use the reset-simple driver The reset-simple driver can be used without changes. Signed-off-by: Philipp Zabel Reviewed-by: Alexandru Gagniuc --- MAINTAINERS | 1 - drivers/reset/Kconfig | 10 +---- drivers/reset/Makefile | 1 - drivers/reset/reset-simple.c | 2 + drivers/reset/reset-zx2967.c | 99 -------------------------------------------- 5 files changed, 4 insertions(+), 109 deletions(-) delete mode 100644 drivers/reset/reset-zx2967.c (limited to 'drivers/reset/Makefile') diff --git a/MAINTAINERS b/MAINTAINERS index 3b9887b3644e..d48d8a238fae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2124,7 +2124,6 @@ F: drivers/gpio/gpio-zx.c F: drivers/i2c/busses/i2c-zx2967.c F: drivers/mmc/host/dw_mmc-zx.* F: drivers/pinctrl/zte/ -F: drivers/reset/reset-zx2967.c F: drivers/soc/zte/ F: drivers/thermal/zx2967_thermal.c F: drivers/watchdog/zx2967_wdt.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 9bdb4fe1b03e..de0090c911cd 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -77,14 +77,14 @@ config RESET_PISTACHIO config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI + default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, exclusive register space. Currently this driver supports Altera SoCFPGAs, the RCC reset - controller in STM32 MCUs, and Allwinner SoCs. + controller in STM32 MCUs, Allwinner SoCs, and ZTE's zx2967 family. config RESET_SUNXI bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI @@ -121,12 +121,6 @@ config RESET_UNIPHIER Say Y if you want to control reset signals provided by System Control block, Media I/O block, Peripheral Block. -config RESET_ZX2967 - bool "ZTE ZX2967 Reset Driver" - depends on ARCH_ZX || COMPILE_TEST - help - This enables the reset controller driver for ZTE's zx2967 family. - config RESET_ZYNQ bool "ZYNQ Reset Driver" if COMPILE_TEST default ARCH_ZYNQ diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 98dd1eccc820..48b64d63b75a 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -17,6 +17,5 @@ obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o -obj-$(CONFIG_RESET_ZX2967) += reset-zx2967.o obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c index 79c6ae3b743f..2d4f362ef025 100644 --- a/drivers/reset/reset-simple.c +++ b/drivers/reset/reset-simple.c @@ -123,6 +123,8 @@ static const struct of_device_id reset_simple_dt_ids[] = { { .compatible = "st,stm32-rcc", }, { .compatible = "allwinner,sun6i-a31-clock-reset", .data = &reset_simple_active_low }, + { .compatible = "zte,zx296718-reset", + .data = &reset_simple_active_low }, { /* sentinel */ }, }; diff --git a/drivers/reset/reset-zx2967.c b/drivers/reset/reset-zx2967.c deleted file mode 100644 index 4f319f7753d4..000000000000 --- a/drivers/reset/reset-zx2967.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * ZTE's zx2967 family reset controller driver - * - * Copyright (C) 2017 ZTE Ltd. - * - * Author: Baoyou Xie - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#include -#include -#include - -struct zx2967_reset { - void __iomem *reg_base; - spinlock_t lock; - struct reset_controller_dev rcdev; -}; - -static int zx2967_reset_act(struct reset_controller_dev *rcdev, - unsigned long id, bool assert) -{ - struct zx2967_reset *reset = NULL; - int bank = id / 32; - int offset = id % 32; - u32 reg; - unsigned long flags; - - reset = container_of(rcdev, struct zx2967_reset, rcdev); - - spin_lock_irqsave(&reset->lock, flags); - - reg = readl_relaxed(reset->reg_base + (bank * 4)); - if (assert) - reg &= ~BIT(offset); - else - reg |= BIT(offset); - writel_relaxed(reg, reset->reg_base + (bank * 4)); - - spin_unlock_irqrestore(&reset->lock, flags); - - return 0; -} - -static int zx2967_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - return zx2967_reset_act(rcdev, id, true); -} - -static int zx2967_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - return zx2967_reset_act(rcdev, id, false); -} - -static const struct reset_control_ops zx2967_reset_ops = { - .assert = zx2967_reset_assert, - .deassert = zx2967_reset_deassert, -}; - -static int zx2967_reset_probe(struct platform_device *pdev) -{ - struct zx2967_reset *reset; - struct resource *res; - - reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); - if (!reset) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - reset->reg_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(reset->reg_base)) - return PTR_ERR(reset->reg_base); - - spin_lock_init(&reset->lock); - - reset->rcdev.owner = THIS_MODULE; - reset->rcdev.nr_resets = resource_size(res) * 8; - reset->rcdev.ops = &zx2967_reset_ops; - reset->rcdev.of_node = pdev->dev.of_node; - - return devm_reset_controller_register(&pdev->dev, &reset->rcdev); -} - -static const struct of_device_id zx2967_reset_dt_ids[] = { - { .compatible = "zte,zx296718-reset", }, - {}, -}; - -static struct platform_driver zx2967_reset_driver = { - .probe = zx2967_reset_probe, - .driver = { - .name = "zx2967-reset", - .of_match_table = zx2967_reset_dt_ids, - }, -}; -builtin_platform_driver(zx2967_reset_driver); -- cgit v1.2.3