From 07dd08c39eb4b645a0e2f2440a54326b49944705 Mon Sep 17 00:00:00 2001 From: Paul Barker Date: Tue, 25 Jun 2024 21:03:08 +0100 Subject: pinctrl: renesas: rzg2l: Clarify OEN read/write support We currently support OEN read/write for the RZ/G3S SoC but not the RZ/G2L SoC family (consisting of RZ/G2L, RZ/G2LC, RZ/G2UL, RZ/V2L & RZ/Five). The appropriate functions are renamed to clarify this and to match the callback names. We should also only set the oen_read and oen_write function pointers for the devices which support these operations. This requires us to check that these function pointers are valid before calling them. Signed-off-by: Paul Barker Acked-by: Linus Walleij Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240625200316.4282-2-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index a04a4ce4a80e..cffc8c010682 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -999,7 +999,7 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, return false; } -static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin) +static bool rzg3s_oen_is_supported(u32 caps, u8 pin, u8 max_pin) { if (!(caps & PIN_CFG_OEN)) return false; @@ -1010,7 +1010,7 @@ static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin) return true; } -static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port) +static u8 rzg3s_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port) { if (pin) pin *= 2; @@ -1021,31 +1021,31 @@ static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port) return pin; } -static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin) +static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin) { u8 max_port = pctrl->data->hwcfg->oen_max_port; u8 max_pin = pctrl->data->hwcfg->oen_max_pin; u8 bit; - if (!rzg2l_oen_is_supported(caps, pin, max_pin)) + if (!rzg3s_oen_is_supported(caps, pin, max_pin)) return 0; - bit = rzg2l_pin_to_oen_bit(offset, pin, max_port); + bit = rzg3s_pin_to_oen_bit(offset, pin, max_port); return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); } -static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen) +static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen) { u8 max_port = pctrl->data->hwcfg->oen_max_port; u8 max_pin = pctrl->data->hwcfg->oen_max_pin; unsigned long flags; u8 val, bit; - if (!rzg2l_oen_is_supported(caps, pin, max_pin)) + if (!rzg3s_oen_is_supported(caps, pin, max_pin)) return -EINVAL; - bit = rzg2l_pin_to_oen_bit(offset, pin, max_port); + bit = rzg3s_pin_to_oen_bit(offset, pin, max_port); spin_lock_irqsave(&pctrl->lock, flags); val = readb(pctrl->base + ETH_MODE); @@ -1220,6 +1220,8 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_OUTPUT_ENABLE: + if (!pctrl->data->oen_read) + return -EOPNOTSUPP; arg = pctrl->data->oen_read(pctrl, cfg, _pin, bit); if (!arg) return -EINVAL; @@ -1359,6 +1361,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, case PIN_CONFIG_OUTPUT_ENABLE: arg = pinconf_to_config_argument(_configs[i]); + if (!pctrl->data->oen_write) + return -EOPNOTSUPP; ret = pctrl->data->oen_write(pctrl, cfg, _pin, bit, !!arg); if (ret) return ret; @@ -3070,8 +3074,6 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { #endif .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb = &rzg2l_pmc_writeb, - .oen_read = &rzg2l_read_oen, - .oen_write = &rzg2l_write_oen, .hw_to_bias_param = &rzg2l_hw_to_bias_param, .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; @@ -3087,8 +3089,6 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .hwcfg = &rzg2l_hwcfg, .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb = &rzg2l_pmc_writeb, - .oen_read = &rzg2l_read_oen, - .oen_write = &rzg2l_write_oen, .hw_to_bias_param = &rzg2l_hw_to_bias_param, .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; @@ -3103,8 +3103,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { .hwcfg = &rzg3s_hwcfg, .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb = &rzg2l_pmc_writeb, - .oen_read = &rzg2l_read_oen, - .oen_write = &rzg2l_write_oen, + .oen_read = &rzg3s_oen_read, + .oen_write = &rzg3s_oen_write, .hw_to_bias_param = &rzg2l_hw_to_bias_param, .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; -- cgit v1.2.3 From a9024a323af2235a6d11cbbde924c6dde8bd355b Mon Sep 17 00:00:00 2001 From: Paul Barker Date: Tue, 25 Jun 2024 21:03:09 +0100 Subject: pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions The variable naming in the various OEN functions has been confusing. We were passing the _pin & bit variables from rzg2l_pinctrl_pinconf_get() and rzg2l_pinctrl_pinconf_set() as the offset & pin argument to the oen_read() and oen_write() functions. This doesn't make sense, the first of these isn't actually an offset and the second is not needed for RZ/V2H but leads to confusion with the bit variable used within these functions. To tidy this up, instead pass the _pin variable directly to the oen_read() and oen_write() functions with consistent naming. Then rzg3s_read_oen() and rzg3s_write_oen() can use macros to get the port and pin numbers it needs. Instead of passing the pin capabilities into oen_read() and oen_write(), check that the pin supports OEN before calling these functions. Also, merge rzg3s_oen_is_supported() into rzg3s_pin_to_oen_bit() to give a single translation function which returns an error if the pin doesn't support OEN. While we're here, remove an unnecessary branch and clarify the variable naming. Lastly, check that we are not dealing with a dedicated pin before calling RZG2L_PIN_ID_TO_{PORT,PIN}(). Signed-off-by: Paul Barker Acked-by: Linus Walleij Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240625200316.4282-3-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 85 ++++++++++++++------------------- 1 file changed, 36 insertions(+), 49 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index cffc8c010682..31d9f0027388 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -294,8 +294,8 @@ struct rzg2l_pinctrl_data { #endif void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock); void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset); - u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin); - int (*oen_write)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen); + u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); + int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen); int (*hw_to_bias_param)(unsigned int val); int (*bias_param_to_hw)(enum pin_config_param param); }; @@ -999,53 +999,46 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, return false; } -static bool rzg3s_oen_is_supported(u32 caps, u8 pin, u8 max_pin) +static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { - if (!(caps & PIN_CFG_OEN)) - return false; - - if (pin > max_pin) - return false; + u64 *pin_data = pctrl->desc.pins[_pin].drv_data; + u8 port, pin, bit; - return true; -} + if (*pin_data & RZG2L_SINGLE_PIN) + return -EINVAL; -static u8 rzg3s_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port) -{ - if (pin) - pin *= 2; + port = RZG2L_PIN_ID_TO_PORT(_pin); + pin = RZG2L_PIN_ID_TO_PIN(_pin); + if (pin > pctrl->data->hwcfg->oen_max_pin) + return -EINVAL; - if (offset / RZG2L_PINS_PER_PORT == max_port) - pin += 1; + bit = pin * 2; + if (port == pctrl->data->hwcfg->oen_max_port) + bit += 1; - return pin; + return bit; } -static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin) +static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { - u8 max_port = pctrl->data->hwcfg->oen_max_port; - u8 max_pin = pctrl->data->hwcfg->oen_max_pin; - u8 bit; - - if (!rzg3s_oen_is_supported(caps, pin, max_pin)) - return 0; + int bit; - bit = rzg3s_pin_to_oen_bit(offset, pin, max_port); + bit = rzg3s_pin_to_oen_bit(pctrl, _pin); + if (bit < 0) + return bit; return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); } -static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen) +static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) { - u8 max_port = pctrl->data->hwcfg->oen_max_port; - u8 max_pin = pctrl->data->hwcfg->oen_max_pin; unsigned long flags; - u8 val, bit; - - if (!rzg3s_oen_is_supported(caps, pin, max_pin)) - return -EINVAL; + int bit; + u8 val; - bit = rzg3s_pin_to_oen_bit(offset, pin, max_port); + bit = rzg3s_pin_to_oen_bit(pctrl, _pin); + if (bit < 0) + return bit; spin_lock_irqsave(&pctrl->lock, flags); val = readb(pctrl->base + ETH_MODE); @@ -1124,12 +1117,12 @@ static int rzv2h_bias_param_to_hw(enum pin_config_param param) return -EINVAL; } -static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, u32 offset) +static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK", "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKN", "XSPI0_CKP" }; - const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin]; unsigned int i; for (i = 0; i < ARRAY_SIZE(pin_names); i++) { @@ -1141,19 +1134,16 @@ static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, u32 offset) return 0; } -static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin) +static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { u8 bit; - if (!(caps & PIN_CFG_OEN)) - return 0; - - bit = rzv2h_pin_to_oen_bit(pctrl, offset); + bit = rzv2h_pin_to_oen_bit(pctrl, _pin); return !(readb(pctrl->base + PFC_OEN) & BIT(bit)); } -static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen) +static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) { const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs = &hwcfg->regs; @@ -1161,10 +1151,7 @@ static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 u8 val, bit; u8 pwpr; - if (!(caps & PIN_CFG_OEN)) - return -EINVAL; - - bit = rzv2h_pin_to_oen_bit(pctrl, offset); + bit = rzv2h_pin_to_oen_bit(pctrl, _pin); spin_lock_irqsave(&pctrl->lock, flags); val = readb(pctrl->base + PFC_OEN); if (oen) @@ -1220,9 +1207,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_OUTPUT_ENABLE: - if (!pctrl->data->oen_read) + if (!pctrl->data->oen_read || !(cfg & PIN_CFG_OEN)) return -EOPNOTSUPP; - arg = pctrl->data->oen_read(pctrl, cfg, _pin, bit); + arg = pctrl->data->oen_read(pctrl, _pin); if (!arg) return -EINVAL; break; @@ -1361,9 +1348,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, case PIN_CONFIG_OUTPUT_ENABLE: arg = pinconf_to_config_argument(_configs[i]); - if (!pctrl->data->oen_write) + if (!pctrl->data->oen_write || !(cfg & PIN_CFG_OEN)) return -EOPNOTSUPP; - ret = pctrl->data->oen_write(pctrl, cfg, _pin, bit, !!arg); + ret = pctrl->data->oen_write(pctrl, _pin, !!arg); if (ret) return ret; break; -- cgit v1.2.3 From 2453e858e945e5e2fa8da9fde8584995e7dd17d1 Mon Sep 17 00:00:00 2001 From: Paul Barker Date: Tue, 25 Jun 2024 21:03:10 +0100 Subject: pinctrl: renesas: rzg2l: Support output enable on RZ/G2L On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK signal is selectable to support an Ethernet PHY operating in either MII or RGMII mode. By default, the signal is configured as an input and MII mode is supported. The ETH_MODE register can be modified to configure this signal as an output to support RGMII mode. As this signal is by default an input, and can optionally be switched to an output, it maps neatly onto an `output-enable` property in the device tree. Signed-off-by: Paul Barker Acked-by: Linus Walleij Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240625200316.4282-4-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 67 +++++++++++++++++++++++++++++++-- 1 file changed, 63 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 31d9f0027388..632180570b70 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -999,6 +999,60 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, return false; } +static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) +{ + u64 *pin_data = pctrl->desc.pins[_pin].drv_data; + u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data); + u8 pin = RZG2L_PIN_ID_TO_PIN(_pin); + + if (pin > pctrl->data->hwcfg->oen_max_pin) + return -EINVAL; + + /* + * We can determine which Ethernet interface we're dealing with from + * the caps. + */ + if (caps & PIN_CFG_IO_VMC_ETH0) + return 0; + if (caps & PIN_CFG_IO_VMC_ETH1) + return 1; + + return -EINVAL; +} + +static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) +{ + int bit; + + bit = rzg2l_pin_to_oen_bit(pctrl, _pin); + if (bit < 0) + return 0; + + return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); +} + +static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) +{ + unsigned long flags; + int bit; + u8 val; + + bit = rzg2l_pin_to_oen_bit(pctrl, _pin); + if (bit < 0) + return bit; + + spin_lock_irqsave(&pctrl->lock, flags); + val = readb(pctrl->base + ETH_MODE); + if (oen) + val &= ~BIT(bit); + else + val |= BIT(bit); + writeb(val, pctrl->base + ETH_MODE); + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { u64 *pin_data = pctrl->desc.pins[_pin].drv_data; @@ -1775,7 +1829,7 @@ static const u64 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), @@ -1784,7 +1838,7 @@ static const u64 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), @@ -1808,13 +1862,13 @@ static const u64 r9a07g044_gpio_configs[] = { static const u64 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), @@ -3007,6 +3061,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000, }, .iolh_groupb_oi = { 100, 66, 50, 33, }, + .oen_max_pin = 0, }; static const struct rzg2l_hwcfg rzg3s_hwcfg = { @@ -3061,6 +3116,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { #endif .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb = &rzg2l_pmc_writeb, + .oen_read = &rzg2l_read_oen, + .oen_write = &rzg2l_write_oen, .hw_to_bias_param = &rzg2l_hw_to_bias_param, .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; @@ -3076,6 +3133,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .hwcfg = &rzg2l_hwcfg, .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb = &rzg2l_pmc_writeb, + .oen_read = &rzg2l_read_oen, + .oen_write = &rzg2l_write_oen, .hw_to_bias_param = &rzg2l_hw_to_bias_param, .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; -- cgit v1.2.3