From 103afc8e9e8c4eff96052b311d19f7c32b653ebb Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Mar 2020 13:27:36 +0100 Subject: pinctrl: tegra: Renumber the GG.0 and GG.1 pins There is no need to define these at a specific offset since they are the only pins defined for this SoC generation. Begin numbering them at 0. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20200319122737.3063291-9-thierry.reding@gmail.com Tested-by: Vidya Sagar Signed-off-by: Linus Walleij --- drivers/pinctrl/tegra/pinctrl-tegra194.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'drivers/pinctrl/tegra/pinctrl-tegra194.c') diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c index 61fc7e680788..61afe5fe9dec 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra194.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c @@ -24,17 +24,14 @@ /* Define unique ID for each pins */ enum pin_id { - TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0 = 256, - TEGRA_PIN_PEX_L5_RST_N_PGG1 = 257, - TEGRA_PIN_NUM_GPIOS = 258, + TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, + TEGRA_PIN_PEX_L5_RST_N_PGG1, }; /* Table for pin descriptor */ static const struct pinctrl_pin_desc tegra194_pins[] = { - PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, - "TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0"), - PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, - "TEGRA_PIN_PEX_L5_RST_N_PGG1"), + PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"), + PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"), }; static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = { -- cgit v1.2.3