From 29081008047892acb39099c39d39f84c2e7fb028 Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Fri, 23 Jul 2021 10:42:32 -0700 Subject: drm/i915/dg2: Add MPLLB programming for SNPS PHY DG2's SNPS PHYs incorporate a dedicated port PLL called MPLLB which takes the place of the shared DPLLs we've used on past platforms. Let's add the MPLLB programming sequences; they'll be plugged into the rest of the code in future patches. Bspec: 54032 Bspec: 53881 Cc: Lucas De Marchi Signed-off-by: Matt Roper Signed-off-by: Vandita Kulkarni Signed-off-by: Jani Nikula Signed-off-by: Nidhi Gupta Reviewed-by: Matt Atwood Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-24-matthew.d.roper@intel.com --- drivers/gpu/drm/i915/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/i915/Makefile') diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 4f22cac1c49b..cab41af9d52d 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -265,6 +265,7 @@ i915-y += \ display/intel_pps.o \ display/intel_qp_tables.o \ display/intel_sdvo.o \ + display/intel_snps_phy.o \ display/intel_tv.o \ display/intel_vdsc.o \ display/intel_vrr.o \ -- cgit v1.2.3