From 47147d56f92ee3f575e4b457413e0f2587b40e17 Mon Sep 17 00:00:00 2001 From: Alfonso Rodriguez Date: Mon, 5 Jun 2023 17:24:33 +0530 Subject: fpga: zynq-fpga: Ensure proper xCAP interface switch The Zynq platform has PCAP, ICAP and JTAG interfaces for configuring programmable logic (PL). The existing driver implementation uses the PCAP interface to configure the PL. Before switching the PL configuration interface from PCAP to ICAP make sure that all outstanding Transactions relevant to the PL configuration should be completed by the PCAP interface otherwise it may lead to PL configuration issues. This patch provides a required fix to ensure that all existing PL transactions are completed before switching from PCAP to ICAP. For detailed information relevant to PL configuration interfaces refer Zynq 7000 TRM (section 6.5.1). Link: https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM Signed-off-by: Alfonso Rodriguez Signed-off-by: Nava kishore Manne Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20230605115433.186087-1-nava.kishore.manne@amd.com Signed-off-by: Xu Yilun --- drivers/fpga/zynq-fpga.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/fpga') diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index ae0da361e6c6..f8214cae9b6e 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -493,15 +493,15 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, if (err) return err; - /* Release 'PR' control back to the ICAP */ - zynq_fpga_write(priv, CTRL_OFFSET, - zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); - err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, intr_status & IXR_PCFG_DONE_MASK, INIT_POLL_DELAY, INIT_POLL_TIMEOUT); + /* Release 'PR' control back to the ICAP */ + zynq_fpga_write(priv, CTRL_OFFSET, + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); + clk_disable(priv->clk); if (err) -- cgit v1.2.3