From fa63aa3dea48fd18e560c232424e080a2e2c4779 Mon Sep 17 00:00:00 2001 From: Tuomas Tynkkynen Date: Wed, 13 May 2015 17:58:38 +0300 Subject: clk: tegra: Add functions for parsing CVB tables Tegra CVB tables encode the relationship between operating voltage and optimal frequency as a function of the so-called speedo value. The speedo value is written to the on-chip fuses at the factory, which allows the voltage-frequency operating points to be calculated on an per-chip basis. Add utility functions to parse the Tegra-specific tables and export the voltage-frequency pairs to the generic OPP framework for other drivers to use. Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen Acked-by: Peter De Schrijver Acked-by: Michael Turquette Signed-off-by: Thierry Reding --- drivers/clk/tegra/cvb.h | 67 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 drivers/clk/tegra/cvb.h (limited to 'drivers/clk/tegra/cvb.h') diff --git a/drivers/clk/tegra/cvb.h b/drivers/clk/tegra/cvb.h new file mode 100644 index 000000000000..f62cdc4f4234 --- /dev/null +++ b/drivers/clk/tegra/cvb.h @@ -0,0 +1,67 @@ +/* + * Utility functions for parsing Tegra CVB voltage tables + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __DRIVERS_CLK_TEGRA_CVB_H +#define __DRIVERS_CLK_TEGRA_CVB_H + +#include + +struct device; + +#define MAX_DVFS_FREQS 40 + +struct rail_alignment { + int offset_uv; + int step_uv; +}; + +struct cvb_coefficients { + int c0; + int c1; + int c2; +}; + +struct cvb_table_freq_entry { + unsigned long freq; + struct cvb_coefficients coefficients; +}; + +struct cvb_cpu_dfll_data { + u32 tune0_low; + u32 tune0_high; + u32 tune1; +}; + +struct cvb_table { + int speedo_id; + int process_id; + + int min_millivolts; + int max_millivolts; + struct rail_alignment alignment; + + int speedo_scale; + int voltage_scale; + struct cvb_table_freq_entry cvb_table[MAX_DVFS_FREQS]; + struct cvb_cpu_dfll_data cpu_dfll_data; +}; + +const struct cvb_table *tegra_cvb_build_opp_table( + const struct cvb_table *cvb_tables, + size_t sz, int process_id, + int speedo_id, int speedo_value, + unsigned long max_rate, + struct device *opp_dev); + +#endif -- cgit v1.2.3