From 62a8a094b0e1de782a1b3dcb5e42a7d44379e583 Mon Sep 17 00:00:00 2001 From: Tuomas Tynkkynen Date: Wed, 13 May 2015 17:58:41 +0300 Subject: clk: tegra: Add Tegra124 DFLL clocksource platform driver Add basic platform driver support for the fast CPU cluster DFLL clocksource found on Tegra124 SoCs. This small driver selects the appropriate Tegra124-specific characterization data and integration code. It relies on the DFLL common code to do most of the work. Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen Acked-by: Michael Turquette [treding@nvidia.com: move setup code into ->probe()] Signed-off-by: Thierry Reding --- drivers/clk/tegra/clk-dfll.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/clk/tegra/clk-dfll.c') diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index 6ec645776897..109a79b95238 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -682,7 +682,7 @@ static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate) struct dev_pm_opp *opp; int i, uv; - opp = dev_pm_opp_find_freq_ceil(td->soc->opp_dev, &rate); + opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); if (IS_ERR(opp)) return PTR_ERR(opp); uv = dev_pm_opp_get_voltage(opp); @@ -1436,7 +1436,7 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td) rcu_read_lock(); rate = ULONG_MAX; - opp = dev_pm_opp_find_freq_floor(td->soc->opp_dev, &rate); + opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate); if (IS_ERR(opp)) { dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n"); goto out; @@ -1449,7 +1449,7 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td) goto out; for (j = 1, rate = 0; ; rate++) { - opp = dev_pm_opp_find_freq_ceil(td->soc->opp_dev, &rate); + opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); if (IS_ERR(opp)) break; v_opp = dev_pm_opp_get_voltage(opp); -- cgit v1.2.3