From 1ec7032ad517714108cc53a6ee7067276ca21e80 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 20 Apr 2015 14:34:57 +0200 Subject: clk: tegra: Add fixed factor peripheral clock type Some of the peripheral clocks on Tegra are derived from one of the top- level PLLs with a fixed factor. Support these clocks by implementing the ->enable() and ->disable() callbacks using the peripheral clock register banks and the ->recalc_rate() by dividing the parent rate by the fixed factor. Signed-off-by: Thierry Reding --- drivers/clk/tegra/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/tegra/Makefile') diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index 97984c503bbb..33fd0938d79e 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -3,6 +3,7 @@ obj-y += clk-audio-sync.o obj-y += clk-dfll.o obj-y += clk-divider.o obj-y += clk-periph.o +obj-y += clk-periph-fixed.o obj-y += clk-periph-gate.o obj-y += clk-pll.o obj-y += clk-pll-out.o -- cgit v1.2.3