From c77de0e5c95a249fd2d4105dbc619f436ec96345 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 19 Feb 2018 12:21:40 +0100 Subject: clk: meson: add gp0 frac parameter for axg and gxl Add the frac parameter for the gp0 pll of the axg and gxl. This allows to achieve rates between the fixed settings provided by the table. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- drivers/clk/meson/gxbb.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers/clk/meson/gxbb.c') diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index ac48eef0f490..fdeb372863de 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -437,7 +437,7 @@ static struct clk_regmap gxbb_gp0_pll = { }; const struct reg_sequence gxl_gp0_init_regs[] = { - { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 }, + { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, @@ -462,6 +462,11 @@ static struct clk_regmap gxl_gp0_pll = { .shift = 16, .width = 2, }, + .frac = { + .reg_off = HHI_GP0_PLL_CNTL1, + .shift = 0, + .width = 10, + }, .l = { .reg_off = HHI_GP0_PLL_CNTL, .shift = 31, -- cgit v1.2.3