From 6ef5fb2cfcedaab4a43493c8f2305a67c0ce1af6 Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@igel.co.jp>
Date: Sun, 12 Aug 2007 15:22:02 +0900
Subject: sh: intc - add a clear register to struct intc_prio_reg

We need a secondary register member in struct intc_prio_reg to support
dual priority registers used by ipi on x3.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---
 arch/sh/kernel/cpu/sh3/setup-sh7705.c | 16 ++++++++--------
 arch/sh/kernel/cpu/sh3/setup-sh770x.c | 16 ++++++++--------
 arch/sh/kernel/cpu/sh3/setup-sh7710.c | 20 ++++++++++----------
 3 files changed, 26 insertions(+), 26 deletions(-)

(limited to 'arch/sh/kernel/cpu/sh3')

diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 568cc08c254b..a1b342e170c6 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -73,14 +73,14 @@ static struct intc_prio priorities[] = {
 };
 
 static struct intc_prio_reg prio_registers[] = {
-	{ 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
-	{ 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
-	{ 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
-	{ 0xa4000018, 16, 4, /* IPRD */ { PINT07, PINT815, IRQ5, IRQ4 } },
-	{ 0xa400001a, 16, 4, /* IPRE */ { DMAC, SCIF0, SCIF2, ADC_ADI } },
-	{ 0xa4080000, 16, 4, /* IPRF */ { 0, 0, USB } },
-	{ 0xa4080002, 16, 4, /* IPRG */ { TPU0, TPU1 } },
-	{ 0xa4080004, 16, 4, /* IPRH */ { TPU2, TPU3 } },
+	{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
+	{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
+	{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
+	{ 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, IRQ5, IRQ4 } },
+	{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, SCIF0, SCIF2, ADC_ADI } },
+	{ 0xa4080000, 0, 16, 4, /* IPRF */ { 0, 0, USB } },
+	{ 0xa4080002, 0, 16, 4, /* IPRG */ { TPU0, TPU1 } },
+	{ 0xa4080004, 0, 16, 4, /* IPRH */ { TPU2, TPU3 } },
 
 };
 
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index eef505b43f0c..2980c44ffb2f 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -89,22 +89,22 @@ static struct intc_prio priorities[] = {
 };
 
 static struct intc_prio_reg prio_registers[] = {
-	{ 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
-	{ 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
+	{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
+	{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
     defined(CONFIG_CPU_SUBTYPE_SH7709)
-	{ 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
-	{ 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
-	{ 0xa400001a, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
+	{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
+	{ 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
+	{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
 #endif
 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
     defined(CONFIG_CPU_SUBTYPE_SH7709)
-	{ 0xa4000018, 16, 4, /* IPRD */ { PINT07, PINT815, } },
-	{ 0xa400001a, 16, 4, /* IPRE */ { 0, SCIF0 } },
+	{ 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
+	{ 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
 #endif
 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
-	{ 0xa400001c, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
+	{ 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
 #endif
 };
 
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index eb55ac9dbf71..5aa77710e42b 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -86,18 +86,18 @@ static struct intc_prio priorities[] = {
 };
 
 static struct intc_prio_reg prio_registers[] = {
-	{ 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
-	{ 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
-	{ 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
-	{ 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
-	{ 0xa400001a, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
-	{ 0xa4080000, 16, 4, /* IPRF */ { 0, DMAC2 } },
+	{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
+	{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
+	{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
+	{ 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
+	{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
+	{ 0xa4080000, 0, 16, 4, /* IPRF */ { 0, DMAC2 } },
 #ifdef CONFIG_CPU_SUBTYPE_SH7710
-	{ 0xa4080000, 16, 4, /* IPRF */ { IPSEC } },
+	{ 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC } },
 #endif
-	{ 0xa4080002, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
-	{ 0xa4080004, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
-	{ 0xa4080006, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
+	{ 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
+	{ 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
+	{ 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
 };
 
 static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,
-- 
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