From 7c6b155fb49fbc63e0b30a1d49552693c0b45be7 Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Mon, 25 Jul 2005 12:51:08 +0000 Subject: kbuild: drop descend - converting existing users There was only two users left of descend. Fix them so they use $(clean)= and $(build)=. Drop definition of descend. Signed-off-by: Sam Ravnborg --- --- arch/mips/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/Makefile b/arch/mips/Makefile index bc1c44274a58..26528b600b97 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -683,7 +683,7 @@ drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ ifdef CONFIG_LASAT rom.bin rom.sw: vmlinux - $(call descend,arch/mips/lasat/image,$@) + $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@ endif # -- cgit v1.2.3 From 006cfb51ad12047497a2a5ad796fb8914a1bc487 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sat, 3 Sep 2005 15:56:03 -0700 Subject: [PATCH] mips: remove obsolete GIU function call for vr41xx This patch has removed obsolete GIU function call for vr41xx. Signed-off-by: Yoichi Yuasa Cc: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/pci/fixup-tb0219.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/pci/fixup-tb0219.c b/arch/mips/pci/fixup-tb0219.c index 850a900f0eb4..bc55b06e1904 100644 --- a/arch/mips/pci/fixup-tb0219.c +++ b/arch/mips/pci/fixup-tb0219.c @@ -29,27 +29,12 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) switch (slot) { case 12: - vr41xx_set_irq_trigger(TB0219_PCI_SLOT1_PIN, - TRIGGER_LEVEL, - SIGNAL_THROUGH); - vr41xx_set_irq_level(TB0219_PCI_SLOT1_PIN, - LEVEL_LOW); irq = TB0219_PCI_SLOT1_IRQ; break; case 13: - vr41xx_set_irq_trigger(TB0219_PCI_SLOT2_PIN, - TRIGGER_LEVEL, - SIGNAL_THROUGH); - vr41xx_set_irq_level(TB0219_PCI_SLOT2_PIN, - LEVEL_LOW); irq = TB0219_PCI_SLOT2_IRQ; break; case 14: - vr41xx_set_irq_trigger(TB0219_PCI_SLOT3_PIN, - TRIGGER_LEVEL, - SIGNAL_THROUGH); - vr41xx_set_irq_level(TB0219_PCI_SLOT3_PIN, - LEVEL_LOW); irq = TB0219_PCI_SLOT3_IRQ; break; default: -- cgit v1.2.3 From 979934da9e7a0005bd9c8b1d7d00febb59ff67f7 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sat, 3 Sep 2005 15:56:04 -0700 Subject: [PATCH] mips: update IRQ handling for vr41xx This patch has updated IRQ handling for vr41xx. o added common IRQ dispatch o changed IRQ number in int-handler.S o added resource management to icu.c Signed-off-by: Yoichi Yuasa Cc: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/vr41xx/common/Makefile | 2 +- arch/mips/vr41xx/common/icu.c | 270 ++++++++++++++++------------------ arch/mips/vr41xx/common/int-handler.S | 10 +- arch/mips/vr41xx/common/irq.c | 94 ++++++++++++ include/asm-mips/vr41xx/vr41xx.h | 16 +- 5 files changed, 234 insertions(+), 158 deletions(-) create mode 100644 arch/mips/vr41xx/common/irq.c (limited to 'arch/mips') diff --git a/arch/mips/vr41xx/common/Makefile b/arch/mips/vr41xx/common/Makefile index fa98ef3855bc..e5039031b69d 100644 --- a/arch/mips/vr41xx/common/Makefile +++ b/arch/mips/vr41xx/common/Makefile @@ -2,7 +2,7 @@ # Makefile for common code of the NEC VR4100 series. # -obj-y += bcu.o cmu.o icu.o init.o int-handler.o pmu.o +obj-y += bcu.o cmu.o icu.o init.o int-handler.o irq.o pmu.o obj-$(CONFIG_VRC4173) += vrc4173.o EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c index c842661144cb..0b73c5ab3c0c 100644 --- a/arch/mips/vr41xx/common/icu.c +++ b/arch/mips/vr41xx/common/icu.c @@ -3,8 +3,7 @@ * * Copyright (C) 2001-2002 MontaVista Software Inc. * Author: Yoichi Yuasa - * Copyright (C) 2003-2004 Yoichi Yuasa - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2003-2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,7 +30,7 @@ */ #include #include -#include +#include #include #include #include @@ -39,34 +38,24 @@ #include #include -#include -#include #include -extern asmlinkage void vr41xx_handle_interrupt(void); - -extern void init_vr41xx_giuint_irq(void); -extern void giuint_irq_dispatch(struct pt_regs *regs); - -static uint32_t icu1_base; -static uint32_t icu2_base; - -static struct irqaction icu_cascade = { - .handler = no_action, - .mask = CPU_MASK_NONE, - .name = "cascade", -}; +static void __iomem *icu1_base; +static void __iomem *icu2_base; static unsigned char sysint1_assign[16] = { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; static unsigned char sysint2_assign[16] = { - 2, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; -#define SYSINT1REG_TYPE1 KSEG1ADDR(0x0b000080) -#define SYSINT2REG_TYPE1 KSEG1ADDR(0x0b000200) +#define ICU1_TYPE1_BASE 0x0b000080UL +#define ICU2_TYPE1_BASE 0x0b000200UL -#define SYSINT1REG_TYPE2 KSEG1ADDR(0x0f000080) -#define SYSINT2REG_TYPE2 KSEG1ADDR(0x0f0000a0) +#define ICU1_TYPE2_BASE 0x0f000080UL +#define ICU2_TYPE2_BASE 0x0f0000a0UL + +#define ICU1_SIZE 0x20 +#define ICU2_SIZE 0x1c #define SYSINT1REG 0x00 #define PIUINTREG 0x02 @@ -106,61 +95,61 @@ static unsigned char sysint2_assign[16] = { #define SYSINT1_IRQ_TO_PIN(x) ((x) - SYSINT1_IRQ_BASE) /* Pin 0-15 */ #define SYSINT2_IRQ_TO_PIN(x) ((x) - SYSINT2_IRQ_BASE) /* Pin 0-15 */ -#define read_icu1(offset) readw(icu1_base + (offset)) -#define write_icu1(val, offset) writew((val), icu1_base + (offset)) +#define INT_TO_IRQ(x) ((x) + 2) /* Int0-4 -> IRQ2-6 */ + +#define icu1_read(offset) readw(icu1_base + (offset)) +#define icu1_write(offset, value) writew((value), icu1_base + (offset)) -#define read_icu2(offset) readw(icu2_base + (offset)) -#define write_icu2(val, offset) writew((val), icu2_base + (offset)) +#define icu2_read(offset) readw(icu2_base + (offset)) +#define icu2_write(offset, value) writew((value), icu2_base + (offset)) #define INTASSIGN_MAX 4 #define INTASSIGN_MASK 0x0007 -static inline uint16_t set_icu1(uint8_t offset, uint16_t set) +static inline uint16_t icu1_set(uint8_t offset, uint16_t set) { - uint16_t res; + uint16_t data; - res = read_icu1(offset); - res |= set; - write_icu1(res, offset); + data = icu1_read(offset); + data |= set; + icu1_write(offset, data); - return res; + return data; } -static inline uint16_t clear_icu1(uint8_t offset, uint16_t clear) +static inline uint16_t icu1_clear(uint8_t offset, uint16_t clear) { - uint16_t res; + uint16_t data; - res = read_icu1(offset); - res &= ~clear; - write_icu1(res, offset); + data = icu1_read(offset); + data &= ~clear; + icu1_write(offset, data); - return res; + return data; } -static inline uint16_t set_icu2(uint8_t offset, uint16_t set) +static inline uint16_t icu2_set(uint8_t offset, uint16_t set) { - uint16_t res; + uint16_t data; - res = read_icu2(offset); - res |= set; - write_icu2(res, offset); + data = icu2_read(offset); + data |= set; + icu2_write(offset, data); - return res; + return data; } -static inline uint16_t clear_icu2(uint8_t offset, uint16_t clear) +static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear) { - uint16_t res; + uint16_t data; - res = read_icu2(offset); - res &= ~clear; - write_icu2(res, offset); + data = icu2_read(offset); + data &= ~clear; + icu2_write(offset, data); - return res; + return data; } -/*=======================================================================*/ - void vr41xx_enable_piuint(uint16_t mask) { irq_desc_t *desc = irq_desc + PIU_IRQ; @@ -169,7 +158,7 @@ void vr41xx_enable_piuint(uint16_t mask) if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - set_icu1(MPIUINTREG, mask); + icu1_set(MPIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -184,7 +173,7 @@ void vr41xx_disable_piuint(uint16_t mask) if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MPIUINTREG, mask); + icu1_clear(MPIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -199,7 +188,7 @@ void vr41xx_enable_aiuint(uint16_t mask) if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - set_icu1(MAIUINTREG, mask); + icu1_set(MAIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -214,7 +203,7 @@ void vr41xx_disable_aiuint(uint16_t mask) if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MAIUINTREG, mask); + icu1_clear(MAIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -229,7 +218,7 @@ void vr41xx_enable_kiuint(uint16_t mask) if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - set_icu1(MKIUINTREG, mask); + icu1_set(MKIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -244,7 +233,7 @@ void vr41xx_disable_kiuint(uint16_t mask) if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MKIUINTREG, mask); + icu1_clear(MKIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -257,7 +246,7 @@ void vr41xx_enable_dsiuint(uint16_t mask) unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - set_icu1(MDSIUINTREG, mask); + icu1_set(MDSIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -269,7 +258,7 @@ void vr41xx_disable_dsiuint(uint16_t mask) unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MDSIUINTREG, mask); + icu1_clear(MDSIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -281,7 +270,7 @@ void vr41xx_enable_firint(uint16_t mask) unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - set_icu2(MFIRINTREG, mask); + icu2_set(MFIRINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -293,7 +282,7 @@ void vr41xx_disable_firint(uint16_t mask) unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - clear_icu2(MFIRINTREG, mask); + icu2_clear(MFIRINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -308,7 +297,7 @@ void vr41xx_enable_pciint(void) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(PCIINT0, MPCIINTREG); + icu2_write(MPCIINTREG, PCIINT0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -324,7 +313,7 @@ void vr41xx_disable_pciint(void) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(0, MPCIINTREG); + icu2_write(MPCIINTREG, 0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -340,7 +329,7 @@ void vr41xx_enable_scuint(void) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(SCUINT0, MSCUINTREG); + icu2_write(MSCUINTREG, SCUINT0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -356,7 +345,7 @@ void vr41xx_disable_scuint(void) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(0, MSCUINTREG); + icu2_write(MSCUINTREG, 0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -372,7 +361,7 @@ void vr41xx_enable_csiint(uint16_t mask) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - set_icu2(MCSIINTREG, mask); + icu2_set(MCSIINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -388,7 +377,7 @@ void vr41xx_disable_csiint(uint16_t mask) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - clear_icu2(MCSIINTREG, mask); + icu2_clear(MCSIINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -404,7 +393,7 @@ void vr41xx_enable_bcuint(void) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(BCUINTR, MBCUINTREG); + icu2_write(MBCUINTREG, BCUINTR); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -420,30 +409,28 @@ void vr41xx_disable_bcuint(void) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(0, MBCUINTREG); + icu2_write(MBCUINTREG, 0); spin_unlock_irqrestore(&desc->lock, flags); } } EXPORT_SYMBOL(vr41xx_disable_bcuint); -/*=======================================================================*/ - static unsigned int startup_sysint1_irq(unsigned int irq) { - set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); return 0; /* never anything pending */ } static void shutdown_sysint1_irq(unsigned int irq) { - clear_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); } static void enable_sysint1_irq(unsigned int irq) { - set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); } #define disable_sysint1_irq shutdown_sysint1_irq @@ -452,7 +439,7 @@ static void enable_sysint1_irq(unsigned int irq) static void end_sysint1_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); } static struct hw_interrupt_type sysint1_irq_type = { @@ -465,23 +452,21 @@ static struct hw_interrupt_type sysint1_irq_type = { .end = end_sysint1_irq, }; -/*=======================================================================*/ - static unsigned int startup_sysint2_irq(unsigned int irq) { - set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); return 0; /* never anything pending */ } static void shutdown_sysint2_irq(unsigned int irq) { - clear_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); } static void enable_sysint2_irq(unsigned int irq) { - set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); } #define disable_sysint2_irq shutdown_sysint2_irq @@ -490,7 +475,7 @@ static void enable_sysint2_irq(unsigned int irq) static void end_sysint2_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); } static struct hw_interrupt_type sysint2_irq_type = { @@ -503,8 +488,6 @@ static struct hw_interrupt_type sysint2_irq_type = { .end = end_sysint2_irq, }; -/*=======================================================================*/ - static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) { irq_desc_t *desc = irq_desc + irq; @@ -515,8 +498,8 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) spin_lock_irq(&desc->lock); - intassign0 = read_icu1(INTASSIGN0); - intassign1 = read_icu1(INTASSIGN1); + intassign0 = icu1_read(INTASSIGN0); + intassign1 = icu1_read(INTASSIGN1); switch (pin) { case 0: @@ -556,8 +539,8 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) } sysint1_assign[pin] = assign; - write_icu1(intassign0, INTASSIGN0); - write_icu1(intassign1, INTASSIGN1); + icu1_write(INTASSIGN0, intassign0); + icu1_write(INTASSIGN1, intassign1); spin_unlock_irq(&desc->lock); @@ -574,8 +557,8 @@ static inline int set_sysint2_assign(unsigned int irq, unsigned char assign) spin_lock_irq(&desc->lock); - intassign2 = read_icu1(INTASSIGN2); - intassign3 = read_icu1(INTASSIGN3); + intassign2 = icu1_read(INTASSIGN2); + intassign3 = icu1_read(INTASSIGN3); switch (pin) { case 0: @@ -623,8 +606,8 @@ static inline int set_sysint2_assign(unsigned int irq, unsigned char assign) } sysint2_assign[pin] = assign; - write_icu1(intassign2, INTASSIGN2); - write_icu1(intassign3, INTASSIGN3); + icu1_write(INTASSIGN2, intassign2); + icu1_write(INTASSIGN3, intassign3); spin_unlock_irq(&desc->lock); @@ -651,88 +634,92 @@ int vr41xx_set_intassign(unsigned int irq, unsigned char intassign) EXPORT_SYMBOL(vr41xx_set_intassign); -/*=======================================================================*/ - -asmlinkage void irq_dispatch(unsigned char intnum, struct pt_regs *regs) +static int icu_get_irq(unsigned int irq, struct pt_regs *regs) { uint16_t pend1, pend2; uint16_t mask1, mask2; int i; - pend1 = read_icu1(SYSINT1REG); - mask1 = read_icu1(MSYSINT1REG); + pend1 = icu1_read(SYSINT1REG); + mask1 = icu1_read(MSYSINT1REG); - pend2 = read_icu2(SYSINT2REG); - mask2 = read_icu2(MSYSINT2REG); + pend2 = icu2_read(SYSINT2REG); + mask2 = icu2_read(MSYSINT2REG); mask1 &= pend1; mask2 &= pend2; if (mask1) { for (i = 0; i < 16; i++) { - if (intnum == sysint1_assign[i] && - (mask1 & ((uint16_t)1 << i))) { - if (i == 8) - giuint_irq_dispatch(regs); - else - do_IRQ(SYSINT1_IRQ(i), regs); - return; - } + if (irq == INT_TO_IRQ(sysint1_assign[i]) && (mask1 & (1 << i))) + return SYSINT1_IRQ(i); } } if (mask2) { for (i = 0; i < 16; i++) { - if (intnum == sysint2_assign[i] && - (mask2 & ((uint16_t)1 << i))) { - do_IRQ(SYSINT2_IRQ(i), regs); - return; - } + if (irq == INT_TO_IRQ(sysint2_assign[i]) && (mask2 & (1 << i))) + return SYSINT2_IRQ(i); } } printk(KERN_ERR "spurious ICU interrupt: %04x,%04x\n", pend1, pend2); atomic_inc(&irq_err_count); -} -/*=======================================================================*/ + return -1; +} static int __init vr41xx_icu_init(void) { + unsigned long icu1_start, icu2_start; + int i; + switch (current_cpu_data.cputype) { case CPU_VR4111: case CPU_VR4121: - icu1_base = SYSINT1REG_TYPE1; - icu2_base = SYSINT2REG_TYPE1; + icu1_start = ICU1_TYPE1_BASE; + icu2_start = ICU2_TYPE1_BASE; break; case CPU_VR4122: case CPU_VR4131: case CPU_VR4133: - icu1_base = SYSINT1REG_TYPE2; - icu2_base = SYSINT2REG_TYPE2; + icu1_start = ICU1_TYPE2_BASE; + icu2_start = ICU2_TYPE2_BASE; break; default: printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n"); - return -EINVAL; + return -ENODEV; } - write_icu1(0, MSYSINT1REG); - write_icu1(0xffff, MGIUINTLREG); + if (request_mem_region(icu1_start, ICU1_SIZE, "ICU") == NULL) + return -EBUSY; - write_icu2(0, MSYSINT2REG); - write_icu2(0xffff, MGIUINTHREG); + if (request_mem_region(icu2_start, ICU2_SIZE, "ICU") == NULL) { + release_mem_region(icu1_start, ICU1_SIZE); + return -EBUSY; + } - return 0; -} + icu1_base = ioremap(icu1_start, ICU1_SIZE); + if (icu1_base == NULL) { + release_mem_region(icu1_start, ICU1_SIZE); + release_mem_region(icu2_start, ICU2_SIZE); + return -ENOMEM; + } -early_initcall(vr41xx_icu_init); + icu2_base = ioremap(icu2_start, ICU2_SIZE); + if (icu2_base == NULL) { + iounmap(icu1_base); + release_mem_region(icu1_start, ICU1_SIZE); + release_mem_region(icu2_start, ICU2_SIZE); + return -ENOMEM; + } -/*=======================================================================*/ + icu1_write(MSYSINT1REG, 0); + icu1_write(MGIUINTLREG, 0xffff); -static inline void init_vr41xx_icu_irq(void) -{ - int i; + icu2_write(MSYSINT2REG, 0); + icu2_write(MGIUINTHREG, 0xffff); for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) irq_desc[i].handler = &sysint1_irq_type; @@ -740,18 +727,13 @@ static inline void init_vr41xx_icu_irq(void) for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) irq_desc[i].handler = &sysint2_irq_type; - setup_irq(INT0_CASCADE_IRQ, &icu_cascade); - setup_irq(INT1_CASCADE_IRQ, &icu_cascade); - setup_irq(INT2_CASCADE_IRQ, &icu_cascade); - setup_irq(INT3_CASCADE_IRQ, &icu_cascade); - setup_irq(INT4_CASCADE_IRQ, &icu_cascade); -} + cascade_irq(INT0_IRQ, icu_get_irq); + cascade_irq(INT1_IRQ, icu_get_irq); + cascade_irq(INT2_IRQ, icu_get_irq); + cascade_irq(INT3_IRQ, icu_get_irq); + cascade_irq(INT4_IRQ, icu_get_irq); -void __init arch_init_irq(void) -{ - mips_cpu_irq_init(MIPS_CPU_IRQ_BASE); - init_vr41xx_icu_irq(); - init_vr41xx_giuint_irq(); - - set_except_vector(0, vr41xx_handle_interrupt); + return 0; } + +core_initcall(vr41xx_icu_init); diff --git a/arch/mips/vr41xx/common/int-handler.S b/arch/mips/vr41xx/common/int-handler.S index 38ff89b505f2..272c13aee4fd 100644 --- a/arch/mips/vr41xx/common/int-handler.S +++ b/arch/mips/vr41xx/common/int-handler.S @@ -71,24 +71,24 @@ andi t1, t0, CAUSEF_IP3 # check for Int1 bnez t1, handle_int - li a0, 1 + li a0, 3 andi t1, t0, CAUSEF_IP4 # check for Int2 bnez t1, handle_int - li a0, 2 + li a0, 4 andi t1, t0, CAUSEF_IP5 # check for Int3 bnez t1, handle_int - li a0, 3 + li a0, 5 andi t1, t0, CAUSEF_IP6 # check for Int4 bnez t1, handle_int - li a0, 4 + li a0, 6 1: andi t1, t0, CAUSEF_IP2 # check for Int0 bnez t1, handle_int - li a0, 0 + li a0, 2 andi t1, t0, CAUSEF_IP0 # check for IP0 bnez t1, handle_irq diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c new file mode 100644 index 000000000000..43b214d39438 --- /dev/null +++ b/arch/mips/vr41xx/common/irq.c @@ -0,0 +1,94 @@ +/* + * Interrupt handing routines for NEC VR4100 series. + * + * Copyright (C) 2005 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include + +#include +#include +#include + +typedef struct irq_cascade { + int (*get_irq)(unsigned int, struct pt_regs *); +} irq_cascade_t; + +static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned; + +static struct irqaction cascade_irqaction = { + .handler = no_action, + .mask = CPU_MASK_NONE, + .name = "cascade", +}; + +int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)) +{ + int retval = 0; + + if (irq >= NR_IRQS) + return -EINVAL; + + if (irq_cascade[irq].get_irq != NULL) + free_irq(irq, NULL); + + irq_cascade[irq].get_irq = get_irq; + + if (get_irq != NULL) { + retval = setup_irq(irq, &cascade_irqaction); + if (retval < 0) + irq_cascade[irq].get_irq = NULL; + } + + return retval; +} + +EXPORT_SYMBOL_GPL(cascade_irq); + +asmlinkage void irq_dispatch(unsigned int irq, struct pt_regs *regs) +{ + irq_cascade_t *cascade; + irq_desc_t *desc; + + if (irq >= NR_IRQS) { + atomic_inc(&irq_err_count); + return; + } + + cascade = irq_cascade + irq; + if (cascade->get_irq != NULL) { + unsigned int source_irq = irq; + desc = irq_desc + source_irq; + desc->handler->ack(source_irq); + irq = cascade->get_irq(irq, regs); + if (irq < 0) + atomic_inc(&irq_err_count); + else + irq_dispatch(irq, regs); + desc->handler->end(source_irq); + } else + do_IRQ(irq, regs); +} + +extern asmlinkage void vr41xx_handle_interrupt(void); + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(MIPS_CPU_IRQ_BASE); + + set_except_vector(0, vr41xx_handle_interrupt); +} diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h index 7d41e44463f9..bd2723c30901 100644 --- a/include/asm-mips/vr41xx/vr41xx.h +++ b/include/asm-mips/vr41xx/vr41xx.h @@ -7,7 +7,7 @@ * Copyright (C) 2001, 2002 Paul Mundt * Copyright (C) 2002 MontaVista Software, Inc. * Copyright (C) 2002 TimeSys Corp. - * Copyright (C) 2003-2004 Yoichi Yuasa + * Copyright (C) 2003-2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -79,11 +79,11 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock); #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) #define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0) #define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1) -#define INT0_CASCADE_IRQ MIPS_CPU_IRQ(2) -#define INT1_CASCADE_IRQ MIPS_CPU_IRQ(3) -#define INT2_CASCADE_IRQ MIPS_CPU_IRQ(4) -#define INT3_CASCADE_IRQ MIPS_CPU_IRQ(5) -#define INT4_CASCADE_IRQ MIPS_CPU_IRQ(6) +#define INT0_IRQ MIPS_CPU_IRQ(2) +#define INT1_IRQ MIPS_CPU_IRQ(3) +#define INT2_IRQ MIPS_CPU_IRQ(4) +#define INT3_IRQ MIPS_CPU_IRQ(5) +#define INT4_IRQ MIPS_CPU_IRQ(6) #define TIMER_IRQ MIPS_CPU_IRQ(7) /* SYINT1 Interrupt Numbers */ @@ -97,7 +97,7 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock); #define PIU_IRQ SYSINT1_IRQ(5) #define AIU_IRQ SYSINT1_IRQ(6) #define KIU_IRQ SYSINT1_IRQ(7) -#define GIUINT_CASCADE_IRQ SYSINT1_IRQ(8) +#define GIUINT_IRQ SYSINT1_IRQ(8) #define SIU_IRQ SYSINT1_IRQ(9) #define BUSERR_IRQ SYSINT1_IRQ(10) #define SOFTINT_IRQ SYSINT1_IRQ(11) @@ -128,7 +128,7 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock); #define GIU_IRQ_LAST GIU_IRQ(31) extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign); -extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq)); +extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)); #define PIUINT_COMMAND 0x0040 #define PIUINT_DATA 0x0020 -- cgit v1.2.3 From 8bb670c1407c2a4890810fd3e348dac1b89e669e Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sat, 3 Sep 2005 15:56:05 -0700 Subject: [PATCH] mips: change system type name in proc for vr41xx This patch has changed system type name in proc for vr41xx. Signed-off-by: Yoichi Yuasa Cc: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/Makefile | 4 ---- arch/mips/vr41xx/casio-e55/setup.c | 5 ----- arch/mips/vr41xx/common/Makefile | 2 +- arch/mips/vr41xx/common/type.c | 24 ++++++++++++++++++++++++ arch/mips/vr41xx/ibm-workpad/setup.c | 5 ----- arch/mips/vr41xx/nec-cmbvr4133/init.c | 12 ------------ arch/mips/vr41xx/tanbac-tb0226/Makefile | 5 ----- arch/mips/vr41xx/tanbac-tb0226/setup.c | 24 ------------------------ arch/mips/vr41xx/tanbac-tb0229/Makefile | 5 ----- arch/mips/vr41xx/tanbac-tb0229/setup.c | 27 --------------------------- arch/mips/vr41xx/victor-mpc30x/Makefile | 5 ----- arch/mips/vr41xx/victor-mpc30x/setup.c | 24 ------------------------ arch/mips/vr41xx/zao-capcella/Makefile | 5 ----- arch/mips/vr41xx/zao-capcella/setup.c | 24 ------------------------ 14 files changed, 25 insertions(+), 146 deletions(-) create mode 100644 arch/mips/vr41xx/common/type.c delete mode 100644 arch/mips/vr41xx/tanbac-tb0226/Makefile delete mode 100644 arch/mips/vr41xx/tanbac-tb0226/setup.c delete mode 100644 arch/mips/vr41xx/tanbac-tb0229/Makefile delete mode 100644 arch/mips/vr41xx/tanbac-tb0229/setup.c delete mode 100644 arch/mips/vr41xx/victor-mpc30x/Makefile delete mode 100644 arch/mips/vr41xx/victor-mpc30x/setup.c delete mode 100644 arch/mips/vr41xx/zao-capcella/Makefile delete mode 100644 arch/mips/vr41xx/zao-capcella/setup.c (limited to 'arch/mips') diff --git a/arch/mips/Makefile b/arch/mips/Makefile index bc1c44274a58..bf874f45144f 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -490,13 +490,11 @@ load-$(CONFIG_NEC_CMBVR4133) += 0xffffffff80100000 # # ZAO Networks Capcella (VR4131) # -core-$(CONFIG_ZAO_CAPCELLA) += arch/mips/vr41xx/zao-capcella/ load-$(CONFIG_ZAO_CAPCELLA) += 0xffffffff80000000 # # Victor MP-C303/304 (VR4122) # -core-$(CONFIG_VICTOR_MPC30X) += arch/mips/vr41xx/victor-mpc30x/ load-$(CONFIG_VICTOR_MPC30X) += 0xffffffff80001000 # @@ -514,13 +512,11 @@ load-$(CONFIG_CASIO_E55) += 0xffffffff80004000 # # TANBAC TB0226 Mbase (VR4131) # -core-$(CONFIG_TANBAC_TB0226) += arch/mips/vr41xx/tanbac-tb0226/ load-$(CONFIG_TANBAC_TB0226) += 0xffffffff80000000 # # TANBAC TB0229 VR4131DIMM (VR4131) # -core-$(CONFIG_TANBAC_TB0229) += arch/mips/vr41xx/tanbac-tb0229/ load-$(CONFIG_TANBAC_TB0229) += 0xffffffff80000000 # diff --git a/arch/mips/vr41xx/casio-e55/setup.c b/arch/mips/vr41xx/casio-e55/setup.c index aa8605ab76ff..d29201acc4f3 100644 --- a/arch/mips/vr41xx/casio-e55/setup.c +++ b/arch/mips/vr41xx/casio-e55/setup.c @@ -23,11 +23,6 @@ #include #include -const char *get_system_type(void) -{ - return "CASIO CASSIOPEIA E-11/15/55/65"; -} - static int __init casio_e55_setup(void) { set_io_port_base(IO_PORT_BASE); diff --git a/arch/mips/vr41xx/common/Makefile b/arch/mips/vr41xx/common/Makefile index e5039031b69d..9096302a7ecc 100644 --- a/arch/mips/vr41xx/common/Makefile +++ b/arch/mips/vr41xx/common/Makefile @@ -2,7 +2,7 @@ # Makefile for common code of the NEC VR4100 series. # -obj-y += bcu.o cmu.o icu.o init.o int-handler.o irq.o pmu.o +obj-y += bcu.o cmu.o icu.o init.o int-handler.o irq.o pmu.o type.o obj-$(CONFIG_VRC4173) += vrc4173.o EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/vr41xx/common/type.c b/arch/mips/vr41xx/common/type.c new file mode 100644 index 000000000000..bcb5f71b5026 --- /dev/null +++ b/arch/mips/vr41xx/common/type.c @@ -0,0 +1,24 @@ +/* + * type.c, System type for NEC VR4100 series. + * + * Copyright (C) 2005 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +const char *get_system_type(void) +{ + return "NEC VR4100 series"; +} diff --git a/arch/mips/vr41xx/ibm-workpad/setup.c b/arch/mips/vr41xx/ibm-workpad/setup.c index cff44602d3d4..e4b34ad6ea61 100644 --- a/arch/mips/vr41xx/ibm-workpad/setup.c +++ b/arch/mips/vr41xx/ibm-workpad/setup.c @@ -23,11 +23,6 @@ #include #include -const char *get_system_type(void) -{ - return "IBM WorkPad z50"; -} - static int __init ibm_workpad_setup(void) { set_io_port_base(IO_PORT_BASE); diff --git a/arch/mips/vr41xx/nec-cmbvr4133/init.c b/arch/mips/vr41xx/nec-cmbvr4133/init.c index 87f06b3f5a9c..be590edb0b83 100644 --- a/arch/mips/vr41xx/nec-cmbvr4133/init.c +++ b/arch/mips/vr41xx/nec-cmbvr4133/init.c @@ -16,11 +16,6 @@ * Manish Lachwani (mlachwani@mvista.com) */ #include -#include -#include -#include - -#include #ifdef CONFIG_ROCKHOPPER #include @@ -28,14 +23,7 @@ #define PCICONFDREG 0xaf000c14 #define PCICONFAREG 0xaf000c18 -#endif - -const char *get_system_type(void) -{ - return "NEC CMB-VR4133"; -} -#ifdef CONFIG_ROCKHOPPER void disable_pcnet(void) { u32 data; diff --git a/arch/mips/vr41xx/tanbac-tb0226/Makefile b/arch/mips/vr41xx/tanbac-tb0226/Makefile deleted file mode 100644 index 372f953d240b..000000000000 --- a/arch/mips/vr41xx/tanbac-tb0226/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the TANBAC TB0226 specific parts of the kernel -# - -obj-y += setup.o diff --git a/arch/mips/vr41xx/tanbac-tb0226/setup.c b/arch/mips/vr41xx/tanbac-tb0226/setup.c deleted file mode 100644 index 60027e5dea25..000000000000 --- a/arch/mips/vr41xx/tanbac-tb0226/setup.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * setup.c, Setup for the TANBAC TB0226. - * - * Copyright (C) 2002-2005 Yoichi Yuasa - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -const char *get_system_type(void) -{ - return "TANBAC TB0226"; -} diff --git a/arch/mips/vr41xx/tanbac-tb0229/Makefile b/arch/mips/vr41xx/tanbac-tb0229/Makefile deleted file mode 100644 index 9c6b864ef2ef..000000000000 --- a/arch/mips/vr41xx/tanbac-tb0229/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the TANBAC TB0229(VR4131DIMM) specific parts of the kernel -# - -obj-y := setup.o diff --git a/arch/mips/vr41xx/tanbac-tb0229/setup.c b/arch/mips/vr41xx/tanbac-tb0229/setup.c deleted file mode 100644 index 5c1b757bfb0c..000000000000 --- a/arch/mips/vr41xx/tanbac-tb0229/setup.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * setup.c, Setup for the TANBAC TB0229 (VR4131DIMM) - * - * Copyright (C) 2002-2005 Yoichi Yuasa - * - * Modified for TANBAC TB0229: - * Copyright (C) 2003 Megasolution Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -const char *get_system_type(void) -{ - return "TANBAC TB0229"; -} diff --git a/arch/mips/vr41xx/victor-mpc30x/Makefile b/arch/mips/vr41xx/victor-mpc30x/Makefile deleted file mode 100644 index a2e8086a31a6..000000000000 --- a/arch/mips/vr41xx/victor-mpc30x/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the Victor MP-C303/304 specific parts of the kernel -# - -obj-y += setup.o diff --git a/arch/mips/vr41xx/victor-mpc30x/setup.c b/arch/mips/vr41xx/victor-mpc30x/setup.c deleted file mode 100644 index f591e36726e6..000000000000 --- a/arch/mips/vr41xx/victor-mpc30x/setup.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * setup.c, Setup for the Victor MP-C303/304. - * - * Copyright (C) 2002-2005 Yoichi Yuasa - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -const char *get_system_type(void) -{ - return "Victor MP-C303/304"; -} diff --git a/arch/mips/vr41xx/zao-capcella/Makefile b/arch/mips/vr41xx/zao-capcella/Makefile deleted file mode 100644 index cf420197cd23..000000000000 --- a/arch/mips/vr41xx/zao-capcella/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the ZAO Networks Capcella specific parts of the kernel -# - -obj-y += setup.o diff --git a/arch/mips/vr41xx/zao-capcella/setup.c b/arch/mips/vr41xx/zao-capcella/setup.c deleted file mode 100644 index 17bade241fe2..000000000000 --- a/arch/mips/vr41xx/zao-capcella/setup.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * setup.c, Setup for the ZAO Networks Capcella. - * - * Copyright (C) 2002-2005 Yoichi Yuasa - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -const char *get_system_type(void) -{ - return "ZAO Networks Capcella"; -} -- cgit v1.2.3 From 0fdda107e10133583f31c72326959555bfb61042 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 3 Sep 2005 15:56:06 -0700 Subject: [PATCH] mips: remove VR4181 support There seem to be no more users or interest in the NEC Osprey evaluation system for the NEC VR4181 SOC which is an old part anyway, so remove the code. More information on the Osprey can be found at http://www.linux-mips.org/wiki/Osprey. Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/configs/osprey_defconfig | 618 ---------------------------------- arch/mips/vr4181/common/Makefile | 7 - arch/mips/vr4181/common/int_handler.S | 206 ------------ arch/mips/vr4181/common/irq.c | 239 ------------- arch/mips/vr4181/common/serial.c | 51 --- arch/mips/vr4181/common/time.c | 145 -------- arch/mips/vr4181/osprey/Makefile | 7 - arch/mips/vr4181/osprey/dbg_io.c | 136 -------- arch/mips/vr4181/osprey/prom.c | 49 --- arch/mips/vr4181/osprey/reset.c | 40 --- arch/mips/vr4181/osprey/setup.c | 68 ---- include/asm-mips/vr4181/irq.h | 122 ------- include/asm-mips/vr4181/vr4181.h | 413 ----------------------- 13 files changed, 2101 deletions(-) delete mode 100644 arch/mips/configs/osprey_defconfig delete mode 100644 arch/mips/vr4181/common/Makefile delete mode 100644 arch/mips/vr4181/common/int_handler.S delete mode 100644 arch/mips/vr4181/common/irq.c delete mode 100644 arch/mips/vr4181/common/serial.c delete mode 100644 arch/mips/vr4181/common/time.c delete mode 100644 arch/mips/vr4181/osprey/Makefile delete mode 100644 arch/mips/vr4181/osprey/dbg_io.c delete mode 100644 arch/mips/vr4181/osprey/prom.c delete mode 100644 arch/mips/vr4181/osprey/reset.c delete mode 100644 arch/mips/vr4181/osprey/setup.c delete mode 100644 include/asm-mips/vr4181/irq.h delete mode 100644 include/asm-mips/vr4181/vr4181.h (limited to 'arch/mips') diff --git a/arch/mips/configs/osprey_defconfig b/arch/mips/configs/osprey_defconfig deleted file mode 100644 index 989cb9e7ae83..000000000000 --- a/arch/mips/configs/osprey_defconfig +++ /dev/null @@ -1,618 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:08 2005 -# -CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -CONFIG_KOBJECT_UEVENT=y -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_FUTEX=y -CONFIG_EPOLL=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SHMEM=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -# CONFIG_TINY_SHMEM is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y - -# -# Machine selection -# -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MIPS_EV96100 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set -# CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set -# CONFIG_DDB5477 is not set -CONFIG_NEC_OSPREY=y -# CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_VR4181=y - -# -# CPU selection -# -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -CONFIG_CPU_VR41XX=y -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -# CONFIG_CPU_ADVANCED is not set -CONFIG_CPU_HAS_SYNC=y -# CONFIG_PREEMPT is not set - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PC-card bridges -# - -# -# PCI Hotplug Support -# - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_ATA_OVER_ETH=m - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -# CONFIG_NFSD_V3 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_EXPORTFS=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="ip=bootp ether=46,0x03fe0300,eth0" - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -CONFIG_LIBCRC32C=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y diff --git a/arch/mips/vr4181/common/Makefile b/arch/mips/vr4181/common/Makefile deleted file mode 100644 index f7587ca64ead..000000000000 --- a/arch/mips/vr4181/common/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Makefile for common code of NEC vr4181 based boards -# - -obj-y := irq.o int_handler.o serial.o time.o - -EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/vr4181/common/int_handler.S b/arch/mips/vr4181/common/int_handler.S deleted file mode 100644 index 2c041b8ee52b..000000000000 --- a/arch/mips/vr4181/common/int_handler.S +++ /dev/null @@ -1,206 +0,0 @@ -/* - * arch/mips/vr4181/common/int_handler.S - * - * Adapted to the VR4181 and almost entirely rewritten: - * Copyright (C) 1999 Bradley D. LaRonde and Michael Klar - * - * Clean up to conform to the new IRQ - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ - -#include -#include -#include -#include - -#include - -/* - * [jsun] - * See include/asm/vr4181/irq.h for IRQ assignment and strategy. - */ - - .text - .set noreorder - - .align 5 - NESTED(vr4181_handle_irq, PT_SIZE, ra) - - .set noat - SAVE_ALL - CLI - - .set at - .set noreorder - - mfc0 t0, CP0_CAUSE - mfc0 t2, CP0_STATUS - - and t0, t2 - - /* we check IP3 first; it happens most frequently */ - andi t1, t0, STATUSF_IP3 - bnez t1, ll_cpu_ip3 - andi t1, t0, STATUSF_IP2 - bnez t1, ll_cpu_ip2 - andi t1, t0, STATUSF_IP7 /* cpu timer */ - bnez t1, ll_cputimer_irq - andi t1, t0, STATUSF_IP4 - bnez t1, ll_cpu_ip4 - andi t1, t0, STATUSF_IP5 - bnez t1, ll_cpu_ip5 - andi t1, t0, STATUSF_IP6 - bnez t1, ll_cpu_ip6 - andi t1, t0, STATUSF_IP0 /* software int 0 */ - bnez t1, ll_cpu_ip0 - andi t1, t0, STATUSF_IP1 /* software int 1 */ - bnez t1, ll_cpu_ip1 - nop - - .set reorder -do_spurious: - j spurious_interrupt - -/* - * regular CPU irqs - */ -ll_cputimer_irq: - li a0, VR4181_IRQ_TIMER - move a1, sp - jal do_IRQ - j ret_from_irq - - -ll_cpu_ip0: - li a0, VR4181_IRQ_SW1 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip1: - li a0, VR4181_IRQ_SW2 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip3: - li a0, VR4181_IRQ_INT1 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip4: - li a0, VR4181_IRQ_INT2 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip5: - li a0, VR4181_IRQ_INT3 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip6: - li a0, VR4181_IRQ_INT4 - move a1, sp - jal do_IRQ - j ret_from_irq - -/* - * One of the sys irq has happend. - * - * In the interest of speed, we first determine in the following order - * which 16-irq block have pending interrupts: - * sysint1 (16 sources, including cascading intrs from GPIO) - * sysint2 - * gpio (16 intr sources) - * - * Then we do binary search to find the exact interrupt source. - */ -ll_cpu_ip2: - - lui t3,%hi(VR4181_SYSINT1REG) - lhu t0,%lo(VR4181_SYSINT1REG)(t3) - lhu t2,%lo(VR4181_MSYSINT1REG)(t3) - and t0, 0xfffb /* hack - remove RTC Long 1 intr */ - and t0, t2 - beqz t0, check_sysint2 - - /* check for GPIO interrupts */ - andi t1, t0, 0x0100 - bnez t1, check_gpio_int - - /* so we have an interrupt in sysint1 which is not gpio int */ - li a0, VR4181_SYS_IRQ_BASE - 1 - j check_16 - -check_sysint2: - - lhu t0,%lo(VR4181_SYSINT2REG)(t3) - lhu t2,%lo(VR4181_MSYSINT2REG)(t3) - and t0, 0xfffe /* hack - remove RTC Long 2 intr */ - and t0, t2 - li a0, VR4181_SYS_IRQ_BASE + 16 - 1 - j check_16 - -check_gpio_int: - lui t3,%hi(VR4181_GPINTMSK) - lhu t0,%lo(VR4181_GPINTMSK)(t3) - lhu t2,%lo(VR4181_GPINTSTAT)(t3) - xori t0, 0xffff /* why? reverse logic? */ - and t0, t2 - li a0, VR4181_GPIO_IRQ_BASE - 1 - j check_16 - -/* - * When we reach check_16, we have 16-bit status in t0 and base irq number - * in a0. - */ -check_16: - andi t1, t0, 0xff - bnez t1, check_8 - - srl t0, 8 - addi a0, 8 - j check_8 - -/* - * When we reach check_8, we have 8-bit status in t0 and base irq number - * in a0. - */ -check_8: - andi t1, t0, 0xf - bnez t1, check_4 - - srl t0, 4 - addi a0, 4 - j check_4 - -/* - * When we reach check_4, we have 4-bit status in t0 and base irq number - * in a0. - */ -check_4: - andi t0, t0, 0xf - beqz t0, do_spurious - -loop: - andi t2, t0, 0x1 - srl t0, 1 - addi a0, 1 - beqz t2, loop - -found_it: - move a1, sp - jal do_IRQ - - j ret_from_irq - - END(vr4181_handle_irq) diff --git a/arch/mips/vr4181/common/irq.c b/arch/mips/vr4181/common/irq.c deleted file mode 100644 index 2cdf77c5cb3e..000000000000 --- a/arch/mips/vr4181/common/irq.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - * - * linux/arch/mips/vr4181/common/irq.c - * Completely re-written to use the new irq.c - * - * Credits to Bradley D. LaRonde and Michael Klar for writing the original - * irq.c file which was derived from the common irq.c file. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -/* - * Strategy: - * - * We essentially have three irq controllers, CPU, system, and gpio. - * - * CPU irq controller is taken care by arch/mips/kernel/irq_cpu.c and - * CONFIG_IRQ_CPU config option. - * - * We here provide sys_irq and gpio_irq controller code. - */ - -static int sys_irq_base; -static int gpio_irq_base; - -/* ---------------------- sys irq ------------------------ */ -static void -sys_irq_enable(unsigned int irq) -{ - irq -= sys_irq_base; - if (irq < 16) { - *VR4181_MSYSINT1REG |= (u16)(1 << irq); - } else { - irq -= 16; - *VR4181_MSYSINT2REG |= (u16)(1 << irq); - } -} - -static void -sys_irq_disable(unsigned int irq) -{ - irq -= sys_irq_base; - if (irq < 16) { - *VR4181_MSYSINT1REG &= ~((u16)(1 << irq)); - } else { - irq -= 16; - *VR4181_MSYSINT2REG &= ~((u16)(1 << irq)); - } - -} - -static unsigned int -sys_irq_startup(unsigned int irq) -{ - sys_irq_enable(irq); - return 0; -} - -#define sys_irq_shutdown sys_irq_disable -#define sys_irq_ack sys_irq_disable - -static void -sys_irq_end(unsigned int irq) -{ - if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - sys_irq_enable(irq); -} - -static hw_irq_controller sys_irq_controller = { - "vr4181_sys_irq", - sys_irq_startup, - sys_irq_shutdown, - sys_irq_enable, - sys_irq_disable, - sys_irq_ack, - sys_irq_end, - NULL /* no affinity stuff for UP */ -}; - -/* ---------------------- gpio irq ------------------------ */ -/* gpio irq lines use reverse logic */ -static void -gpio_irq_enable(unsigned int irq) -{ - irq -= gpio_irq_base; - *VR4181_GPINTMSK &= ~((u16)(1 << irq)); -} - -static void -gpio_irq_disable(unsigned int irq) -{ - irq -= gpio_irq_base; - *VR4181_GPINTMSK |= (u16)(1 << irq); -} - -static unsigned int -gpio_irq_startup(unsigned int irq) -{ - gpio_irq_enable(irq); - - irq -= gpio_irq_base; - *VR4181_GPINTEN |= (u16)(1 << irq ); - - return 0; -} - -static void -gpio_irq_shutdown(unsigned int irq) -{ - gpio_irq_disable(irq); - - irq -= gpio_irq_base; - *VR4181_GPINTEN &= ~((u16)(1 << irq )); -} - -static void -gpio_irq_ack(unsigned int irq) -{ - u16 irqtype; - u16 irqshift; - - gpio_irq_disable(irq); - - /* we clear interrupt if it is edge triggered */ - irq -= gpio_irq_base; - if (irq < 8) { - irqtype = *VR4181_GPINTTYPL; - irqshift = 2 << (irq*2); - } else { - irqtype = *VR4181_GPINTTYPH; - irqshift = 2 << ((irq-8)*2); - } - if ( ! (irqtype & irqshift) ) { - *VR4181_GPINTSTAT = (u16) (1 << irq); - } -} - -static void -gpio_irq_end(unsigned int irq) -{ - if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - gpio_irq_enable(irq); -} - -static hw_irq_controller gpio_irq_controller = { - "vr4181_gpio_irq", - gpio_irq_startup, - gpio_irq_shutdown, - gpio_irq_enable, - gpio_irq_disable, - gpio_irq_ack, - gpio_irq_end, - NULL /* no affinity stuff for UP */ -}; - -/* --------------------- IRQ init stuff ---------------------- */ - -extern asmlinkage void vr4181_handle_irq(void); -extern void breakpoint(void); -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); -extern void mips_cpu_irq_init(u32 irq_base); - -static struct irqaction cascade = - { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL }; -static struct irqaction reserved = - { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL }; - -void __init arch_init_irq(void) -{ - int i; - - set_except_vector(0, vr4181_handle_irq); - - /* init CPU irqs */ - mips_cpu_irq_init(VR4181_CPU_IRQ_BASE); - - /* init sys irqs */ - sys_irq_base = VR4181_SYS_IRQ_BASE; - for (i=sys_irq_base; i < sys_irq_base + VR4181_NUM_SYS_IRQ; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].handler = &sys_irq_controller; - } - - /* init gpio irqs */ - gpio_irq_base = VR4181_GPIO_IRQ_BASE; - for (i=gpio_irq_base; i < gpio_irq_base + VR4181_NUM_GPIO_IRQ; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].handler = &gpio_irq_controller; - } - - /* Default all ICU IRQs to off ... */ - *VR4181_MSYSINT1REG = 0; - *VR4181_MSYSINT2REG = 0; - - /* We initialize the level 2 ICU registers to all bits disabled. */ - *VR4181_MPIUINTREG = 0; - *VR4181_MAIUINTREG = 0; - *VR4181_MKIUINTREG = 0; - - /* disable all GPIO intrs */ - *VR4181_GPINTMSK = 0xffff; - - /* vector handler. What these do is register the IRQ as non-sharable */ - setup_irq(VR4181_IRQ_INT0, &cascade); - setup_irq(VR4181_IRQ_GIU, &cascade); - - /* - * RTC interrupts are interesting. They have two destinations. - * One is at sys irq controller, and the other is at CPU IP3 and IP4. - * RTC timer is used as system timer. - * We enable them here, but timer routine will register later - * with CPU IP3/IP4. - */ - setup_irq(VR4181_IRQ_RTCL1, &reserved); - setup_irq(VR4181_IRQ_RTCL2, &reserved); -} diff --git a/arch/mips/vr4181/common/serial.c b/arch/mips/vr4181/common/serial.c deleted file mode 100644 index 3f62c62b107f..000000000000 --- a/arch/mips/vr4181/common/serial.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/vr4181/common/serial.c - * initialize serial port on vr4181. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* - * [jsun, 010925] - * You need to make sure rs_table has at least one element in - * drivers/char/serial.c file. There is no good way to do it right - * now. A workaround is to include CONFIG_SERIAL_MANY_PORTS in your - * configure file, which would gives you 64 ports and wastes 11K ram. - */ - -#include -#include -#include -#include - -#include - -void __init vr4181_init_serial(void) -{ - struct serial_struct s; - - /* turn on UART clock */ - *VR4181_CMUCLKMSK |= VR4181_CMUCLKMSK_MSKSIU; - - /* clear memory */ - memset(&s, 0, sizeof(s)); - - s.line = 0; /* we set the first one */ - s.baud_base = 1152000; - s.irq = VR4181_IRQ_SIU; - s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; /* STD_COM_FLAGS */ - s.iomem_base = (u8*)VR4181_SIURB; - s.iomem_reg_shift = 0; - s.io_type = SERIAL_IO_MEM; - if (early_serial_setup(&s) != 0) { - panic("vr4181_init_serial() failed!"); - } -} - diff --git a/arch/mips/vr4181/common/time.c b/arch/mips/vr4181/common/time.c deleted file mode 100644 index 17814076b6f4..000000000000 --- a/arch/mips/vr4181/common/time.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * rtc and time ops for vr4181. Part of code is drived from - * linux-vr, originally written by Bradley D. LaRonde & Michael Klar. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include -#include /* for HZ */ -#include -#include - -#include -#include - -#include - -#define COUNTS_PER_JIFFY ((32768 + HZ/2) / HZ) - -/* - * RTC ops - */ - -DEFINE_SPINLOCK(rtc_lock); - -/* per VR41xx docs, bad data can be read if between 2 counts */ -static inline unsigned short -read_time_reg(volatile unsigned short *reg) -{ - unsigned short value; - do { - value = *reg; - barrier(); - } while (value != *reg); - return value; -} - -static unsigned long -vr4181_rtc_get_time(void) -{ - unsigned short regh, regm, regl; - - // why this crazy order, you ask? to guarantee that neither m - // nor l wrap before all 3 read - do { - regm = read_time_reg(VR4181_ETIMEMREG); - barrier(); - regh = read_time_reg(VR4181_ETIMEHREG); - barrier(); - regl = read_time_reg(VR4181_ETIMELREG); - } while (regm != read_time_reg(VR4181_ETIMEMREG)); - return ((regh << 17) | (regm << 1) | (regl >> 15)); -} - -static int -vr4181_rtc_set_time(unsigned long timeval) -{ - unsigned short intreg; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - intreg = *VR4181_RTCINTREG & 0x05; - barrier(); - *VR4181_ETIMELREG = timeval << 15; - *VR4181_ETIMEMREG = timeval >> 1; - *VR4181_ETIMEHREG = timeval >> 17; - barrier(); - // assume that any ints that just triggered are invalid, since the - // time value is written non-atomically in 3 separate regs - *VR4181_RTCINTREG = 0x05 ^ intreg; - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - - -/* - * timer interrupt routine (wrapper) - * - * we need our own interrupt routine because we need to clear - * RTC1 interrupt. - */ -static void -vr4181_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - /* Clear the interrupt. */ - *VR4181_RTCINTREG = 0x2; - - /* call the generic one */ - timer_interrupt(irq, dev_id, regs); -} - - -/* - * vr4181_time_init: - * - * We pick the following choices: - * . we use elapsed timer as the RTC. We set some reasonable init data since - * it does not persist across reset - * . we use RTC1 as the system timer interrupt source. - * . we use CPU counter for fast_gettimeoffset and we calivrate the cpu - * frequency. In other words, we use calibrate_div64_gettimeoffset(). - * . we use our own timer interrupt routine which clears the interrupt - * and then calls the generic high-level timer interrupt routine. - * - */ - -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); - -static void -vr4181_timer_setup(struct irqaction *irq) -{ - /* over-write the handler to be our own one */ - irq->handler = vr4181_timer_interrupt; - - /* sets up the frequency */ - *VR4181_RTCL1LREG = COUNTS_PER_JIFFY; - *VR4181_RTCL1HREG = 0; - - /* and ack any pending ints */ - *VR4181_RTCINTREG = 0x2; - - /* setup irqaction */ - setup_irq(VR4181_IRQ_INT1, irq); - -} - -void -vr4181_init_time(void) -{ - /* setup hookup functions */ - rtc_get_time = vr4181_rtc_get_time; - rtc_set_time = vr4181_rtc_set_time; - - board_timer_setup = vr4181_timer_setup; -} - diff --git a/arch/mips/vr4181/osprey/Makefile b/arch/mips/vr4181/osprey/Makefile deleted file mode 100644 index 34be05790883..000000000000 --- a/arch/mips/vr4181/osprey/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Makefile for common code of NEC Osprey board -# - -obj-y := setup.o prom.o reset.o - -obj-$(CONFIG_KGDB) += dbg_io.o diff --git a/arch/mips/vr4181/osprey/dbg_io.c b/arch/mips/vr4181/osprey/dbg_io.c deleted file mode 100644 index 5e8a84072d5b..000000000000 --- a/arch/mips/vr4181/osprey/dbg_io.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * kgdb io functions for osprey. We use the serial port on debug board. - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* ======================= CONFIG ======================== */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE 0xb7fffff0 -#define MAX_BAUD 115200 - -/* distance in bytes between two serial registers */ -#define REG_OFFSET 1 - -/* - * 0 - kgdb does serial init - * 1 - kgdb skip serial init - */ -static int remoteDebugInitialized = 1; - -/* - * the default baud rate *if* kgdb does serial init - */ -#define BAUD_DEFAULT UART16550_BAUD_38400 - -/* ======================= END OF CONFIG ======================== */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up buad rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(BAUD_DEFAULT, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(BAUD_DEFAULT, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} diff --git a/arch/mips/vr4181/osprey/prom.c b/arch/mips/vr4181/osprey/prom.c deleted file mode 100644 index af0d14561619..000000000000 --- a/arch/mips/vr4181/osprey/prom.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * arch/mips/vr4181/osprey/prom.c - * prom code for osprey. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include -#include -#include -#include -#include - -const char *get_system_type(void) -{ - return "NEC_Vr41xx Osprey"; -} - -/* - * [jsun] right now we assume it is the nec debug monitor, which does - * not pass any arguments. - */ -void __init prom_init(void) -{ - // cmdline is now set in default config - // strcpy(arcs_cmdline, "ip=bootp "); - // strcat(arcs_cmdline, "ether=46,0x03fe0300,eth0 "); - // strcpy(arcs_cmdline, "ether=0,0x0300,eth0 " - // strcat(arcs_cmdline, "video=vr4181fb:xres:240,yres:320,bpp:8 "); - - mips_machgroup = MACH_GROUP_NEC_VR41XX; - mips_machtype = MACH_NEC_OSPREY; - - /* 16MB fixed */ - add_memory_region(0, 16 << 20, BOOT_MEM_RAM); -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} diff --git a/arch/mips/vr4181/osprey/reset.c b/arch/mips/vr4181/osprey/reset.c deleted file mode 100644 index 036ae83d89d6..000000000000 --- a/arch/mips/vr4181/osprey/reset.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 2001 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - */ -#include -#include -#include -#include -#include -#include -#include - -void nec_osprey_restart(char *command) -{ - set_c0_status(ST0_ERL); - change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); - flush_cache_all(); - write_c0_wired(0); - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); -} - -void nec_osprey_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void nec_osprey_power_off(void) -{ - nec_osprey_halt(); -} diff --git a/arch/mips/vr4181/osprey/setup.c b/arch/mips/vr4181/osprey/setup.c deleted file mode 100644 index 2ff7140e7ed7..000000000000 --- a/arch/mips/vr4181/osprey/setup.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * linux/arch/mips/vr4181/setup.c - * - * VR41xx setup routines - * - * Copyright (C) 1999 Bradley D. LaRonde - * Copyright (C) 1999, 2000 Michael Klar - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ - -#include -#include -#include -#include -#include -#include - - -extern void nec_osprey_restart(char* c); -extern void nec_osprey_halt(void); -extern void nec_osprey_power_off(void); - -extern void vr4181_init_serial(void); -extern void vr4181_init_time(void); - -static void __init nec_osprey_setup(void) -{ - set_io_port_base(VR4181_PORT_BASE); - isa_slot_offset = VR4181_ISAMEM_BASE; - - vr4181_init_serial(); - vr4181_init_time(); - - _machine_restart = nec_osprey_restart; - _machine_halt = nec_osprey_halt; - _machine_power_off = nec_osprey_power_off; - - /* setup resource limit */ - ioport_resource.end = 0xffffffff; - iomem_resource.end = 0xffffffff; - - /* [jsun] hack */ - /* - printk("[jsun] hack to change external ISA control register, %x -> %x\n", - (*VR4181_XISACTL), - (*VR4181_XISACTL) | 0x2); - *VR4181_XISACTL |= 0x2; - */ - - // *VR4181_GPHIBSTH = 0x2000; - // *VR4181_GPMD0REG = 0x00c0; - // *VR4181_GPINTEN = 1<<6; - - /* [jsun] I believe this will get the interrupt type right - * for the ether port. - */ - *VR4181_GPINTTYPL = 0x3000; -} - -early_initcall(nec_osprey_setup); diff --git a/include/asm-mips/vr4181/irq.h b/include/asm-mips/vr4181/irq.h deleted file mode 100644 index 4bf0ea970ed0..000000000000 --- a/include/asm-mips/vr4181/irq.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Macros for vr4181 IRQ numbers. - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* - * Strategy: - * - * Vr4181 has conceptually three levels of interrupt controllers: - * 1. the CPU itself with 8 intr level. - * 2. system interrupt controller, cascaded from int0 pin in CPU, 32 intrs - * 3. GPIO interrupts : forwarding external interrupts to sys intr controller - */ - -/* decide the irq block assignment */ -#define VR4181_NUM_CPU_IRQ 8 -#define VR4181_NUM_SYS_IRQ 32 -#define VR4181_NUM_GPIO_IRQ 16 - -#define VR4181_IRQ_BASE 0 - -#define VR4181_CPU_IRQ_BASE VR4181_IRQ_BASE -#define VR4181_SYS_IRQ_BASE (VR4181_CPU_IRQ_BASE + VR4181_NUM_CPU_IRQ) -#define VR4181_GPIO_IRQ_BASE (VR4181_SYS_IRQ_BASE + VR4181_NUM_SYS_IRQ) - -/* CPU interrupts */ - -/* - IP0 - Software interrupt - IP1 - Software interrupt - IP2 - All but battery, high speed modem, and real time clock - IP3 - RTC Long1 (system timer) - IP4 - RTC Long2 - IP5 - High Speed Modem (unused on VR4181) - IP6 - Unused - IP7 - Timer interrupt from CPO_COMPARE -*/ - -#define VR4181_IRQ_SW1 (VR4181_CPU_IRQ_BASE + 0) -#define VR4181_IRQ_SW2 (VR4181_CPU_IRQ_BASE + 1) -#define VR4181_IRQ_INT0 (VR4181_CPU_IRQ_BASE + 2) -#define VR4181_IRQ_INT1 (VR4181_CPU_IRQ_BASE + 3) -#define VR4181_IRQ_INT2 (VR4181_CPU_IRQ_BASE + 4) -#define VR4181_IRQ_INT3 (VR4181_CPU_IRQ_BASE + 5) -#define VR4181_IRQ_INT4 (VR4181_CPU_IRQ_BASE + 6) -#define VR4181_IRQ_TIMER (VR4181_CPU_IRQ_BASE + 7) - - -/* Cascaded from VR4181_IRQ_INT0 (ICU mapped interrupts) */ - -/* - IP2 - same as VR4181_IRQ_INT1 - IP8 - This is a cascade to GPIO IRQ's. Do not use. - IP16 - same as VR4181_IRQ_INT2 - IP18 - CompactFlash -*/ - -#define VR4181_IRQ_BATTERY (VR4181_SYS_IRQ_BASE + 0) -#define VR4181_IRQ_POWER (VR4181_SYS_IRQ_BASE + 1) -#define VR4181_IRQ_RTCL1 (VR4181_SYS_IRQ_BASE + 2) -#define VR4181_IRQ_ETIMER (VR4181_SYS_IRQ_BASE + 3) -#define VR4181_IRQ_RFU12 (VR4181_SYS_IRQ_BASE + 4) -#define VR4181_IRQ_PIU (VR4181_SYS_IRQ_BASE + 5) -#define VR4181_IRQ_AIU (VR4181_SYS_IRQ_BASE + 6) -#define VR4181_IRQ_KIU (VR4181_SYS_IRQ_BASE + 7) -#define VR4181_IRQ_GIU (VR4181_SYS_IRQ_BASE + 8) -#define VR4181_IRQ_SIU (VR4181_SYS_IRQ_BASE + 9) -#define VR4181_IRQ_RFU18 (VR4181_SYS_IRQ_BASE + 10) -#define VR4181_IRQ_SOFT (VR4181_SYS_IRQ_BASE + 11) -#define VR4181_IRQ_RFU20 (VR4181_SYS_IRQ_BASE + 12) -#define VR4181_IRQ_DOZEPIU (VR4181_SYS_IRQ_BASE + 13) -#define VR4181_IRQ_RFU22 (VR4181_SYS_IRQ_BASE + 14) -#define VR4181_IRQ_RFU23 (VR4181_SYS_IRQ_BASE + 15) -#define VR4181_IRQ_RTCL2 (VR4181_SYS_IRQ_BASE + 16) -#define VR4181_IRQ_LED (VR4181_SYS_IRQ_BASE + 17) -#define VR4181_IRQ_ECU (VR4181_SYS_IRQ_BASE + 18) -#define VR4181_IRQ_CSU (VR4181_SYS_IRQ_BASE + 19) -#define VR4181_IRQ_USB (VR4181_SYS_IRQ_BASE + 20) -#define VR4181_IRQ_DMA (VR4181_SYS_IRQ_BASE + 21) -#define VR4181_IRQ_LCD (VR4181_SYS_IRQ_BASE + 22) -#define VR4181_IRQ_RFU31 (VR4181_SYS_IRQ_BASE + 23) -#define VR4181_IRQ_RFU32 (VR4181_SYS_IRQ_BASE + 24) -#define VR4181_IRQ_RFU33 (VR4181_SYS_IRQ_BASE + 25) -#define VR4181_IRQ_RFU34 (VR4181_SYS_IRQ_BASE + 26) -#define VR4181_IRQ_RFU35 (VR4181_SYS_IRQ_BASE + 27) -#define VR4181_IRQ_RFU36 (VR4181_SYS_IRQ_BASE + 28) -#define VR4181_IRQ_RFU37 (VR4181_SYS_IRQ_BASE + 29) -#define VR4181_IRQ_RFU38 (VR4181_SYS_IRQ_BASE + 30) -#define VR4181_IRQ_RFU39 (VR4181_SYS_IRQ_BASE + 31) - -/* Cascaded from VR4181_IRQ_GIU */ -#define VR4181_IRQ_GPIO0 (VR4181_GPIO_IRQ_BASE + 0) -#define VR4181_IRQ_GPIO1 (VR4181_GPIO_IRQ_BASE + 1) -#define VR4181_IRQ_GPIO2 (VR4181_GPIO_IRQ_BASE + 2) -#define VR4181_IRQ_GPIO3 (VR4181_GPIO_IRQ_BASE + 3) -#define VR4181_IRQ_GPIO4 (VR4181_GPIO_IRQ_BASE + 4) -#define VR4181_IRQ_GPIO5 (VR4181_GPIO_IRQ_BASE + 5) -#define VR4181_IRQ_GPIO6 (VR4181_GPIO_IRQ_BASE + 6) -#define VR4181_IRQ_GPIO7 (VR4181_GPIO_IRQ_BASE + 7) -#define VR4181_IRQ_GPIO8 (VR4181_GPIO_IRQ_BASE + 8) -#define VR4181_IRQ_GPIO9 (VR4181_GPIO_IRQ_BASE + 9) -#define VR4181_IRQ_GPIO10 (VR4181_GPIO_IRQ_BASE + 10) -#define VR4181_IRQ_GPIO11 (VR4181_GPIO_IRQ_BASE + 11) -#define VR4181_IRQ_GPIO12 (VR4181_GPIO_IRQ_BASE + 12) -#define VR4181_IRQ_GPIO13 (VR4181_GPIO_IRQ_BASE + 13) -#define VR4181_IRQ_GPIO14 (VR4181_GPIO_IRQ_BASE + 14) -#define VR4181_IRQ_GPIO15 (VR4181_GPIO_IRQ_BASE + 15) - - -// Alternative to above GPIO IRQ defines -#define VR4181_IRQ_GPIO(pin) ((VR4181_IRQ_GPIO0) + (pin)) - -#define VR4181_IRQ_MAX (VR4181_IRQ_BASE + VR4181_NUM_CPU_IRQ + \ - VR4181_NUM_SYS_IRQ + VR4181_NUM_GPIO_IRQ) diff --git a/include/asm-mips/vr4181/vr4181.h b/include/asm-mips/vr4181/vr4181.h deleted file mode 100644 index 5c5d60741515..000000000000 --- a/include/asm-mips/vr4181/vr4181.h +++ /dev/null @@ -1,413 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999 by Michael Klar - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - */ -#ifndef __ASM_VR4181_VR4181_H -#define __ASM_VR4181_VR4181_H - -#include - -#include - -#ifndef __ASSEMBLY__ -#define __preg8 (volatile unsigned char*) -#define __preg16 (volatile unsigned short*) -#define __preg32 (volatile unsigned int*) -#else -#define __preg8 -#define __preg16 -#define __preg32 -#endif - -// Embedded CPU peripheral registers -// Note that many of the registers have different physical address for VR4181 - -// Bus Control Unit (BCU) -#define VR4181_BCUCNTREG1 __preg16(KSEG1 + 0x0A000000) /* BCU control register 1 (R/W) */ -#define VR4181_CMUCLKMSK __preg16(KSEG1 + 0x0A000004) /* Clock mask register (R/W) */ -#define VR4181_CMUCLKMSK_MSKCSUPCLK 0x0040 -#define VR4181_CMUCLKMSK_MSKAIUPCLK 0x0020 -#define VR4181_CMUCLKMSK_MSKPIUPCLK 0x0010 -#define VR4181_CMUCLKMSK_MSKADUPCLK 0x0008 -#define VR4181_CMUCLKMSK_MSKSIU18M 0x0004 -#define VR4181_CMUCLKMSK_MSKADU18M 0x0002 -#define VR4181_CMUCLKMSK_MSKUSB 0x0001 -#define VR4181_CMUCLKMSK_MSKSIU VR4181_CMUCLKMSK_MSKSIU18M -#define VR4181_BCUSPEEDREG __preg16(KSEG1 + 0x0A00000C) /* BCU access time parameter (R/W) */ -#define VR4181_BCURFCNTREG __preg16(KSEG1 + 0x0A000010) /* BCU refresh control register (R/W) */ -#define VR4181_REVIDREG __preg16(KSEG1 + 0x0A000014) /* Revision ID register (R) */ -#define VR4181_CLKSPEEDREG __preg16(KSEG1 + 0x0A000018) /* Clock speed register (R) */ -#define VR4181_EDOMCYTREG __preg16(KSEG1 + 0x0A000300) /* Memory cycle timing register (R/W) */ -#define VR4181_MEMCFG_REG __preg16(KSEG1 + 0x0A000304) /* Memory configuration register (R/W) */ -#define VR4181_MODE_REG __preg16(KSEG1 + 0x0A000308) /* SDRAM mode register (R/W) */ -#define VR4181_SDTIMINGREG __preg16(KSEG1 + 0x0A00030C) /* SDRAM timing register (R/W) */ - -// DMA Control Unit (DCU) -#define VR4181_MICDEST1REG1 __preg16(KSEG1 + 0x0A000020) /* Microphone destination 1 address register 1 (R/W) */ -#define VR4181_MICDEST1REG2 __preg16(KSEG1 + 0x0A000022) /* Microphone destination 1 address register 2 (R/W) */ -#define VR4181_MICDEST2REG1 __preg16(KSEG1 + 0x0A000024) /* Microphone destination 2 address register 1 (R/W) */ -#define VR4181_MICDEST2REG2 __preg16(KSEG1 + 0x0A000026) /* Microphone destination 2 address register 2 (R/W) */ -#define VR4181_SPKRRC1REG1 __preg16(KSEG1 + 0x0A000028) /* Speaker Source 1 address register 1 (R/W) */ -#define VR4181_SPKRRC1REG2 __preg16(KSEG1 + 0x0A00002A) /* Speaker Source 1 address register 2 (R/W) */ -#define VR4181_SPKRRC2REG1 __preg16(KSEG1 + 0x0A00002C) /* Speaker Source 2 address register 1 (R/W) */ -#define VR4181_SPKRRC2REG2 __preg16(KSEG1 + 0x0A00002E) /* Speaker Source 2 address register 2 (R/W) */ -#define VR4181_DMARSTREG __preg16(KSEG1 + 0x0A000040) /* DMA Reset register (R/W) */ -#define VR4181_AIUDMAMSKREG __preg16(KSEG1 + 0x0A000046) /* Audio DMA mask register (R/W) */ -#define VR4181_USBDMAMSKREG __preg16(KSEG1 + 0x0A000600) /* USB DMA Mask register (R/W) */ -#define VR4181_USBRXS1AREG1 __preg16(KSEG1 + 0x0A000602) /* USB Rx source 1 address register 1 (R/W) */ -#define VR4181_USBRXS1AREG2 __preg16(KSEG1 + 0x0A000604) /* USB Rx source 1 address register 2 (R/W) */ -#define VR4181_USBRXS2AREG1 __preg16(KSEG1 + 0x0A000606) /* USB Rx source 2 address register 1 (R/W) */ -#define VR4181_USBRXS2AREG2 __preg16(KSEG1 + 0x0A000608) /* USB Rx source 2 address register 2 (R/W) */ -#define VR4181_USBTXS1AREG1 __preg16(KSEG1 + 0x0A00060A) /* USB Tx source 1 address register 1 (R/W) */ -#define VR4181_USBTXS1AREG2 __preg16(KSEG1 + 0x0A00060C) /* USB Tx source 1 address register 2 (R/W) */ -#define VR4181_USBTXS2AREG1 __preg16(KSEG1 + 0x0A00060E) /* USB Tx source 2 address register 1 (R/W) */ -#define VR4181_USBTXS2AREG2 __preg16(KSEG1 + 0x0A000610) /* USB Tx source 2 address register 2 (R/W) */ -#define VR4181_USBRXD1AREG1 __preg16(KSEG1 + 0x0A00062A) /* USB Rx destination 1 address register 1 (R/W) */ -#define VR4181_USBRXD1AREG2 __preg16(KSEG1 + 0x0A00062C) /* USB Rx destination 1 address register 2 (R/W) */ -#define VR4181_USBRXD2AREG1 __preg16(KSEG1 + 0x0A00062E) /* USB Rx destination 2 address register 1 (R/W) */ -#define VR4181_USBRXD2AREG2 __preg16(KSEG1 + 0x0A000630) /* USB Rx destination 2 address register 2 (R/W) */ -#define VR4181_USBTXD1AREG1 __preg16(KSEG1 + 0x0A000632) /* USB Tx destination 1 address register 1 (R/W) */ -#define VR4181_USBTXD1AREG2 __preg16(KSEG1 + 0x0A000634) /* USB Tx destination 1 address register 2 (R/W) */ -#define VR4181_USBTXD2AREG1 __preg16(KSEG1 + 0x0A000636) /* USB Tx destination 2 address register 1 (R/W) */ -#define VR4181_USBTXD2AREG2 __preg16(KSEG1 + 0x0A000638) /* USB Tx destination 2 address register 2 (R/W) */ -#define VR4181_RxRCLENREG __preg16(KSEG1 + 0x0A000652) /* USB Rx record length register (R/W) */ -#define VR4181_TxRCLENREG __preg16(KSEG1 + 0x0A000654) /* USB Tx record length register (R/W) */ -#define VR4181_MICRCLENREG __preg16(KSEG1 + 0x0A000658) /* Microphone record length register (R/W) */ -#define VR4181_SPKRCLENREG __preg16(KSEG1 + 0x0A00065A) /* Speaker record length register (R/W) */ -#define VR4181_USBCFGREG __preg16(KSEG1 + 0x0A00065C) /* USB configuration register (R/W) */ -#define VR4181_MICDMACFGREG __preg16(KSEG1 + 0x0A00065E) /* Microphone DMA configuration register (R/W) */ -#define VR4181_SPKDMACFGREG __preg16(KSEG1 + 0x0A000660) /* Speaker DMA configuration register (R/W) */ -#define VR4181_DMAITRQREG __preg16(KSEG1 + 0x0A000662) /* DMA interrupt request register (R/W) */ -#define VR4181_DMACLTREG __preg16(KSEG1 + 0x0A000664) /* DMA control register (R/W) */ -#define VR4181_DMAITMKREG __preg16(KSEG1 + 0x0A000666) /* DMA interrupt mask register (R/W) */ - -// ISA Bridge -#define VR4181_ISABRGCTL __preg16(KSEG1 + 0x0B0002C0) /* ISA Bridge Control Register (R/W) */ -#define VR4181_ISABRGSTS __preg16(KSEG1 + 0x0B0002C2) /* ISA Bridge Status Register (R/W) */ -#define VR4181_XISACTL __preg16(KSEG1 + 0x0B0002C4) /* External ISA Control Register (R/W) */ - -// Clocked Serial Interface (CSI) -#define VR4181_CSIMODE __preg16(KSEG1 + 0x0B000900) /* CSI Mode Register (R/W) */ -#define VR4181_CSIRXDATA __preg16(KSEG1 + 0x0B000902) /* CSI Receive Data Register (R) */ -#define VR4181_CSITXDATA __preg16(KSEG1 + 0x0B000904) /* CSI Transmit Data Register (R/W) */ -#define VR4181_CSILSTAT __preg16(KSEG1 + 0x0B000906) /* CSI Line Status Register (R/W) */ -#define VR4181_CSIINTMSK __preg16(KSEG1 + 0x0B000908) /* CSI Interrupt Mask Register (R/W) */ -#define VR4181_CSIINTSTAT __preg16(KSEG1 + 0x0B00090a) /* CSI Interrupt Status Register (R/W) */ -#define VR4181_CSITXBLEN __preg16(KSEG1 + 0x0B00090c) /* CSI Transmit Burst Length Register (R/W) */ -#define VR4181_CSIRXBLEN __preg16(KSEG1 + 0x0B00090e) /* CSI Receive Burst Length Register (R/W) */ - -// Interrupt Control Unit (ICU) -#define VR4181_SYSINT1REG __preg16(KSEG1 + 0x0A000080) /* Level 1 System interrupt register 1 (R) */ -#define VR4181_MSYSINT1REG __preg16(KSEG1 + 0x0A00008C) /* Level 1 mask system interrupt register 1 (R/W) */ -#define VR4181_NMIREG __preg16(KSEG1 + 0x0A000098) /* NMI register (R/W) */ -#define VR4181_SOFTINTREG __preg16(KSEG1 + 0x0A00009A) /* Software interrupt register (R/W) */ -#define VR4181_SYSINT2REG __preg16(KSEG1 + 0x0A000200) /* Level 1 System interrupt register 2 (R) */ -#define VR4181_MSYSINT2REG __preg16(KSEG1 + 0x0A000206) /* Level 1 mask system interrupt register 2 (R/W) */ -#define VR4181_PIUINTREGro __preg16(KSEG1 + 0x0B000082) /* Level 2 PIU interrupt register (R) */ -#define VR4181_AIUINTREG __preg16(KSEG1 + 0x0B000084) /* Level 2 AIU interrupt register (R) */ -#define VR4181_MPIUINTREG __preg16(KSEG1 + 0x0B00008E) /* Level 2 mask PIU interrupt register (R/W) */ -#define VR4181_MAIUINTREG __preg16(KSEG1 + 0x0B000090) /* Level 2 mask AIU interrupt register (R/W) */ -#define VR4181_MKIUINTREG __preg16(KSEG1 + 0x0B000092) /* Level 2 mask KIU interrupt register (R/W) */ -#define VR4181_KIUINTREG __preg16(KSEG1 + 0x0B000198) /* Level 2 KIU interrupt register (R) */ - -// Power Management Unit (PMU) -#define VR4181_PMUINTREG __preg16(KSEG1 + 0x0B0000A0) /* PMU Status Register (R/W) */ -#define VR4181_PMUINT_POWERSW 0x1 /* Power switch */ -#define VR4181_PMUINT_BATT 0x2 /* Low batt during normal operation */ -#define VR4181_PMUINT_DEADMAN 0x4 /* Deadman's switch */ -#define VR4181_PMUINT_RESET 0x8 /* Reset switch */ -#define VR4181_PMUINT_RTCRESET 0x10 /* RTC Reset */ -#define VR4181_PMUINT_TIMEOUT 0x20 /* HAL Timer Reset */ -#define VR4181_PMUINT_BATTLOW 0x100 /* Battery low */ -#define VR4181_PMUINT_RTC 0x200 /* RTC Alarm */ -#define VR4181_PMUINT_DCD 0x400 /* DCD# */ -#define VR4181_PMUINT_GPIO0 0x1000 /* GPIO0 */ -#define VR4181_PMUINT_GPIO1 0x2000 /* GPIO1 */ -#define VR4181_PMUINT_GPIO2 0x4000 /* GPIO2 */ -#define VR4181_PMUINT_GPIO3 0x8000 /* GPIO3 */ - -#define VR4181_PMUCNTREG __preg16(KSEG1 + 0x0B0000A2) /* PMU Control Register (R/W) */ -#define VR4181_PMUWAITREG __preg16(KSEG1 + 0x0B0000A8) /* PMU Wait Counter Register (R/W) */ -#define VR4181_PMUDIVREG __preg16(KSEG1 + 0x0B0000AC) /* PMU Divide Mode Register (R/W) */ -#define VR4181_DRAMHIBCTL __preg16(KSEG1 + 0x0B0000B2) /* DRAM Hibernate Control Register (R/W) */ - -// Real Time Clock Unit (RTC) -#define VR4181_ETIMELREG __preg16(KSEG1 + 0x0B0000C0) /* Elapsed Time L Register (R/W) */ -#define VR4181_ETIMEMREG __preg16(KSEG1 + 0x0B0000C2) /* Elapsed Time M Register (R/W) */ -#define VR4181_ETIMEHREG __preg16(KSEG1 + 0x0B0000C4) /* Elapsed Time H Register (R/W) */ -#define VR4181_ECMPLREG __preg16(KSEG1 + 0x0B0000C8) /* Elapsed Compare L Register (R/W) */ -#define VR4181_ECMPMREG __preg16(KSEG1 + 0x0B0000CA) /* Elapsed Compare M Register (R/W) */ -#define VR4181_ECMPHREG __preg16(KSEG1 + 0x0B0000CC) /* Elapsed Compare H Register (R/W) */ -#define VR4181_RTCL1LREG __preg16(KSEG1 + 0x0B0000D0) /* RTC Long 1 L Register (R/W) */ -#define VR4181_RTCL1HREG __preg16(KSEG1 + 0x0B0000D2) /* RTC Long 1 H Register (R/W) */ -#define VR4181_RTCL1CNTLREG __preg16(KSEG1 + 0x0B0000D4) /* RTC Long 1 Count L Register (R) */ -#define VR4181_RTCL1CNTHREG __preg16(KSEG1 + 0x0B0000D6) /* RTC Long 1 Count H Register (R) */ -#define VR4181_RTCL2LREG __preg16(KSEG1 + 0x0B0000D8) /* RTC Long 2 L Register (R/W) */ -#define VR4181_RTCL2HREG __preg16(KSEG1 + 0x0B0000DA) /* RTC Long 2 H Register (R/W) */ -#define VR4181_RTCL2CNTLREG __preg16(KSEG1 + 0x0B0000DC) /* RTC Long 2 Count L Register (R) */ -#define VR4181_RTCL2CNTHREG __preg16(KSEG1 + 0x0B0000DE) /* RTC Long 2 Count H Register (R) */ -#define VR4181_RTCINTREG __preg16(KSEG1 + 0x0B0001DE) /* RTC Interrupt Register (R/W) */ - -// Deadman's Switch Unit (DSU) -#define VR4181_DSUCNTREG __preg16(KSEG1 + 0x0B0000E0) /* DSU Control Register (R/W) */ -#define VR4181_DSUSETREG __preg16(KSEG1 + 0x0B0000E2) /* DSU Dead Time Set Register (R/W) */ -#define VR4181_DSUCLRREG __preg16(KSEG1 + 0x0B0000E4) /* DSU Clear Register (W) */ -#define VR4181_DSUTIMREG __preg16(KSEG1 + 0x0B0000E6) /* DSU Elapsed Time Register (R/W) */ - -// General Purpose I/O Unit (GIU) -#define VR4181_GPMD0REG __preg16(KSEG1 + 0x0B000300) /* GPIO Mode 0 Register (R/W) */ -#define VR4181_GPMD1REG __preg16(KSEG1 + 0x0B000302) /* GPIO Mode 1 Register (R/W) */ -#define VR4181_GPMD2REG __preg16(KSEG1 + 0x0B000304) /* GPIO Mode 2 Register (R/W) */ -#define VR4181_GPMD3REG __preg16(KSEG1 + 0x0B000306) /* GPIO Mode 3 Register (R/W) */ -#define VR4181_GPDATHREG __preg16(KSEG1 + 0x0B000308) /* GPIO Data High Register (R/W) */ -#define VR4181_GPDATHREG_GPIO16 0x0001 -#define VR4181_GPDATHREG_GPIO17 0x0002 -#define VR4181_GPDATHREG_GPIO18 0x0004 -#define VR4181_GPDATHREG_GPIO19 0x0008 -#define VR4181_GPDATHREG_GPIO20 0x0010 -#define VR4181_GPDATHREG_GPIO21 0x0020 -#define VR4181_GPDATHREG_GPIO22 0x0040 -#define VR4181_GPDATHREG_GPIO23 0x0080 -#define VR4181_GPDATHREG_GPIO24 0x0100 -#define VR4181_GPDATHREG_GPIO25 0x0200 -#define VR4181_GPDATHREG_GPIO26 0x0400 -#define VR4181_GPDATHREG_GPIO27 0x0800 -#define VR4181_GPDATHREG_GPIO28 0x1000 -#define VR4181_GPDATHREG_GPIO29 0x2000 -#define VR4181_GPDATHREG_GPIO30 0x4000 -#define VR4181_GPDATHREG_GPIO31 0x8000 -#define VR4181_GPDATLREG __preg16(KSEG1 + 0x0B00030A) /* GPIO Data Low Register (R/W) */ -#define VR4181_GPDATLREG_GPIO0 0x0001 -#define VR4181_GPDATLREG_GPIO1 0x0002 -#define VR4181_GPDATLREG_GPIO2 0x0004 -#define VR4181_GPDATLREG_GPIO3 0x0008 -#define VR4181_GPDATLREG_GPIO4 0x0010 -#define VR4181_GPDATLREG_GPIO5 0x0020 -#define VR4181_GPDATLREG_GPIO6 0x0040 -#define VR4181_GPDATLREG_GPIO7 0x0080 -#define VR4181_GPDATLREG_GPIO8 0x0100 -#define VR4181_GPDATLREG_GPIO9 0x0200 -#define VR4181_GPDATLREG_GPIO10 0x0400 -#define VR4181_GPDATLREG_GPIO11 0x0800 -#define VR4181_GPDATLREG_GPIO12 0x1000 -#define VR4181_GPDATLREG_GPIO13 0x2000 -#define VR4181_GPDATLREG_GPIO14 0x4000 -#define VR4181_GPDATLREG_GPIO15 0x8000 -#define VR4181_GPINTEN __preg16(KSEG1 + 0x0B00030C) /* GPIO Interrupt Enable Register (R/W) */ -#define VR4181_GPINTMSK __preg16(KSEG1 + 0x0B00030E) /* GPIO Interrupt Mask Register (R/W) */ -#define VR4181_GPINTTYPH __preg16(KSEG1 + 0x0B000310) /* GPIO Interrupt Type High Register (R/W) */ -#define VR4181_GPINTTYPL __preg16(KSEG1 + 0x0B000312) /* GPIO Interrupt Type Low Register (R/W) */ -#define VR4181_GPINTSTAT __preg16(KSEG1 + 0x0B000314) /* GPIO Interrupt Status Register (R/W) */ -#define VR4181_GPHIBSTH __preg16(KSEG1 + 0x0B000316) /* GPIO Hibernate Pin State High Register (R/W) */ -#define VR4181_GPHIBSTL __preg16(KSEG1 + 0x0B000318) /* GPIO Hibernate Pin State Low Register (R/W) */ -#define VR4181_GPSICTL __preg16(KSEG1 + 0x0B00031A) /* GPIO Serial Interface Control Register (R/W) */ -#define VR4181_KEYEN __preg16(KSEG1 + 0x0B00031C) /* Keyboard Scan Pin Enable Register (R/W) */ -#define VR4181_PCS0STRA __preg16(KSEG1 + 0x0B000320) /* Programmable Chip Select [0] Start Address Register (R/W) */ -#define VR4181_PCS0STPA __preg16(KSEG1 + 0x0B000322) /* Programmable Chip Select [0] Stop Address Register (R/W) */ -#define VR4181_PCS0HIA __preg16(KSEG1 + 0x0B000324) /* Programmable Chip Select [0] High Address Register (R/W) */ -#define VR4181_PCS1STRA __preg16(KSEG1 + 0x0B000326) /* Programmable Chip Select [1] Start Address Register (R/W) */ -#define VR4181_PCS1STPA __preg16(KSEG1 + 0x0B000328) /* Programmable Chip Select [1] Stop Address Register (R/W) */ -#define VR4181_PCS1HIA __preg16(KSEG1 + 0x0B00032A) /* Programmable Chip Select [1] High Address Register (R/W) */ -#define VR4181_PCSMODE __preg16(KSEG1 + 0x0B00032C) /* Programmable Chip Select Mode Register (R/W) */ -#define VR4181_LCDGPMODE __preg16(KSEG1 + 0x0B00032E) /* LCD General Purpose Mode Register (R/W) */ -#define VR4181_MISCREG0 __preg16(KSEG1 + 0x0B000330) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG1 __preg16(KSEG1 + 0x0B000332) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG2 __preg16(KSEG1 + 0x0B000334) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG3 __preg16(KSEG1 + 0x0B000336) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG4 __preg16(KSEG1 + 0x0B000338) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG5 __preg16(KSEG1 + 0x0B00033A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG6 __preg16(KSEG1 + 0x0B00033C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG7 __preg16(KSEG1 + 0x0B00033D) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG8 __preg16(KSEG1 + 0x0B000340) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG9 __preg16(KSEG1 + 0x0B000342) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG10 __preg16(KSEG1 + 0x0B000344) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG11 __preg16(KSEG1 + 0x0B000346) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG12 __preg16(KSEG1 + 0x0B000348) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG13 __preg16(KSEG1 + 0x0B00034A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG14 __preg16(KSEG1 + 0x0B00034C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG15 __preg16(KSEG1 + 0x0B00034E) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_SECIRQMASKL VR4181_GPINTEN -// No SECIRQMASKH for VR4181 - -// Touch Panel Interface Unit (PIU) -#define VR4181_PIUCNTREG __preg16(KSEG1 + 0x0B000122) /* PIU Control register (R/W) */ -#define VR4181_PIUCNTREG_PIUSEQEN 0x0004 -#define VR4181_PIUCNTREG_PIUPWR 0x0002 -#define VR4181_PIUCNTREG_PADRST 0x0001 - -#define VR4181_PIUINTREG __preg16(KSEG1 + 0x0B000124) /* PIU Interrupt cause register (R/W) */ -#define VR4181_PIUINTREG_OVP 0x8000 -#define VR4181_PIUINTREG_PADCMD 0x0040 -#define VR4181_PIUINTREG_PADADP 0x0020 -#define VR4181_PIUINTREG_PADPAGE1 0x0010 -#define VR4181_PIUINTREG_PADPAGE0 0x0008 -#define VR4181_PIUINTREG_PADDLOST 0x0004 -#define VR4181_PIUINTREG_PENCHG 0x0001 - -#define VR4181_PIUSIVLREG __preg16(KSEG1 + 0x0B000126) /* PIU Data sampling interval register (R/W) */ -#define VR4181_PIUSTBLREG __preg16(KSEG1 + 0x0B000128) /* PIU A/D converter start delay register (R/W) */ -#define VR4181_PIUCMDREG __preg16(KSEG1 + 0x0B00012A) /* PIU A/D command register (R/W) */ -#define VR4181_PIUASCNREG __preg16(KSEG1 + 0x0B000130) /* PIU A/D port scan register (R/W) */ -#define VR4181_PIUAMSKREG __preg16(KSEG1 + 0x0B000132) /* PIU A/D scan mask register (R/W) */ -#define VR4181_PIUCIVLREG __preg16(KSEG1 + 0x0B00013E) /* PIU Check interval register (R) */ -#define VR4181_PIUPB00REG __preg16(KSEG1 + 0x0B0002A0) /* PIU Page 0 Buffer 0 register (R/W) */ -#define VR4181_PIUPB01REG __preg16(KSEG1 + 0x0B0002A2) /* PIU Page 0 Buffer 1 register (R/W) */ -#define VR4181_PIUPB02REG __preg16(KSEG1 + 0x0B0002A4) /* PIU Page 0 Buffer 2 register (R/W) */ -#define VR4181_PIUPB03REG __preg16(KSEG1 + 0x0B0002A6) /* PIU Page 0 Buffer 3 register (R/W) */ -#define VR4181_PIUPB10REG __preg16(KSEG1 + 0x0B0002A8) /* PIU Page 1 Buffer 0 register (R/W) */ -#define VR4181_PIUPB11REG __preg16(KSEG1 + 0x0B0002AA) /* PIU Page 1 Buffer 1 register (R/W) */ -#define VR4181_PIUPB12REG __preg16(KSEG1 + 0x0B0002AC) /* PIU Page 1 Buffer 2 register (R/W) */ -#define VR4181_PIUPB13REG __preg16(KSEG1 + 0x0B0002AE) /* PIU Page 1 Buffer 3 register (R/W) */ -#define VR4181_PIUAB0REG __preg16(KSEG1 + 0x0B0002B0) /* PIU A/D scan Buffer 0 register (R/W) */ -#define VR4181_PIUAB1REG __preg16(KSEG1 + 0x0B0002B2) /* PIU A/D scan Buffer 1 register (R/W) */ -#define VR4181_PIUAB2REG __preg16(KSEG1 + 0x0B0002B4) /* PIU A/D scan Buffer 2 register (R/W) */ -#define VR4181_PIUAB3REG __preg16(KSEG1 + 0x0B0002B6) /* PIU A/D scan Buffer 3 register (R/W) */ -#define VR4181_PIUPB04REG __preg16(KSEG1 + 0x0B0002BC) /* PIU Page 0 Buffer 4 register (R/W) */ -#define VR4181_PIUPB14REG __preg16(KSEG1 + 0x0B0002BE) /* PIU Page 1 Buffer 4 register (R/W) */ - -// Audio Interface Unit (AIU) -#define VR4181_SODATREG __preg16(KSEG1 + 0x0B000166) /* Speaker Output Data Register (R/W) */ -#define VR4181_SCNTREG __preg16(KSEG1 + 0x0B000168) /* Speaker Output Control Register (R/W) */ -#define VR4181_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Mike Input Data Register (R/W) */ -#define VR4181_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Mike Input Control Register (R/W) */ -#define VR4181_DVALIDREG __preg16(KSEG1 + 0x0B000178) /* Data Valid Register (R/W) */ -#define VR4181_SEQREG __preg16(KSEG1 + 0x0B00017A) /* Sequential Register (R/W) */ -#define VR4181_INTREG __preg16(KSEG1 + 0x0B00017C) /* Interrupt Register (R/W) */ -#define VR4181_SDMADATREG __preg16(KSEG1 + 0x0B000160) /* Speaker DMA Data Register (R/W) */ -#define VR4181_MDMADATREG __preg16(KSEG1 + 0x0B000162) /* Microphone DMA Data Register (R/W) */ -#define VR4181_DAVREF_SETUP __preg16(KSEG1 + 0x0B000164) /* DAC Vref setup register (R/W) */ -#define VR4181_SCNVC_END __preg16(KSEG1 + 0x0B00016E) /* Speaker sample rate control (R/W) */ -#define VR4181_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Microphone Input Data Register (R/W) */ -#define VR4181_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Microphone Input Control Register (R/W) */ -#define VR4181_MCNVC_END __preg16(KSEG1 + 0x0B00017E) /* Microphone sample rate control (R/W) */ - -// Keyboard Interface Unit (KIU) -#define VR4181_KIUDAT0 __preg16(KSEG1 + 0x0B000180) /* KIU Data0 Register (R/W) */ -#define VR4181_KIUDAT1 __preg16(KSEG1 + 0x0B000182) /* KIU Data1 Register (R/W) */ -#define VR4181_KIUDAT2 __preg16(KSEG1 + 0x0B000184) /* KIU Data2 Register (R/W) */ -#define VR4181_KIUDAT3 __preg16(KSEG1 + 0x0B000186) /* KIU Data3 Register (R/W) */ -#define VR4181_KIUDAT4 __preg16(KSEG1 + 0x0B000188) /* KIU Data4 Register (R/W) */ -#define VR4181_KIUDAT5 __preg16(KSEG1 + 0x0B00018A) /* KIU Data5 Register (R/W) */ -#define VR4181_KIUSCANREP __preg16(KSEG1 + 0x0B000190) /* KIU Scan/Repeat Register (R/W) */ -#define VR4181_KIUSCANREP_KEYEN 0x8000 -#define VR4181_KIUSCANREP_SCANSTP 0x0008 -#define VR4181_KIUSCANREP_SCANSTART 0x0004 -#define VR4181_KIUSCANREP_ATSTP 0x0002 -#define VR4181_KIUSCANREP_ATSCAN 0x0001 -#define VR4181_KIUSCANS __preg16(KSEG1 + 0x0B000192) /* KIU Scan Status Register (R) */ -#define VR4181_KIUWKS __preg16(KSEG1 + 0x0B000194) /* KIU Wait Keyscan Stable Register (R/W) */ -#define VR4181_KIUWKI __preg16(KSEG1 + 0x0B000196) /* KIU Wait Keyscan Interval Register (R/W) */ -#define VR4181_KIUINT __preg16(KSEG1 + 0x0B000198) /* KIU Interrupt Register (R/W) */ -#define VR4181_KIUINT_KDATLOST 0x0004 -#define VR4181_KIUINT_KDATRDY 0x0002 -#define VR4181_KIUINT_SCANINT 0x0001 -#define VR4181_KIUDAT6 __preg16(KSEG1 + 0x0B00018C) /* Scan Line 6 Key Data Register (R) */ -#define VR4181_KIUDAT7 __preg16(KSEG1 + 0x0B00018E) /* Scan Line 7 Key Data Register (R) */ - -// CompactFlash Controller -#define VR4181_PCCARDINDEX __preg8(KSEG1 + 0x0B0008E0) /* PC Card Controller Index Register */ -#define VR4181_PCCARDDATA __preg8(KSEG1 + 0x0B0008E1) /* PC Card Controller Data Register */ -#define VR4181_INTSTATREG __preg16(KSEG1 + 0x0B0008F8) /* Interrupt Status Register (R/W) */ -#define VR4181_INTMSKREG __preg16(KSEG1 + 0x0B0008FA) /* Interrupt Mask Register (R/W) */ -#define VR4181_CFG_REG_1 __preg16(KSEG1 + 0x0B0008FE) /* Configuration Register 1 */ - -// LED Control Unit (LED) -#define VR4181_LEDHTSREG __preg16(KSEG1 + 0x0B000240) /* LED H Time Set register (R/W) */ -#define VR4181_LEDLTSREG __preg16(KSEG1 + 0x0B000242) /* LED L Time Set register (R/W) */ -#define VR4181_LEDCNTREG __preg16(KSEG1 + 0x0B000248) /* LED Control register (R/W) */ -#define VR4181_LEDASTCREG __preg16(KSEG1 + 0x0B00024A) /* LED Auto Stop Time Count register (R/W) */ -#define VR4181_LEDINTREG __preg16(KSEG1 + 0x0B00024C) /* LED Interrupt register (R/W) */ - -// Serial Interface Unit (SIU / SIU1 and SIU2) -#define VR4181_SIURB __preg8(KSEG1 + 0x0C000010) /* Receiver Buffer Register (Read) DLAB = 0 (R) */ -#define VR4181_SIUTH __preg8(KSEG1 + 0x0C000010) /* Transmitter Holding Register (Write) DLAB = 0 (W) */ -#define VR4181_SIUDLL __preg8(KSEG1 + 0x0C000010) /* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */ -#define VR4181_SIUIE __preg8(KSEG1 + 0x0C000011) /* Interrupt Enable DLAB = 0 (R/W) */ -#define VR4181_SIUDLM __preg8(KSEG1 + 0x0C000011) /* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */ -#define VR4181_SIUIID __preg8(KSEG1 + 0x0C000012) /* Interrupt Identification Register (Read) (R) */ -#define VR4181_SIUFC __preg8(KSEG1 + 0x0C000012) /* FIFO Control Register (Write) (W) */ -#define VR4181_SIULC __preg8(KSEG1 + 0x0C000013) /* Line Control Register (R/W) */ -#define VR4181_SIUMC __preg8(KSEG1 + 0x0C000014) /* MODEM Control Register (R/W) */ -#define VR4181_SIULS __preg8(KSEG1 + 0x0C000015) /* Line Status Register (R/W) */ -#define VR4181_SIUMS __preg8(KSEG1 + 0x0C000016) /* MODEM Status Register (R/W) */ -#define VR4181_SIUSC __preg8(KSEG1 + 0x0C000017) /* Scratch Register (R/W) */ -#define VR4181_SIURESET __preg8(KSEG1 + 0x0C000019) /* SIU Reset Register (R/W) */ -#define VR4181_SIUACTMSK __preg8(KSEG1 + 0x0C00001C) /* SIU Activity Mask (R/W) */ -#define VR4181_SIUACTTMR __preg8(KSEG1 + 0x0C00001E) /* SIU Activity Timer (R/W) */ -#define VR4181_SIURB_2 __preg8(KSEG1 + 0x0C000000) /* Receive Buffer Register (Read) (R) */ -#define VR4181_SIUTH_2 __preg8(KSEG1 + 0x0C000000) /* Transmitter Holding Register (Write) (W) */ -#define VR4181_SIUDLL_2 __preg8(KSEG1 + 0x0C000000) /* Divisor Latch (Least Significant Byte) (R/W) */ -#define VR4181_SIUIE_2 __preg8(KSEG1 + 0x0C000001) /* Interrupt Enable (DLAB = 0) (R/W) */ -#define VR4181_SIUDLM_2 __preg8(KSEG1 + 0x0C000001) /* Divisor Latch (Most Significant Byte) (DLAB = 1) (R/W) */ -#define VR4181_SIUIID_2 __preg8(KSEG1 + 0x0C000002) /* Interrupt Identification Register (Read) (R) */ -#define VR4181_SIUFC_2 __preg8(KSEG1 + 0x0C000002) /* FIFO Control Register (Write) (W) */ -#define VR4181_SIULC_2 __preg8(KSEG1 + 0x0C000003) /* Line Control Register (R/W) */ -#define VR4181_SIUMC_2 __preg8(KSEG1 + 0x0C000004) /* Modem Control Register (R/W) */ -#define VR4181_SIULS_2 __preg8(KSEG1 + 0x0C000005) /* Line Status Register (R/W) */ -#define VR4181_SIUMS_2 __preg8(KSEG1 + 0x0C000006) /* Modem Status Register (R/W) */ -#define VR4181_SIUSC_2 __preg8(KSEG1 + 0x0C000007) /* Scratch Register (R/W) */ -#define VR4181_SIUIRSEL_2 __preg8(KSEG1 + 0x0C000008) /* SIU IrDA Selectot (R/W) */ -#define VR4181_SIURESET_2 __preg8(KSEG1 + 0x0C000009) /* SIU Reset Register (R/W) */ -#define VR4181_SIUCSEL_2 __preg8(KSEG1 + 0x0C00000A) /* IrDA Echo-back Control (R/W) */ -#define VR4181_SIUACTMSK_2 __preg8(KSEG1 + 0x0C00000C) /* SIU Activity Mask Register (R/W) */ -#define VR4181_SIUACTTMR_2 __preg8(KSEG1 + 0x0C00000E) /* SIU Activity Timer Register (R/W) */ - - -// USB Module -#define VR4181_USBINFIFO __preg16(KSEG1 + 0x0B000780) /* USB Bulk Input FIFO (Bulk In End Point) (W) */ -#define VR4181_USBOUTFIFO __preg16(KSEG1 + 0x0B000782) /* USB Bulk Output FIFO (Bulk Out End Point) (R) */ -#define VR4181_USBCTLFIFO __preg16(KSEG1 + 0x0B000784) /* USB Control FIFO (Control End Point) (W) */ -#define VR4181_USBSTAT __preg16(KSEG1 + 0x0B000786) /* Interrupt Status Register (R/W) */ -#define VR4181_USBINTMSK __preg16(KSEG1 + 0x0B000788) /* Interrupt Mask Register (R/W) */ -#define VR4181_USBCTLREG __preg16(KSEG1 + 0x0B00078A) /* Control Register (R/W) */ -#define VR4181_USBSTPREG __preg16(KSEG1 + 0x0B00078C) /* USB Transfer Stop Register (R/W) */ - -// LCD Controller -#define VR4181_HRTOTALREG __preg16(KSEG1 + 0x0A000400) /* Horizontal total Register (R/W) */ -#define VR4181_HRVISIBREG __preg16(KSEG1 + 0x0A000402) /* Horizontal Visible Register (R/W) */ -#define VR4181_LDCLKSTREG __preg16(KSEG1 + 0x0A000404) /* Load clock start Register (R/W) */ -#define VR4181_LDCLKNDREG __preg16(KSEG1 + 0x0A000406) /* Load clock end Register (R/W) */ -#define VR4181_VRTOTALREG __preg16(KSEG1 + 0x0A000408) /* Vertical Total Register (R/W) */ -#define VR4181_VRVISIBREG __preg16(KSEG1 + 0x0A00040A) /* Vertical Visible Register (R/W) */ -#define VR4181_FVSTARTREG __preg16(KSEG1 + 0x0A00040C) /* FLM vertical start Register (R/W) */ -#define VR4181_FVENDREG __preg16(KSEG1 + 0x0A00040E) /* FLM vertical end Register (R/W) */ -#define VR4181_LCDCTRLREG __preg16(KSEG1 + 0x0A000410) /* LCD control Register (R/W) */ -#define VR4181_LCDINRQREG __preg16(KSEG1 + 0x0A000412) /* LCD Interrupt request Register (R/W) */ -#define VR4181_LCDCFGREG0 __preg16(KSEG1 + 0x0A000414) /* LCD Configuration Register 0 (R/W) */ -#define VR4181_LCDCFGREG1 __preg16(KSEG1 + 0x0A000416) /* LCD Configuration Register 1 (R/W) */ -#define VR4181_FBSTAD1REG __preg16(KSEG1 + 0x0A000418) /* Frame Buffer Start Address 1 Register (R/W) */ -#define VR4181_FBSTAD2REG __preg16(KSEG1 + 0x0A00041A) /* Frame Buffer Start Address 2 Register (R/W) */ -#define VR4181_FBNDAD1REG __preg16(KSEG1 + 0x0A000420) /* Frame Buffer End Address 1 Register (R/W) */ -#define VR4181_FBNDAD2REG __preg16(KSEG1 + 0x0A000422) /* Frame Buffer End Address 2 register (R/W) */ -#define VR4181_FHSTARTREG __preg16(KSEG1 + 0x0A000424) /* FLM horizontal Start Register (R/W) */ -#define VR4181_FHENDREG __preg16(KSEG1 + 0x0A000426) /* FLM horizontal End Register (R/W) */ -#define VR4181_PWRCONREG1 __preg16(KSEG1 + 0x0A000430) /* Power Control register 1 (R/W) */ -#define VR4181_PWRCONREG2 __preg16(KSEG1 + 0x0A000432) /* Power Control register 2 (R/W) */ -#define VR4181_LCDIMSKREG __preg16(KSEG1 + 0x0A000434) /* LCD Interrupt Mask register (R/W) */ -#define VR4181_CPINDCTREG __preg16(KSEG1 + 0x0A00047E) /* Color palette Index and control Register (R/W) */ -#define VR4181_CPALDATREG __preg32(KSEG1 + 0x0A000480) /* Color palette data register (32bits Register) (R/W) */ - -// physical address spaces -#define VR4181_LCD 0x0a000000 -#define VR4181_INTERNAL_IO_2 0x0b000000 -#define VR4181_INTERNAL_IO_1 0x0c000000 -#define VR4181_ISA_MEM 0x10000000 -#define VR4181_ISA_IO 0x14000000 -#define VR4181_ROM 0x18000000 - -// This is the base address for IO port decoding to which the 16 bit IO port address -// is added. Defining it to 0 will usually cause a kernel oops any time port IO is -// attempted, which can be handy for turning up parts of the kernel that make -// incorrect architecture assumptions (by assuming that everything acts like a PC), -// but we need it correctly defined to use the PCMCIA/CF controller: -#define VR4181_PORT_BASE (KSEG1 + VR4181_ISA_IO) -#define VR4181_ISAMEM_BASE (KSEG1 + VR4181_ISA_MEM) - -#endif /* __ASM_VR4181_VR4181_H */ -- cgit v1.2.3 From 0ad7305f52bc8880d50a6471c90d35a6768f2865 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sat, 3 Sep 2005 15:56:07 -0700 Subject: [PATCH] mips: moreover remove vr4181 We also need this patch for removing mips vr4181. Signed-off-by: Yoichi Yuasa Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/Makefile | 7 ------- 1 file changed, 7 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Makefile b/arch/mips/Makefile index bf874f45144f..e7764f3e4887 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -468,13 +468,6 @@ core-$(CONFIG_LASAT) += arch/mips/lasat/ cflags-$(CONFIG_LASAT) += -Iinclude/asm-mips/mach-lasat load-$(CONFIG_LASAT) += 0xffffffff80000000 -# -# NEC Osprey (vr4181) board -# -core-$(CONFIG_NEC_OSPREY) += arch/mips/vr4181/common/ \ - arch/mips/vr4181/osprey/ -load-$(CONFIG_NEC_OSPREY) += 0xffffffff80002000 - # # Common VR41xx # -- cgit v1.2.3 From ab1418a31619a47d78843c20b5fa2245c29824ca Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Sat, 3 Sep 2005 15:56:07 -0700 Subject: [PATCH] more vr4181 removal Signed-off-by: Adrian Bunk Cc: Yoichi Yuasa Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/Kconfig | 12 +----------- arch/mips/kernel/cpu-probe.c | 6 ------ 2 files changed, 1 insertion(+), 17 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 898de2df1fc7..e82d9240ea8e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -445,11 +445,6 @@ config DDB5477_BUS_FREQUENCY depends on DDB5477 default 0 -config NEC_OSPREY - bool "Support for NEC Osprey board" - select DMA_NONCOHERENT - select IRQ_CPU - config SGI_IP22 bool "Support for SGI IP22 (Indy/Indigo2)" select ARC @@ -974,7 +969,7 @@ config MIPS_DISABLE_OBSOLETE_IDE config CPU_LITTLE_ENDIAN bool "Generate little endian code" - default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || NEC_OSPREY || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA + default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA default n if MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927 help Some MIPS machines can be configured for either little or big endian @@ -1091,11 +1086,6 @@ config ARC32 config HAVE_STD_PC_SERIAL_PORT bool -config VR4181 - bool - depends on NEC_OSPREY - default y - config ARC_CONSOLE bool "ARC console support" depends on SGI_IP22 || SNI_RM200_PCI diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 4bb849582314..7685f8baf3f0 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -229,15 +229,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_VR41XX: switch (c->processor_id & 0xf0) { -#ifndef CONFIG_VR4181 case PRID_REV_VR4111: c->cputype = CPU_VR4111; break; -#else - case PRID_REV_VR4181: - c->cputype = CPU_VR4181; - break; -#endif case PRID_REV_VR4121: c->cputype = CPU_VR4121; break; -- cgit v1.2.3 From 07119621e62de0a2c8db6e4896e762c498bfdd17 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 3 Sep 2005 15:56:11 -0700 Subject: [PATCH] mips: add support for Qemu system architecture Add support for the virtual MIPS system that is emulated by Qemu. See http://www.linux-mips.org/wiki/Qemu for a detailed current status. Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/Kconfig | 18 + arch/mips/Makefile | 6 + arch/mips/configs/qemu_defconfig | 655 +++++++++++++++++++++ arch/mips/qemu/Makefile | 5 + arch/mips/qemu/q-firmware.c | 7 + arch/mips/qemu/q-int.S | 17 + arch/mips/qemu/q-irq.c | 37 ++ arch/mips/qemu/q-mem.c | 6 + arch/mips/qemu/q-setup.c | 20 + include/asm-mips/mach-qemu/cpu-feature-overrides.h | 31 + include/asm-mips/mach-qemu/param.h | 13 + include/asm-mips/qemu.h | 24 + 12 files changed, 839 insertions(+) create mode 100644 arch/mips/configs/qemu_defconfig create mode 100644 arch/mips/qemu/Makefile create mode 100644 arch/mips/qemu/q-firmware.c create mode 100644 arch/mips/qemu/q-int.S create mode 100644 arch/mips/qemu/q-irq.c create mode 100644 arch/mips/qemu/q-mem.c create mode 100644 arch/mips/qemu/q-setup.c create mode 100644 include/asm-mips/mach-qemu/cpu-feature-overrides.h create mode 100644 include/asm-mips/mach-qemu/param.h create mode 100644 include/asm-mips/qemu.h (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e82d9240ea8e..8398efdee2fa 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -445,6 +445,24 @@ config DDB5477_BUS_FREQUENCY depends on DDB5477 default 0 +config QEMU + bool "Support for Qemu" + select DMA_COHERENT + select GENERIC_ISA_DMA + select HAVE_STD_PC_SERIAL_PORT + select I8259 + select ISA + select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + help + Qemu is a software emulator which among other architectures also + can simulate a MIPS32 4Kc system. This patch adds support for the + system architecture that currently is being simulated by Qemu. It + will eventually be removed again when Qemu has the capability to + simulate actual MIPS hardware platforms. More information on Qemu + can be found at http://www.linux-mips.org/wiki/Qemu. + config SGI_IP22 bool "Support for SGI IP22 (Indy/Indigo2)" select ARC diff --git a/arch/mips/Makefile b/arch/mips/Makefile index e7764f3e4887..c8b16e668c17 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -423,6 +423,12 @@ core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/ cflags-$(CONFIG_PMC_YOSEMITE) += -Iinclude/asm-mips/mach-yosemite load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 +# Qemu simulating MIPS32 4Kc +# +core-$(CONFIG_QEMU) += arch/mips/qemu/ +cflags-$(CONFIG_QEMU) += -Iinclude/asm-mips/mach-qemu +load-$(CONFIG_QEMU) += 0xffffffff80010000 + # # Momentum Ocelot-3 # diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig new file mode 100644 index 000000000000..b6568e421b99 --- /dev/null +++ b/arch/mips/configs/qemu_defconfig @@ -0,0 +1,655 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.13-rc6 +# Mon Aug 8 11:49:54 2005 +# +CONFIG_MIPS=y + +# +# Code maturity level options +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_CLEAN_COMPILE=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +# CONFIG_SWAP is not set +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_SYSCTL is not set +# CONFIG_AUDIT is not set +# CONFIG_HOTPLUG is not set +CONFIG_KOBJECT_UEVENT=y +# CONFIG_IKCONFIG is not set +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +# CONFIG_BUG is not set +# CONFIG_BASE_FULL is not set +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +# CONFIG_SHMEM is not set +CONFIG_CC_ALIGN_FUNCTIONS=0 +CONFIG_CC_ALIGN_LABELS=0 +CONFIG_CC_ALIGN_LOOPS=0 +CONFIG_CC_ALIGN_JUMPS=0 +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=1 + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# Machine selection +# +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_3 is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +CONFIG_QEMU=y +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_HAVE_DEC_LOCK=y +CONFIG_DMA_COHERENT=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_I8259=y +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_HAVE_STD_PC_SERIAL_PORT=y + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +CONFIG_CPU_R4X00=y +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set +# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_ISA=y +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# PCI Hotplug Support +# + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_IP_TCPDIAG=y +# CONFIG_IP_TCPDIAG_IPV6 is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CDROM_PKTCDVD is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Old CD-ROM drivers (not SCSI, not IDE) +# +# CONFIG_CD_NO_IDESCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# I2O device support +# + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_DEPCA is not set +# CONFIG_HP100 is not set +CONFIG_NET_ISA=y +# CONFIG_E2100 is not set +# CONFIG_EWRK3 is not set +# CONFIG_EEXPRESS is not set +# CONFIG_EEXPRESS_PRO is not set +# CONFIG_HPLAN_PLUS is not set +# CONFIG_HPLAN is not set +# CONFIG_LP486E is not set +# CONFIG_ETH16I is not set +CONFIG_NE2000=y +# CONFIG_NET_PCI is not set +# CONFIG_NET_POCKET is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# + +# +# Token Ring devices +# +# CONFIG_TR is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_UNIX98_PTYS is not set +# CONFIG_LEGACY_PTYS is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# + +# +# I2C support +# +# CONFIG_I2C is not set +# CONFIG_I2C_SENSOR is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +# CONFIG_HWMON is not set + +# +# Misc devices +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB_ARCH_HAS_HCD is not set +# CONFIG_USB_ARCH_HAS_OHCI is not set + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# InfiniBand support +# +# CONFIG_INFINIBAND is not set + +# +# SN Devices +# + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set + +# +# XFS support +# +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +# CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +# CONFIG_PROC_FS is not set +# CONFIG_SYSFS is not set +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_HFSPLUS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="console=ttyS0 debug ip=172.20.0.2:172.20.0.1::255.255.0.0" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +# CONFIG_CRC_CCITT is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y diff --git a/arch/mips/qemu/Makefile b/arch/mips/qemu/Makefile new file mode 100644 index 000000000000..934944ab9e85 --- /dev/null +++ b/arch/mips/qemu/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for Qemu specific kernel interface routines under Linux. +# + +obj-y = q-firmware.o q-int.o q-irq.o q-mem.o q-setup.o diff --git a/arch/mips/qemu/q-firmware.c b/arch/mips/qemu/q-firmware.c new file mode 100644 index 000000000000..5980f02b2df9 --- /dev/null +++ b/arch/mips/qemu/q-firmware.c @@ -0,0 +1,7 @@ +#include +#include + +void __init prom_init(void) +{ + add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM); +} diff --git a/arch/mips/qemu/q-int.S b/arch/mips/qemu/q-int.S new file mode 100644 index 000000000000..6e3dfe5eb14b --- /dev/null +++ b/arch/mips/qemu/q-int.S @@ -0,0 +1,17 @@ +/* + * Qemu interrupt handler code. + * + * Copyright (C) 2005 by Ralf Baechle + */ +#include +#include +#include + + .align 5 + NESTED(qemu_handle_int, PT_SIZE, sp) + SAVE_ALL + CLI + move a0, sp + PTR_LA ra, ret_from_irq + j do_qemu_int + END(qemu_handle_int) diff --git a/arch/mips/qemu/q-irq.c b/arch/mips/qemu/q-irq.c new file mode 100644 index 000000000000..2c4e0704ff10 --- /dev/null +++ b/arch/mips/qemu/q-irq.c @@ -0,0 +1,37 @@ +#include +#include + +#include +#include +#include +#include +#include + +extern asmlinkage void qemu_handle_int(void); + +asmlinkage void do_qemu_int(struct pt_regs *regs) +{ + unsigned int pending = read_c0_status() & read_c0_cause(); + + if (pending & 0x8000) { + ll_timer_interrupt(Q_COUNT_COMPARE_IRQ, regs); + return; + } + if (pending & 0x0400) { + int irq = i8259_irq(); + + if (likely(irq >= 0)) + do_IRQ(irq, regs); + + return; + } +} + +void __init arch_init_irq(void) +{ + set_except_vector(0, qemu_handle_int); + mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK; /* 100MHz */ + + init_i8259_irqs(); + set_c0_status(0x8400); +} diff --git a/arch/mips/qemu/q-mem.c b/arch/mips/qemu/q-mem.c new file mode 100644 index 000000000000..d174fac43031 --- /dev/null +++ b/arch/mips/qemu/q-mem.c @@ -0,0 +1,6 @@ +#include + +unsigned long __init prom_free_prom_memory(void) +{ + return 0UL; +} diff --git a/arch/mips/qemu/q-setup.c b/arch/mips/qemu/q-setup.c new file mode 100644 index 000000000000..1a80eee8cd35 --- /dev/null +++ b/arch/mips/qemu/q-setup.c @@ -0,0 +1,20 @@ +#include +#include +#include + +#define QEMU_PORT_BASE 0xb4000000 + +static void __init qemu_timer_setup(struct irqaction *irq) +{ + /* set the clock to 100 Hz */ + outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */ + outb_p(LATCH & 0xff , 0x40); /* LSB */ + outb(LATCH >> 8 , 0x40); /* MSB */ + setup_irq(0, irq); +} + +void __init plat_setup(void) +{ + set_io_port_base(QEMU_PORT_BASE); + board_timer_setup = qemu_timer_setup; +} diff --git a/include/asm-mips/mach-qemu/cpu-feature-overrides.h b/include/asm-mips/mach-qemu/cpu-feature-overrides.h new file mode 100644 index 000000000000..f4e370e27168 --- /dev/null +++ b/include/asm-mips/mach-qemu/cpu-feature-overrides.h @@ -0,0 +1,31 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H + +/* + * QEMU only comes with a hazard-free MIPS32 processor, so things are easy. + */ +#define cpu_has_mips16 0 +#define cpu_has_divec 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_prefetch 0 +#define cpu_has_mcheck 0 +#define cpu_has_ejtag 0 + +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) +#define cpu_has_ic_fills_f_dc 0 + +#define cpu_has_dsp 0 + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 0 + +#endif /* __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-qemu/param.h b/include/asm-mips/mach-qemu/param.h new file mode 100644 index 000000000000..cb30ee490ae6 --- /dev/null +++ b/include/asm-mips/mach-qemu/param.h @@ -0,0 +1,13 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005 by Ralf Baechle + */ +#ifndef __ASM_MACH_QEMU_PARAM_H +#define __ASM_MACH_QEMU_PARAM_H + +#define HZ 100 /* Internal kernel timer frequency */ + +#endif /* __ASM_MACH_QEMU_PARAM_H */ diff --git a/include/asm-mips/qemu.h b/include/asm-mips/qemu.h new file mode 100644 index 000000000000..905c39585903 --- /dev/null +++ b/include/asm-mips/qemu.h @@ -0,0 +1,24 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005 by Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_QEMU_H +#define __ASM_QEMU_H + +/* + * Interrupt numbers + */ +#define Q_PIC_IRQ_BASE 0 +#define Q_COUNT_COMPARE_IRQ 16 + +/* + * Qemu clock rate. Unlike on real MIPS this has no relation to the + * instruction issue rate, so the choosen value is pure fiction, just needs + * to match the value in Qemu itself. + */ +#define QEMU_C0_COUNTER_CLOCK 100000000 + +#endif /* __ASM_QEMU_H */ -- cgit v1.2.3 From 63b799f9ded82444212afdcf61379a247d544909 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sat, 3 Sep 2005 15:56:13 -0700 Subject: [PATCH] mips: add TANBAC VR4131 multichip module This patch has added TANBAC VR4131 multichip module in arch/mips/Kconfig Signed-off-by: Yoichi Yuasa Cc: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/Kconfig | 30 +++++++++++++++++------------- arch/mips/Makefile | 9 ++------- drivers/char/Kconfig | 5 +++-- 3 files changed, 22 insertions(+), 22 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 8398efdee2fa..0b0d48437129 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -102,25 +102,29 @@ config IBM_WORKPAD select IRQ_CPU select ISA -config TANBAC_TB0226 - bool "Support for TANBAC TB0226 (Mbase)" +config TANBAC_TB022X + bool "Support for TANBAC VR4131 multichip module and TANBAC VR4131DIMM" depends on MACH_VR41XX + select CPU_LITTLE_ENDIAN select DMA_NONCOHERENT - select HW_HAS_PCI select IRQ_CPU + select HW_HAS_PCI help - The TANBAC TB0226 (Mbase) is a MIPS-based platform manufactured by TANBAC. - Please refer to about Mbase. + The TANBAC VR4131 multichip module(TB0225) and + the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms + manufactured by TANBAC. + Please refer to + about VR4131 multichip module and VR4131DIMM. -config TANBAC_TB0229 - bool "Support for TANBAC TB0229 (VR4131DIMM)" - depends on MACH_VR41XX - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU +config TANBAC_TB0226 + bool "Support for TANBAC Mbase(TB0226)" + depends on TANBAC_TB022X + select PCI + select PCI_VR41XX + select GPIO_VR41XX help - The TANBAC TB0229 (VR4131DIMM) is a MIPS-based platform manufactured by TANBAC. - Please refer to about VR4131DIMM. + The TANBAC Mbase(TB0226) is a MIPS-based platform manufactured by TANBAC. + Please refer to about Mbase. config VICTOR_MPC30X bool "Support for Victor MP-C303/304" diff --git a/arch/mips/Makefile b/arch/mips/Makefile index c8b16e668c17..7d1d7c91b857 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -509,14 +509,9 @@ core-$(CONFIG_CASIO_E55) += arch/mips/vr41xx/casio-e55/ load-$(CONFIG_CASIO_E55) += 0xffffffff80004000 # -# TANBAC TB0226 Mbase (VR4131) +# TANBAC VR4131 multichip module(TB0225) and TANBAC VR4131DIMM(TB0229) (VR4131) # -load-$(CONFIG_TANBAC_TB0226) += 0xffffffff80000000 - -# -# TANBAC TB0229 VR4131DIMM (VR4131) -# -load-$(CONFIG_TANBAC_TB0229) += 0xffffffff80000000 +load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000 # # SGI IP22 (Indy/Indigo2) diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index 7333b41d4224..116a7b185999 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -842,8 +842,9 @@ config SONYPI config TANBAC_TB0219 tristate "TANBAC TB0219 base board support" - depends TANBAC_TB0229 - + depends TANBAC_TB022X + select PCI + select PCI_VR41XX menu "Ftape, the floppy tape device driver" -- cgit v1.2.3 From 8dd4aebe49b24348e48581af835ac41c8e483d68 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sat, 3 Sep 2005 15:56:14 -0700 Subject: [PATCH] mips: add default select configs for vr41xx This patch has added default select configs for vr41xx. Signed-off-by: Yoichi Yuasa Cc: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/Kconfig | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 0b0d48437129..a83bc666e7ed 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -80,6 +80,7 @@ config NEC_CMBVR4133 select DMA_NONCOHERENT select IRQ_CPU select HW_HAS_PCI + select PCI select PCI_VR41XX config ROCKHOPPER @@ -91,6 +92,7 @@ config ROCKHOPPER config CASIO_E55 bool "Support for CASIO CASSIOPEIA E-10/15/55/65" depends on MACH_VR41XX + select CPU_LITTLE_ENDIAN select DMA_NONCOHERENT select IRQ_CPU select ISA @@ -98,6 +100,7 @@ config CASIO_E55 config IBM_WORKPAD bool "Support for IBM WorkPad z50" depends on MACH_VR41XX + select CPU_LITTLE_ENDIAN select DMA_NONCOHERENT select IRQ_CPU select ISA @@ -128,17 +131,23 @@ config TANBAC_TB0226 config VICTOR_MPC30X bool "Support for Victor MP-C303/304" + depends on MACH_VR41XX + select CPU_LITTLE_ENDIAN select DMA_NONCOHERENT - select HW_HAS_PCI select IRQ_CPU - depends on MACH_VR41XX + select HW_HAS_PCI + select PCI + select PCI_VR41XX config ZAO_CAPCELLA bool "Support for ZAO Networks Capcella" depends on MACH_VR41XX + select CPU_LITTLE_ENDIAN select DMA_NONCOHERENT - select HW_HAS_PCI select IRQ_CPU + select HW_HAS_PCI + select PCI + select PCI_VR41XX config PCI_VR41XX bool "Add PCI control unit support of NEC VR4100 series" -- cgit v1.2.3 From 466adc66cf6eea0268c8678834c8c6a56e5a2f9e Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sat, 3 Sep 2005 15:56:14 -0700 Subject: [PATCH] fix warning of TANBAC_TB0219 in drivers/char/Kconfig $ make menuconfig scripts/kconfig/mconf arch/i386/Kconfig drivers/char/Kconfig:847:warning: 'select' used by config symbol 'TANBAC_TB0219' refer to undefined symbol 'PCI_VR41XX' Here is a patch for this warning fix. Signed-off-by: Yoichi Yuasa Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/Kconfig | 12 +++--------- drivers/char/Kconfig | 2 -- 2 files changed, 3 insertions(+), 11 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a83bc666e7ed..516a380f3218 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -80,8 +80,6 @@ config NEC_CMBVR4133 select DMA_NONCOHERENT select IRQ_CPU select HW_HAS_PCI - select PCI - select PCI_VR41XX config ROCKHOPPER bool "Support for Rockhopper baseboard" @@ -122,8 +120,6 @@ config TANBAC_TB022X config TANBAC_TB0226 bool "Support for TANBAC Mbase(TB0226)" depends on TANBAC_TB022X - select PCI - select PCI_VR41XX select GPIO_VR41XX help The TANBAC Mbase(TB0226) is a MIPS-based platform manufactured by TANBAC. @@ -136,8 +132,6 @@ config VICTOR_MPC30X select DMA_NONCOHERENT select IRQ_CPU select HW_HAS_PCI - select PCI - select PCI_VR41XX config ZAO_CAPCELLA bool "Support for ZAO Networks Capcella" @@ -146,12 +140,12 @@ config ZAO_CAPCELLA select DMA_NONCOHERENT select IRQ_CPU select HW_HAS_PCI - select PCI - select PCI_VR41XX config PCI_VR41XX bool "Add PCI control unit support of NEC VR4100 series" - depends on MACH_VR41XX && PCI + depends on MACH_VR41XX && HW_HAS_PCI + default y + select PCI config VRC4171 tristate "Add NEC VRC4171 companion chip support" diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index 116a7b185999..f418f45e0780 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -843,8 +843,6 @@ config SONYPI config TANBAC_TB0219 tristate "TANBAC TB0219 base board support" depends TANBAC_TB022X - select PCI - select PCI_VR41XX menu "Ftape, the floppy tape device driver" -- cgit v1.2.3 From e07a7235dd05891a8c1695213ae1f2b48b09f69e Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sat, 3 Sep 2005 15:56:15 -0700 Subject: [PATCH] mips: remove vrc4171 config This patch has removed obsolete VRC4171 config. Cc: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/Kconfig | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 516a380f3218..b1860f717191 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -147,12 +147,6 @@ config PCI_VR41XX default y select PCI -config VRC4171 - tristate "Add NEC VRC4171 companion chip support" - depends on MACH_VR41XX && ISA - ---help--- - The NEC VRC4171/4171A is a companion chip for NEC VR4111/VR4121. - config VRC4173 tristate "Add NEC VRC4173 companion chip support" depends on MACH_VR41XX && PCI_VR41XX -- cgit v1.2.3 From 63fb6fd1c86181d9dd9ba0e6e6082799e149b56b Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sat, 3 Sep 2005 15:56:16 -0700 Subject: [PATCH] mips: changed from VR41xx to VR4100 series in Kconfig This patch has changed from VR41XX to VR4100 series in arch/mips/Kconfig. Signed-off-by: Yoichi Yuasa Cc: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b1860f717191..77ba9ffdf463 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -71,7 +71,7 @@ config OLIVETTI_M700 . config MACH_VR41XX - bool "Support for NEC VR41XX-based machines" + bool "Support for NEC VR4100 series based machines" config NEC_CMBVR4133 bool "Support for NEC CMB-VR4133" -- cgit v1.2.3 From 875d43e72b5bf22161a81de7554f88eccf8a51ae Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 3 Sep 2005 15:56:16 -0700 Subject: [PATCH] mips: clean up 32/64-bit configuration Start cleaning 32-bit vs. 64-bit configuration. Signed-off-by: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/Kconfig | 75 +++++++++++++--------- arch/mips/Makefile | 16 ++--- arch/mips/configs/atlas_defconfig | 4 +- arch/mips/configs/capcella_defconfig | 4 +- arch/mips/configs/cobalt_defconfig | 4 +- arch/mips/configs/db1000_defconfig | 4 +- arch/mips/configs/db1100_defconfig | 4 +- arch/mips/configs/db1500_defconfig | 4 +- arch/mips/configs/db1550_defconfig | 4 +- arch/mips/configs/ddb5476_defconfig | 4 +- arch/mips/configs/ddb5477_defconfig | 4 +- arch/mips/configs/decstation_defconfig | 4 +- arch/mips/configs/e55_defconfig | 4 +- arch/mips/configs/ev64120_defconfig | 4 +- arch/mips/configs/ev96100_defconfig | 4 +- arch/mips/configs/ip22_defconfig | 4 +- arch/mips/configs/ip27_defconfig | 2 +- arch/mips/configs/ip32_defconfig | 2 +- arch/mips/configs/it8172_defconfig | 4 +- arch/mips/configs/ivr_defconfig | 4 +- arch/mips/configs/jaguar-atx_defconfig | 4 +- arch/mips/configs/jmr3927_defconfig | 4 +- arch/mips/configs/lasat200_defconfig | 4 +- arch/mips/configs/malta_defconfig | 4 +- arch/mips/configs/mpc30x_defconfig | 4 +- arch/mips/configs/ocelot_3_defconfig | 4 +- arch/mips/configs/ocelot_c_defconfig | 2 +- arch/mips/configs/ocelot_defconfig | 4 +- arch/mips/configs/ocelot_g_defconfig | 2 +- arch/mips/configs/pb1100_defconfig | 4 +- arch/mips/configs/pb1500_defconfig | 4 +- arch/mips/configs/pb1550_defconfig | 4 +- arch/mips/configs/rm200_defconfig | 4 +- arch/mips/configs/sb1250-swarm_defconfig | 4 +- arch/mips/configs/sead_defconfig | 4 +- arch/mips/configs/tb0226_defconfig | 4 +- arch/mips/configs/tb0229_defconfig | 4 +- arch/mips/configs/workpad_defconfig | 4 +- arch/mips/configs/yosemite_defconfig | 4 +- arch/mips/dec/int-handler.S | 6 +- arch/mips/dec/prom/Makefile | 4 +- arch/mips/defconfig | 4 +- arch/mips/kernel/Makefile | 10 +-- arch/mips/kernel/gdb-low.S | 4 +- arch/mips/kernel/genex.S | 10 +-- arch/mips/kernel/head.S | 6 +- arch/mips/kernel/mips_ksyms.c | 2 +- arch/mips/kernel/process.c | 8 +-- arch/mips/kernel/ptrace.c | 12 ++-- arch/mips/kernel/r4k_fpu.S | 4 +- arch/mips/kernel/r4k_switch.S | 4 +- arch/mips/kernel/setup.c | 4 +- arch/mips/kernel/traps.c | 2 +- arch/mips/kernel/unaligned.c | 12 ++-- arch/mips/lib/memcpy.S | 2 +- arch/mips/math-emu/kernel_linkage.c | 2 +- arch/mips/mm/Makefile | 4 +- arch/mips/mm/c-r4k.c | 4 +- arch/mips/mm/init.c | 8 +-- arch/mips/mm/pg-sb1.c | 8 +-- arch/mips/mm/tlbex.c | 30 ++++----- arch/mips/momentum/jaguar_atx/prom.c | 10 +-- arch/mips/momentum/jaguar_atx/reset.c | 2 +- arch/mips/momentum/jaguar_atx/setup.c | 2 +- arch/mips/momentum/ocelot_3/prom.c | 12 ++-- arch/mips/momentum/ocelot_c/ocelot_c_fpga.h | 2 +- arch/mips/momentum/ocelot_c/prom.c | 12 ++-- arch/mips/momentum/ocelot_c/reset.c | 2 +- arch/mips/momentum/ocelot_c/setup.c | 8 +-- arch/mips/pci/pci-ip32.c | 2 +- arch/mips/sibyte/cfe/setup.c | 2 +- arch/mips/sibyte/swarm/setup.c | 2 +- drivers/block/Kconfig | 2 +- drivers/scsi/Kconfig | 2 +- drivers/serial/Kconfig | 2 +- include/asm-mips/a.out.h | 4 +- include/asm-mips/addrspace.h | 2 +- include/asm-mips/asmmacro.h | 4 +- include/asm-mips/atomic.h | 4 +- include/asm-mips/bitops.h | 8 +-- include/asm-mips/bugs.h | 2 +- include/asm-mips/checksum.h | 4 +- include/asm-mips/cpu-features.h | 4 +- include/asm-mips/dec/prom.h | 12 ++-- include/asm-mips/delay.h | 6 +- include/asm-mips/elf.h | 16 ++--- include/asm-mips/local.h | 4 +- include/asm-mips/mach-generic/spaces.h | 8 +-- include/asm-mips/mach-ip22/spaces.h | 8 +-- include/asm-mips/mach-ip32/cpu-feature-overrides.h | 2 +- include/asm-mips/mmu_context.h | 6 +- include/asm-mips/module.h | 4 +- include/asm-mips/msgbuf.h | 12 ++-- include/asm-mips/paccess.h | 4 +- include/asm-mips/pgalloc.h | 4 +- include/asm-mips/pgtable.h | 4 +- include/asm-mips/processor.h | 4 +- include/asm-mips/ptrace.h | 2 +- include/asm-mips/reg.h | 6 +- include/asm-mips/resource.h | 2 +- include/asm-mips/sgiarcs.h | 8 +-- include/asm-mips/siginfo.h | 4 +- include/asm-mips/sim.h | 8 +-- include/asm-mips/stackframe.h | 22 +++---- include/asm-mips/string.h | 8 +-- include/asm-mips/system.h | 4 +- include/asm-mips/thread_info.h | 4 +- include/asm-mips/types.h | 2 +- include/asm-mips/uaccess.h | 8 +-- include/asm-mips/unistd.h | 2 +- 110 files changed, 330 insertions(+), 319 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 77ba9ffdf463..d892a23fa978 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -4,26 +4,37 @@ config MIPS # Horrible source of confusion. Die, die, die ... select EMBEDDED -config MIPS64 - bool "64-bit kernel" +mainmenu "Linux/MIPS Kernel Configuration" + +source "init/Kconfig" + +menu "Kernel type" + +choice + + prompt "Kernel code model" help - Select this option if you want to build a 64-bit kernel. You should - only select this option if you have hardware that actually has a - 64-bit processor and if your application will actually benefit from - 64-bit processing, otherwise say N. You must say Y for kernels for - SGI IP27 (Origin 200 and 2000) and SGI IP32 (O2). If in doubt say N. + You should only select this option if you have a workload that + actually benefits from 64-bit processing or if your machine has + large memory. You will only be presented a single option in this + menu if your system does not support both 32-bit and 64-bit kernels. -config 64BIT - def_bool MIPS64 +config 32BIT + bool "32-bit kernel" + depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL + select TRAD_SIGNALS + help + Select this option if you want to build a 32-bit kernel. -config MIPS32 - bool - depends on MIPS64 = 'n' - default y +config 64BIT + bool "64-bit kernel" + depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL + help + Select this option if you want to build a 64-bit kernel. -mainmenu "Linux/MIPS Kernel Configuration" +endchoice -source "init/Kconfig" +endmenu menu "Machine selection" @@ -155,7 +166,7 @@ config VRC4173 config TOSHIBA_JMR3927 bool "Support for Toshiba JMR-TX3927 board" - depends on MIPS32 + depends on 32BIT select DMA_NONCOHERENT select HW_HAS_PCI select SWAP_IO_SPACE @@ -173,7 +184,7 @@ config MACH_DECSTATION select BOOT_ELF32 select DMA_NONCOHERENT select IRQ_CPU - depends on MIPS32 || EXPERIMENTAL + depends on 32BIT || EXPERIMENTAL ---help--- This enables support for DEC's MIPS based workstations. For details see the Linux/MIPS FAQ on and the @@ -480,7 +491,7 @@ config SGI_IP22 config SGI_IP27 bool "Support for SGI IP27 (Origin200/2000)" - depends on MIPS64 + depends on 64BIT select ARC select ARC64 select DMA_IP27 @@ -548,7 +559,7 @@ config REPLICATE_EXHANDLERS config SGI_IP32 bool "Support for SGI IP32 (O2) (EXPERIMENTAL)" - depends on MIPS64 && EXPERIMENTAL + depends on 64BIT && EXPERIMENTAL select ARC select ARC32 select BOOT_ELF32 @@ -562,7 +573,7 @@ config SGI_IP32 If you want this kernel to run on SGI O2 workstation, say Y here. config SOC_AU1X00 - depends on MIPS32 + depends on 32BIT bool "Support for AMD/Alchemy Au1X00 SOCs" choice @@ -902,7 +913,7 @@ config SNI_RM200_PCI config TOSHIBA_RBTX4927 bool "Support for Toshiba TBTX49[23]7 board" - depends on MIPS32 + depends on 32BIT select DMA_NONCOHERENT select HAS_TXX9_SERIAL select HW_HAS_PCI @@ -1171,7 +1182,7 @@ config CPU_R3000 config CPU_TX39XX bool "R39XX" - depends on MIPS32 + depends on 32BIT config CPU_VR41XX bool "R41xx" @@ -1205,7 +1216,7 @@ config CPU_R5432 config CPU_R6000 bool "R6000" - depends on MIPS32 && EXPERIMENTAL + depends on 32BIT && EXPERIMENTAL help MIPS Technologies R6000 and R6000A series processors. Note these processors are extremly rare and the support for them is incomplete. @@ -1217,7 +1228,7 @@ config CPU_NEVADA config CPU_R8000 bool "R8000" - depends on MIPS64 && EXPERIMENTAL + depends on 64BIT && EXPERIMENTAL help MIPS Technologies R8000 processors. Note these processors are uncommon and the support for them is incomplete. @@ -1330,11 +1341,11 @@ config SB1_PASS_2_1_WORKAROUNDS config 64BIT_PHYS_ADDR bool "Support for 64-bit physical address space" - depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && MIPS32 + depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT config CPU_ADVANCED bool "Override CPU Options" - depends on MIPS32 + depends on 32BIT help Saying yes here allows you to select support for various features your CPU may or may not have. Most people should say N here. @@ -1388,7 +1399,7 @@ config CPU_HAS_SYNC # config HIGHMEM bool "High Memory Support" - depends on MIPS32 && (CPU_R3000 || CPU_SB1 || CPU_R7000 || CPU_RM9000 || CPU_R10000) && !(MACH_DECSTATION || MOMENCO_JAGUAR_ATX) + depends on 32BIT && (CPU_R3000 || CPU_SB1 || CPU_R7000 || CPU_RM9000 || CPU_R10000) && !(MACH_DECSTATION || MOMENCO_JAGUAR_ATX) config ARCH_FLATMEM_ENABLE def_bool y @@ -1448,7 +1459,7 @@ config RTC_DS1742 config MIPS_INSANE_LARGE bool "Support for large 64-bit configurations" - depends on CPU_R10000 && MIPS64 + depends on CPU_R10000 && 64BIT help MIPS R10000 does support a 44 bit / 16TB address space as opposed to previous 64-bit processors which only supported 40 bit / 1TB. If you @@ -1549,11 +1560,11 @@ source "fs/Kconfig.binfmt" config TRAD_SIGNALS bool - default y if MIPS32 + default y if 32BIT config BUILD_ELF64 bool "Use 64-bit ELF format for building" - depends on MIPS64 + depends on 64BIT help A 64-bit kernel is usually built using the 64-bit ELF binary object format as it's one that allows arbitrary 64-bit constructs. For @@ -1568,11 +1579,11 @@ config BUILD_ELF64 config BINFMT_IRIX bool "Include IRIX binary compatibility" - depends on !CPU_LITTLE_ENDIAN && MIPS32 && BROKEN + depends on !CPU_LITTLE_ENDIAN && 32BIT && BROKEN config MIPS32_COMPAT bool "Kernel support for Linux/MIPS 32-bit binary compatibility" - depends on MIPS64 + depends on 64BIT help Select this option if you want Linux/MIPS 32-bit binary compatibility. Since all software available for Linux/MIPS is diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 7d1d7c91b857..a33328ef86f7 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -37,12 +37,12 @@ else 64bit-emul = elf64btsmip endif -ifdef CONFIG_MIPS32 +ifdef CONFIG_32BIT gcc-abi = 32 tool-prefix = $(32bit-tool-prefix) UTS_MACHINE := mips endif -ifdef CONFIG_MIPS64 +ifdef CONFIG_64BIT gcc-abi = 64 tool-prefix = $(64bit-tool-prefix) UTS_MACHINE := mips64 @@ -63,7 +63,7 @@ ld-emul = $(32bit-emul) vmlinux-32 = vmlinux vmlinux-64 = vmlinux.64 -cflags-$(CONFIG_MIPS64) += $(call cc-option,-mno-explicit-relocs) +cflags-$(CONFIG_64BIT) += $(call cc-option,-mno-explicit-relocs) endif # @@ -524,10 +524,10 @@ load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000 # core-$(CONFIG_SGI_IP22) += arch/mips/sgi-ip22/ cflags-$(CONFIG_SGI_IP22) += -Iinclude/asm-mips/mach-ip22 -ifdef CONFIG_MIPS32 +ifdef CONFIG_32BIT load-$(CONFIG_SGI_IP22) += 0xffffffff88002000 endif -ifdef CONFIG_MIPS64 +ifdef CONFIG_64BIT load-$(CONFIG_SGI_IP22) += 0xffffffff88004000 endif @@ -632,7 +632,7 @@ load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000 cflags-y += -Iinclude/asm-mips/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ -ifdef CONFIG_MIPS32 +ifdef CONFIG_32BIT ifdef CONFIG_CPU_LITTLE_ENDIAN JIFFIES = jiffies_64 else @@ -664,8 +664,8 @@ CPPFLAGS_vmlinux.lds := \ head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o libs-y += arch/mips/lib/ -libs-$(CONFIG_MIPS32) += arch/mips/lib-32/ -libs-$(CONFIG_MIPS64) += arch/mips/lib-64/ +libs-$(CONFIG_32BIT) += arch/mips/lib-32/ +libs-$(CONFIG_64BIT) += arch/mips/lib-64/ core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/ diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig index caad7ca27abd..4084ca3a7581 100644 --- a/arch/mips/configs/atlas_defconfig +++ b/arch/mips/configs/atlas_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:00 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig index 1b7f8a702d06..9abdcbc20a9e 100644 --- a/arch/mips/configs/capcella_defconfig +++ b/arch/mips/configs/capcella_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:00 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index 8861854561e5..ddcfcfbe098a 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:00 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index 19cac1bf4f01..05905dfec1e6 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:01 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index 035ac95d197e..610ff73a6706 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:01 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index c38c4ed18fe7..fed6f2fab48b 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:01 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index ee81309ae3a5..178c0ad1af75 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:02 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/ddb5476_defconfig b/arch/mips/configs/ddb5476_defconfig index d43ed57c4b4e..345cc8b078fc 100644 --- a/arch/mips/configs/ddb5476_defconfig +++ b/arch/mips/configs/ddb5476_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:02 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig index 5a032cdefd63..4acb9e48d24e 100644 --- a/arch/mips/configs/ddb5477_defconfig +++ b/arch/mips/configs/ddb5477_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:02 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index 32ada79da9d8..27b21fb4f13a 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:03 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig index 52074a2085fb..3812e5f10c9b 100644 --- a/arch/mips/configs/e55_defconfig +++ b/arch/mips/configs/e55_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:03 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/ev64120_defconfig b/arch/mips/configs/ev64120_defconfig index 360e842fd4be..705cdbd682d6 100644 --- a/arch/mips/configs/ev64120_defconfig +++ b/arch/mips/configs/ev64120_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:03 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/ev96100_defconfig b/arch/mips/configs/ev96100_defconfig index 657a9508d31a..4c89dfef8e78 100644 --- a/arch/mips/configs/ev96100_defconfig +++ b/arch/mips/configs/ev96100_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:03 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index 3fb102e6a7f7..2990802899da 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:04 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index b5bab3a42fc4..b2a67da1e031 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -4,7 +4,7 @@ # Wed Jan 26 02:49:04 2005 # CONFIG_MIPS=y -CONFIG_MIPS64=y +CONFIG_64BIT=y CONFIG_64BIT=y # diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index bdf1415475ff..2759162f173b 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -4,7 +4,7 @@ # Wed Jan 26 02:49:04 2005 # CONFIG_MIPS=y -CONFIG_MIPS64=y +CONFIG_64BIT=y CONFIG_64BIT=y # diff --git a/arch/mips/configs/it8172_defconfig b/arch/mips/configs/it8172_defconfig index 1ca7746388f0..09c83a01dd92 100644 --- a/arch/mips/configs/it8172_defconfig +++ b/arch/mips/configs/it8172_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:05 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/ivr_defconfig b/arch/mips/configs/ivr_defconfig index c6eef708be1e..121d0c029c5d 100644 --- a/arch/mips/configs/ivr_defconfig +++ b/arch/mips/configs/ivr_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:05 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/jaguar-atx_defconfig b/arch/mips/configs/jaguar-atx_defconfig index 757c4e88cc00..d4e19da57d70 100644 --- a/arch/mips/configs/jaguar-atx_defconfig +++ b/arch/mips/configs/jaguar-atx_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:05 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index e5a613906554..c95e52a9d8bb 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:06 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/lasat200_defconfig b/arch/mips/configs/lasat200_defconfig index 1e7697834e90..3b4d7e6afac4 100644 --- a/arch/mips/configs/lasat200_defconfig +++ b/arch/mips/configs/lasat200_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:06 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 61fb9fb97e6e..33e6bb62f2ea 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:53:14 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig index 31b8f2ad7338..ed44a1a660f7 100644 --- a/arch/mips/configs/mpc30x_defconfig +++ b/arch/mips/configs/mpc30x_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:07 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/ocelot_3_defconfig b/arch/mips/configs/ocelot_3_defconfig index 2cce682fffcf..daa5b8828f57 100644 --- a/arch/mips/configs/ocelot_3_defconfig +++ b/arch/mips/configs/ocelot_3_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:07 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/ocelot_c_defconfig b/arch/mips/configs/ocelot_c_defconfig index 0cbf48a62e02..bdefd4f1310a 100644 --- a/arch/mips/configs/ocelot_c_defconfig +++ b/arch/mips/configs/ocelot_c_defconfig @@ -4,7 +4,7 @@ # Wed Jan 26 02:49:07 2005 # CONFIG_MIPS=y -CONFIG_MIPS64=y +CONFIG_64BIT=y CONFIG_64BIT=y # diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig index 4043950d360a..7526b4748dfe 100644 --- a/arch/mips/configs/ocelot_defconfig +++ b/arch/mips/configs/ocelot_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:08 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/ocelot_g_defconfig index 3870af4537ad..f372508bc25b 100644 --- a/arch/mips/configs/ocelot_g_defconfig +++ b/arch/mips/configs/ocelot_g_defconfig @@ -4,7 +4,7 @@ # Wed Jan 26 02:49:08 2005 # CONFIG_MIPS=y -CONFIG_MIPS64=y +CONFIG_64BIT=y CONFIG_64BIT=y # diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index 6cdabd550300..b7b95789fefb 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:08 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig index 2aebbd2e82b3..49e528340a39 100644 --- a/arch/mips/configs/pb1500_defconfig +++ b/arch/mips/configs/pb1500_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:09 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index 9e21edc28280..8e426776c098 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:09 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index d0c85a4009d6..021cfe38371a 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:09 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index 84978b70714b..1dc935f37582 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:10 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig index 7c718a429b04..4d2fde827f01 100644 --- a/arch/mips/configs/sead_defconfig +++ b/arch/mips/configs/sead_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:10 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index e01727cd0fe9..53e3d4adf1dd 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:12 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/tb0229_defconfig b/arch/mips/configs/tb0229_defconfig index c6ba3de27614..0fe7f505226e 100644 --- a/arch/mips/configs/tb0229_defconfig +++ b/arch/mips/configs/tb0229_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:12 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig index 915c43b6e2d9..d793616effbb 100644 --- a/arch/mips/configs/workpad_defconfig +++ b/arch/mips/configs/workpad_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:12 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig index 562f2b8043ac..6d2290777ad7 100644 --- a/arch/mips/configs/yosemite_defconfig +++ b/arch/mips/configs/yosemite_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:13 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S index 3b3790993219..c89768d5c4e5 100644 --- a/arch/mips/dec/int-handler.S +++ b/arch/mips/dec/int-handler.S @@ -133,7 +133,7 @@ */ mfc0 t0,CP0_CAUSE # get pending interrupts mfc0 t1,CP0_STATUS -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT lw t2,cpu_fpu_mask #endif andi t0,ST0_IM # CAUSE.CE may be non-zero! @@ -141,7 +141,7 @@ beqz t0,spurious -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT and t2,t0 bnez t2,fpu # handle FPU immediately #endif @@ -271,7 +271,7 @@ handle_it: j ret_from_irq nop -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT fpu: j handle_fpe_int nop diff --git a/arch/mips/dec/prom/Makefile b/arch/mips/dec/prom/Makefile index 373822ec2d8c..bcd0247b3a66 100644 --- a/arch/mips/dec/prom/Makefile +++ b/arch/mips/dec/prom/Makefile @@ -5,7 +5,7 @@ lib-y += init.o memory.o cmdline.o identify.o console.o -lib-$(CONFIG_MIPS32) += locore.o -lib-$(CONFIG_MIPS64) += call_o32.o +lib-$(CONFIG_32BIT) += locore.o +lib-$(CONFIG_64BIT) += call_o32.o EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/defconfig b/arch/mips/defconfig index d55fe665926f..2081583daabc 100644 --- a/arch/mips/defconfig +++ b/arch/mips/defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:48:59 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index a0230ee0f7f4..d3303584fbd1 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -13,8 +13,8 @@ binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \ ifdef CONFIG_MODULES obj-y += mips_ksyms.o module.o -obj-$(CONFIG_MIPS32) += module-elf32.o -obj-$(CONFIG_MIPS64) += module-elf64.o +obj-$(CONFIG_32BIT) += module-elf32.o +obj-$(CONFIG_64BIT) += module-elf64.o endif obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o @@ -45,8 +45,8 @@ obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o obj-$(CONFIG_IRQ_MV64340) += irq-mv6434x.o -obj-$(CONFIG_MIPS32) += scall32-o32.o -obj-$(CONFIG_MIPS64) += scall64-64.o +obj-$(CONFIG_32BIT) += scall32-o32.o +obj-$(CONFIG_64BIT) += scall64-64.o obj-$(CONFIG_BINFMT_IRIX) += binfmt_irix.o obj-$(CONFIG_MIPS32_COMPAT) += ioctl32.o linux32.o signal32.o obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o @@ -55,7 +55,7 @@ obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o ptrace32.o obj-$(CONFIG_KGDB) += gdb-low.o gdb-stub.o obj-$(CONFIG_PROC_FS) += proc.o -obj-$(CONFIG_MIPS64) += cpu-bugs64.o +obj-$(CONFIG_64BIT) += cpu-bugs64.o obj-$(CONFIG_GEN_RTC) += genrtc.o diff --git a/arch/mips/kernel/gdb-low.S b/arch/mips/kernel/gdb-low.S index ece6ddaf7011..512bedbfa7b9 100644 --- a/arch/mips/kernel/gdb-low.S +++ b/arch/mips/kernel/gdb-low.S @@ -13,13 +13,13 @@ #include #include -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define DMFC0 mfc0 #define DMTC0 mtc0 #define LDC1 lwc1 #define SDC1 lwc1 #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define DMFC0 dmfc0 #define DMTC0 dmtc0 #define LDC1 ldc1 diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index a5b0a389b063..3a1a3e7586f6 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -54,7 +54,7 @@ NESTED(except_vec3_generic, 0, sp) #endif mfc0 k1, CP0_CAUSE andi k1, k1, 0x7c -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT dsll k1, k1, 1 #endif PTR_L k0, exception_handlers(k1) @@ -81,7 +81,7 @@ NESTED(except_vec3_r4000, 0, sp) beq k1, k0, handle_vced li k0, 14<<2 beq k1, k0, handle_vcei -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT dsll k1, k1, 1 #endif .set pop @@ -244,10 +244,10 @@ NESTED(nmi_handler, PT_SIZE, sp) start with an n and gas will believe \n is ok ... */ .macro __BUILD_verbose nexception LONG_L a1, PT_EPC(sp) -#if CONFIG_MIPS32 +#if CONFIG_32BIT PRINT("Got \nexception at %08lx\012") #endif -#if CONFIG_MIPS64 +#if CONFIG_64BIT PRINT("Got \nexception at %016lx\012") #endif .endm @@ -293,7 +293,7 @@ NESTED(nmi_handler, PT_SIZE, sp) BUILD_HANDLER mcheck mcheck cli verbose /* #24 */ BUILD_HANDLER reserved reserved sti verbose /* others */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* A temporary overflow handler used by check_daddi(). */ __INIT diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index a64e87d22014..2a1b45d66f04 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -107,7 +107,7 @@ .endm .macro setup_c0_status_pri -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT setup_c0_status ST0_KX 0 #else setup_c0_status 0 0 @@ -115,7 +115,7 @@ .endm .macro setup_c0_status_sec -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT setup_c0_status ST0_KX ST0_BEV #else setup_c0_status 0 ST0_BEV @@ -215,7 +215,7 @@ NESTED(smp_bootstrap, 16, sp) * slightly different layout ... */ page swapper_pg_dir, _PGD_ORDER -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT page invalid_pmd_table, _PMD_ORDER #endif page invalid_pte_table, _PTE_ORDER diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c index eed29fc9dc82..86e42c633f73 100644 --- a/arch/mips/kernel/mips_ksyms.c +++ b/arch/mips/kernel/mips_ksyms.c @@ -35,7 +35,7 @@ EXPORT_SYMBOL(memcpy); EXPORT_SYMBOL(memmove); EXPORT_SYMBOL(strcat); EXPORT_SYMBOL(strchr); -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT EXPORT_SYMBOL(strncmp); #endif EXPORT_SYMBOL(strlen); diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 6e70c42c2058..e4f2f8011387 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -70,7 +70,7 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) /* New thread loses kernel privileges. */ status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|KU_MASK); -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT status &= ~ST0_FR; status |= (current->thread.mflags & MF_32BIT_REGS) ? 0 : ST0_FR; #endif @@ -236,10 +236,10 @@ static int __init get_frame_info(struct mips_frame_info *info, void *func) break; if ( -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT ip->i_format.opcode == sw_op && #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT ip->i_format.opcode == sd_op && #endif ip->i_format.rs == 29) @@ -353,7 +353,7 @@ schedule_timeout_caller: out: -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT if (current->thread.mflags & MF_32BIT_REGS) /* Kludge for 32-bit ps */ pc &= 0xffffffffUL; #endif diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 92e70ca3bff9..0b571a5b4b83 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -124,7 +124,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) if (tsk_used_math(child)) { fpureg_t *fregs = get_fpu_regs(child); -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT /* * The odd registers are actually the high * order bits of the values stored in the even @@ -135,7 +135,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) else tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff); #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT tmp = fregs[addr - FPR_BASE]; #endif } else { @@ -213,7 +213,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) sizeof(child->thread.fpu.hard)); child->thread.fpu.hard.fcr31 = 0; } -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT /* * The odd registers are actually the high order bits * of the values stored in the even registers - unless @@ -227,7 +227,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) fregs[addr - FPR_BASE] |= data; } #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT fregs[addr - FPR_BASE] = data; #endif break; @@ -304,14 +304,14 @@ out: static inline int audit_arch(void) { #ifdef CONFIG_CPU_LITTLE_ENDIAN -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT if (!(current->thread.mflags & MF_32BIT_REGS)) return AUDIT_ARCH_MIPSEL64; #endif /* MIPS64 */ return AUDIT_ARCH_MIPSEL; #else /* big endian... */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT if (!(current->thread.mflags & MF_32BIT_REGS)) return AUDIT_ARCH_MIPS64; #endif /* MIPS64 */ diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S index ebb643d8d14c..aba665bcb386 100644 --- a/arch/mips/kernel/r4k_fpu.S +++ b/arch/mips/kernel/r4k_fpu.S @@ -36,7 +36,7 @@ LEAF(_save_fp_context) cfc1 t1, fcr31 -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* Store the 16 odd double precision registers */ EX sdc1 $f1, SC_FPREGS+8(a0) EX sdc1 $f3, SC_FPREGS+24(a0) @@ -118,7 +118,7 @@ LEAF(_save_fp_context32) */ LEAF(_restore_fp_context) EX lw t0, SC_FPC_CSR(a0) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT EX ldc1 $f1, SC_FPREGS+8(a0) EX ldc1 $f3, SC_FPREGS+24(a0) EX ldc1 $f5, SC_FPREGS+40(a0) diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index 1fc3b2eb12bd..175dd1fcbb33 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -105,7 +105,7 @@ * Save a thread's fp context. */ LEAF(_save_fp) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT mfc0 t1, CP0_STATUS #endif fpu_save_double a0 t1 t0 t2 # clobbers t1 @@ -142,7 +142,7 @@ LEAF(_init_fpu) li t1, -1 # SNaN -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT sll t0, t0, 5 bgez t0, 1f # 16 / 32 register mode? diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 3a240e3e004c..12b531c295c4 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -241,7 +241,7 @@ static inline int parse_rd_cmdline(unsigned long* rd_start, unsigned long* rd_en if (*tmp) strcat(command_line, tmp); -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* HACK: Guess if the sign extension was forgotten */ if (start > 0x0000000080000000 && start < 0x00000000ffffffff) start |= 0xffffffff00000000; @@ -446,7 +446,7 @@ static inline void resource_init(void) { int i; -#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64) +#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) /* * The 64bit code in 32bit object format trick can't represent * 64bit wide relocations for linker script symbols. diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 56c36e42e0a6..a53b1ed7b386 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -924,7 +924,7 @@ void __init per_cpu_trap_init(void) * flag that some firmware may have left set and the TS bit (for * IP27). Set XX for ISA IV code to work. */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; #endif if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 3f24a1d45865..36c5212e0928 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -240,7 +240,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, break; case lwu_op: -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * A 32-bit kernel might be running on a 64-bit processor. But * if we're on a 32-bit processor and an i-cache incoherency @@ -278,13 +278,13 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, *newvalue = value; *regptr = ®s->regs[insn.i_format.rt]; break; -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* Cannot handle 64-bit instructions in 32-bit kernel */ goto sigill; case ld_op: -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * A 32-bit kernel might be running on a 64-bit processor. But * if we're on a 32-bit processor and an i-cache incoherency @@ -320,7 +320,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, *newvalue = value; *regptr = ®s->regs[insn.i_format.rt]; break; -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* Cannot handle 64-bit instructions in 32-bit kernel */ goto sigill; @@ -392,7 +392,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, break; case sd_op: -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * A 32-bit kernel might be running on a 64-bit processor. But * if we're on a 32-bit processor and an i-cache incoherency @@ -428,7 +428,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, if (res) goto fault; break; -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* Cannot handle 64-bit instructions in 32-bit kernel */ goto sigill; diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S index afa8eae18ff6..00d73be7dc27 100644 --- a/arch/mips/lib/memcpy.S +++ b/arch/mips/lib/memcpy.S @@ -79,7 +79,7 @@ /* * Only on the 64-bit kernel we can made use of 64-bit registers. */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define USE_DOUBLE #endif diff --git a/arch/mips/math-emu/kernel_linkage.c b/arch/mips/math-emu/kernel_linkage.c index 04397fec30fc..4002f0cf79f3 100644 --- a/arch/mips/math-emu/kernel_linkage.c +++ b/arch/mips/math-emu/kernel_linkage.c @@ -86,7 +86,7 @@ int fpu_emulator_restore_context(struct sigcontext *sc) return err; } -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * This is the o32 version */ diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index f61e038b4440..b56a0abdc3d4 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -5,8 +5,8 @@ obj-y += cache.o extable.o fault.o init.o pgtable.o \ tlbex.o tlbex-fault.o -obj-$(CONFIG_MIPS32) += ioremap.o pgtable-32.o -obj-$(CONFIG_MIPS64) += pgtable-64.o +obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o +obj-$(CONFIG_64BIT) += pgtable-64.o obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index a03ebb2cba67..20d40725e5bb 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -723,10 +723,10 @@ static void local_r4k_flush_cache_sigtramp(void * arg) ".set push\n\t" ".set noat\n\t" ".set mips3\n\t" -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT "la $at,1f\n\t" #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT "dla $at,1f\n\t" #endif "cache %0,($at)\n\t" diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 9c9a271c8a3a..dc6830b10fab 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -96,7 +96,7 @@ static void __init kmap_init(void) kmap_prot = PAGE_KERNEL; } -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT static void __init fixrange_init(unsigned long start, unsigned long end, pgd_t *pgd_base) { @@ -125,7 +125,7 @@ static void __init fixrange_init(unsigned long start, unsigned long end, j = 0; } } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ #endif /* CONFIG_HIGHMEM */ #ifndef CONFIG_NEED_MULTIPLE_NODES @@ -258,7 +258,7 @@ void __init mem_init(void) #ifdef CONFIG_BLK_DEV_INITRD void free_initrd_mem(unsigned long start, unsigned long end) { -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* Switch from KSEG0 to XKPHYS addresses */ start = (unsigned long)phys_to_virt(CPHYSADDR(start)); end = (unsigned long)phys_to_virt(CPHYSADDR(end)); @@ -286,7 +286,7 @@ void free_initmem(void) addr = (unsigned long) &__init_begin; while (addr < (unsigned long) &__init_end) { -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT page = PAGE_OFFSET | CPHYSADDR(addr); #else page = addr; diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c index 59d131b5e536..b63e1ca350f5 100644 --- a/arch/mips/mm/pg-sb1.c +++ b/arch/mips/mm/pg-sb1.c @@ -114,7 +114,7 @@ static inline void copy_page_cpu(void *to, void *from) " pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%1)\n" " pref " SB1_PREF_LOAD_STREAMED_HINT ", -32(%0)\n" "1: pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%1)\n" -# ifdef CONFIG_MIPS64 +# ifdef CONFIG_64BIT " ld $8, -128(%0) \n" /* Block copy a cacheline */ " ld $9, -120(%0) \n" " ld $10, -112(%0) \n" @@ -148,7 +148,7 @@ static inline void copy_page_cpu(void *to, void *from) " daddiu %0, %0, -128 \n" " daddiu %1, %1, -128 \n" #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT " ld $8, 0(%0) \n" /* Block copy a cacheline */ "1: ld $9, 8(%0) \n" " ld $10, 16(%0) \n" @@ -178,7 +178,7 @@ static inline void copy_page_cpu(void *to, void *from) " daddiu %0, %0, 32 \n" " daddiu %1, %1, 32 \n" " bnel %0, %2, 1b \n" -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT " ld $8, 0(%0) \n" #else " lw $2, 0(%0) \n" @@ -186,7 +186,7 @@ static inline void copy_page_cpu(void *to, void *from) " .set pop \n" : "+r" (src), "+r" (dst) : "r" (end) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT : "$8","$9","$10","$11","memory"); #else : "$2","$3","$6","$7","$8","$9","$10","$11","memory"); diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 87e229f4d3d5..592377fa694d 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -448,7 +448,7 @@ L_LA(_r3000_write_probe_fail) L_LA(_r3000_write_probe_ok) /* convenience macros for instructions */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT # define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off) # define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off) # define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh) @@ -486,7 +486,7 @@ L_LA(_r3000_write_probe_ok) #define i_ssnop(buf) i_sll(buf, 0, 0, 1) #define i_ehb(buf) i_sll(buf, 0, 0, 3) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT static __init int __attribute__((unused)) in_compat_space_p(long addr) { /* Is this address in 32bit compat space? */ @@ -516,7 +516,7 @@ static __init int rel_lo(long val) static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) { -#if CONFIG_MIPS64 +#if CONFIG_64BIT if (!in_compat_space_p(addr)) { i_lui(buf, rs, rel_highest(addr)); if (rel_higher(addr)) @@ -682,7 +682,7 @@ static void il_bgezl(u32 **p, struct reloc **r, unsigned int reg, #define C0_EPC 14 #define C0_XCONTEXT 20 -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT) #else # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT) @@ -923,7 +923,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, } } -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * TMP and PTR are scratch. * TMP will be clobbered, PTR will hold the pmd entry. @@ -1010,7 +1010,7 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, } } -#else /* !CONFIG_MIPS64 */ +#else /* !CONFIG_64BIT */ /* * TMP and PTR are scratch. @@ -1038,7 +1038,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ } -#endif /* !CONFIG_MIPS64 */ +#endif /* !CONFIG_64BIT */ static __init void build_adjust_context(u32 **p, unsigned int ctx) { @@ -1159,7 +1159,7 @@ static void __init build_r4000_tlb_refill_handler(void) /* No need for i_nop */ } -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ #else build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ @@ -1171,7 +1171,7 @@ static void __init build_r4000_tlb_refill_handler(void) l_leave(&l, p); i_eret(&p); /* return from trap */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); #endif @@ -1182,7 +1182,7 @@ static void __init build_r4000_tlb_refill_handler(void) * need three, with the the second nop'ed and the third being * unused. */ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT if ((p - tlb_handler) > 64) panic("TLB refill handler space exceeded"); #else @@ -1195,12 +1195,12 @@ static void __init build_r4000_tlb_refill_handler(void) /* * Now fold the handler in the TLB refill handler space. */ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT f = final_handler; /* Simplest case, just copy the handler. */ copy_handler(relocs, labels, tlb_handler, p, f); final_len = p - tlb_handler; -#else /* CONFIG_MIPS64 */ +#else /* CONFIG_64BIT */ f = final_handler + 32; if ((p - tlb_handler) <= 32) { /* Just copy the handler. */ @@ -1235,7 +1235,7 @@ static void __init build_r4000_tlb_refill_handler(void) copy_handler(relocs, labels, split, p, final_handler); final_len = (f - (final_handler + 32)) + (p - split); } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ resolve_relocs(relocs, labels); printk("Synthesized TLB refill handler (%u instructions).\n", @@ -1605,7 +1605,7 @@ build_r4000_tlbchange_handler_head(u32 **p, struct label **l, struct reloc **r, unsigned int pte, unsigned int ptr) { -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ #else build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ @@ -1636,7 +1636,7 @@ build_r4000_tlbchange_handler_tail(u32 **p, struct label **l, l_leave(l, *p); i_eret(p); /* return from trap */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT build_get_pgd_vmalloc64(p, l, r, tmp, ptr); #endif } diff --git a/arch/mips/momentum/jaguar_atx/prom.c b/arch/mips/momentum/jaguar_atx/prom.c index fa5982ac0ac6..827960802b8f 100644 --- a/arch/mips/momentum/jaguar_atx/prom.c +++ b/arch/mips/momentum/jaguar_atx/prom.c @@ -90,7 +90,7 @@ void get_mac(char dest[6]) } #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT unsigned long signext(unsigned long addr) { @@ -143,7 +143,7 @@ char *arg64(unsigned long addrin, int arg_index) return p; } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* PMON passes arguments in C main() style */ void __init prom_init(void) @@ -158,7 +158,7 @@ void __init prom_init(void) // ja_setup_console(); /* The very first thing. */ #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT char *ptr; printk("Mips64 Jaguar-ATX\n"); @@ -201,7 +201,7 @@ void __init prom_init(void) } printk("arcs_cmdline: %s\n", arcs_cmdline); -#else /* CONFIG_MIPS64 */ +#else /* CONFIG_64BIT */ /* save the PROM vectors for debugging use */ debug_vectors = cv; @@ -226,7 +226,7 @@ void __init prom_init(void) } env++; } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ mips_machgroup = MACH_GROUP_MOMENCO; mips_machtype = MACH_MOMENCO_JAGUAR_ATX; diff --git a/arch/mips/momentum/jaguar_atx/reset.c b/arch/mips/momentum/jaguar_atx/reset.c index 48039484cdf9..c4236b1e59fa 100644 --- a/arch/mips/momentum/jaguar_atx/reset.c +++ b/arch/mips/momentum/jaguar_atx/reset.c @@ -27,7 +27,7 @@ void momenco_jaguar_restart(char *command) { /* base address of timekeeper portion of part */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT void *nvram = (void*) 0xfffffffffc807000; #else void *nvram = (void*) 0xfc807000; diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c index 30462e715066..3cf1e46aa4b8 100644 --- a/arch/mips/momentum/jaguar_atx/setup.c +++ b/arch/mips/momentum/jaguar_atx/setup.c @@ -105,7 +105,7 @@ void __init bus_error_init(void) { /* nothing */ } static __init void wire_stupidity_into_tlb(void) { -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT write_c0_wired(0); local_flush_tlb_all(); diff --git a/arch/mips/momentum/ocelot_3/prom.c b/arch/mips/momentum/ocelot_3/prom.c index 89c17a0c0bed..c4fa9c525faa 100644 --- a/arch/mips/momentum/ocelot_3/prom.c +++ b/arch/mips/momentum/ocelot_3/prom.c @@ -93,7 +93,7 @@ void get_mac(char dest[6]) #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT unsigned long signext(unsigned long addr) { @@ -145,7 +145,7 @@ char *arg64(unsigned long addrin, int arg_index) return p; } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ void __init prom_init(void) { @@ -155,7 +155,7 @@ void __init prom_init(void) struct callvectors *cv = (struct callvectors *) fw_arg3; int i; -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT char *ptr; printk("prom_init - MIPS64\n"); @@ -198,7 +198,7 @@ void __init prom_init(void) } printk("arcs_cmdline: %s\n", arcs_cmdline); -#else /* CONFIG_MIPS64 */ +#else /* CONFIG_64BIT */ /* save the PROM vectors for debugging use */ debug_vectors = cv; @@ -224,7 +224,7 @@ void __init prom_init(void) } env++; } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ mips_machgroup = MACH_GROUP_MOMENCO; mips_machtype = MACH_MOMENCO_OCELOT_3; @@ -234,7 +234,7 @@ void __init prom_init(void) get_mac(prom_mac_addr_base); #endif -#ifndef CONFIG_MIPS64 +#ifndef CONFIG_64BIT debug_vectors->printf("Booting Linux kernel...\n"); #endif } diff --git a/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h b/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h index a6cf7a7959b3..97fb77dad723 100644 --- a/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h +++ b/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h @@ -32,7 +32,7 @@ #include -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define OCELOT_C_CS0_ADDR (0xfffffffffc000000) #else #define OCELOT_C_CS0_ADDR (0xfc000000) diff --git a/arch/mips/momentum/ocelot_c/prom.c b/arch/mips/momentum/ocelot_c/prom.c index 49ac302d8901..375877aebcf6 100644 --- a/arch/mips/momentum/ocelot_c/prom.c +++ b/arch/mips/momentum/ocelot_c/prom.c @@ -94,7 +94,7 @@ void get_mac(char dest[6]) #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT unsigned long signext(unsigned long addr) { @@ -144,7 +144,7 @@ char *arg64(unsigned long addrin, int arg_index) p = (char *)get_arg(args, arg_index); return p; } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ void __init prom_init(void) @@ -155,7 +155,7 @@ void __init prom_init(void) struct callvectors *cv = (struct callvectors *) fw_arg3; int i; -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT char *ptr; printk("prom_init - MIPS64\n"); @@ -197,7 +197,7 @@ void __init prom_init(void) } printk("arcs_cmdline: %s\n", arcs_cmdline); -#else /* CONFIG_MIPS64 */ +#else /* CONFIG_64BIT */ /* save the PROM vectors for debugging use */ debug_vectors = cv; @@ -222,7 +222,7 @@ void __init prom_init(void) } env++; } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ mips_machgroup = MACH_GROUP_MOMENCO; mips_machtype = MACH_MOMENCO_OCELOT_C; @@ -232,7 +232,7 @@ void __init prom_init(void) get_mac(prom_mac_addr_base); #endif -#ifndef CONFIG_MIPS64 +#ifndef CONFIG_64BIT debug_vectors->printf("Booting Linux kernel...\n"); #endif } diff --git a/arch/mips/momentum/ocelot_c/reset.c b/arch/mips/momentum/ocelot_c/reset.c index 1f2b4263cc8c..6a2489f3b9a0 100644 --- a/arch/mips/momentum/ocelot_c/reset.c +++ b/arch/mips/momentum/ocelot_c/reset.c @@ -28,7 +28,7 @@ void momenco_ocelot_restart(char *command) { /* base address of timekeeper portion of part */ void *nvram = (void *) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT 0xfffffffffc807000; #else 0xfc807000; diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c index 021c00e3c07c..844ddd06349b 100644 --- a/arch/mips/momentum/ocelot_c/setup.c +++ b/arch/mips/momentum/ocelot_c/setup.c @@ -109,7 +109,7 @@ void PMON_v2_setup(void) */ printk("PMON_v2_setup\n"); -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* marvell and extra space */ add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K); /* fpga, rtc, and uart */ @@ -134,7 +134,7 @@ void PMON_v2_setup(void) unsigned long m48t37y_get_time(void) { -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000; #else unsigned char* rtc_base = (unsigned char*)0xfc800000; @@ -163,7 +163,7 @@ unsigned long m48t37y_get_time(void) int m48t37y_set_time(unsigned long sec) { -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000; #else unsigned char* rtc_base = (unsigned char*)0xfc800000; @@ -342,7 +342,7 @@ static void __init momenco_ocelot_c_setup(void) early_initcall(momenco_ocelot_c_setup); -#ifndef CONFIG_MIPS64 +#ifndef CONFIG_64BIT /* This needs to be one of the first initcalls, because no I/O port access can work before this */ static int io_base_ioremap(void) diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c index 1faeb034f06e..000dc6af6cd3 100644 --- a/arch/mips/pci/pci-ip32.c +++ b/arch/mips/pci/pci-ip32.c @@ -84,7 +84,7 @@ static irqreturn_t macepci_error(int irq, void *dev, struct pt_regs *regs) extern struct pci_ops mace_pci_ops; -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT static struct resource mace_pci_mem_resource = { .name = "SGI O2 PCI MEM", .start = MACEPCI_HI_MEMORY, diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c index d6d0364fa760..d86943f9d812 100644 --- a/arch/mips/sibyte/cfe/setup.c +++ b/arch/mips/sibyte/cfe/setup.c @@ -33,7 +33,7 @@ #include "cfe_error.h" /* Max ram addressable in 32-bit segments */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define MAX_RAM_SIZE (~0ULL) #else #ifdef CONFIG_HIGHMEM diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 457aeb7be858..4742e4fc89f7 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -73,7 +73,7 @@ int swarm_be_handler(struct pt_regs *regs, int is_fixup) { if (!is_fixup && (regs->cp0_cause & 4)) { /* Data bus error - print PA */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT printk("DBE physical address: %010lx\n", __read_64bit_c0_register($26, 1)); #else diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index b594768b0241..879036d4b30b 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -455,7 +455,7 @@ config INITRAMFS_ROOT_GID #for instance. config LBD bool "Support for Large Block Devices" - depends on X86 || MIPS32 || PPC32 || ARCH_S390_31 || SUPERH || UML + depends on X86 || (MIPS && 32BIT) || PPC32 || ARCH_S390_31 || SUPERH || UML help Say Y here if you want to attach large (bigger than 2TB) discs to your machine, or if you want to have a raid or loopback device diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig index 12c208fb18c5..787ad00a2b73 100644 --- a/drivers/scsi/Kconfig +++ b/drivers/scsi/Kconfig @@ -250,7 +250,7 @@ config SCSI_DECNCR config SCSI_DECSII tristate "DEC SII Scsi Driver" - depends on MACH_DECSTATION && SCSI && MIPS32 + depends on MACH_DECSTATION && SCSI && 32BIT config BLK_DEV_3W_XXXX_RAID tristate "3ware 5/6/7/8xxx ATA-RAID support" diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 74b80f7c062d..e39818a34a07 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -308,7 +308,7 @@ config SERIAL_S3C2410_CONSOLE config SERIAL_DZ bool "DECstation DZ serial driver" - depends on MACH_DECSTATION && MIPS32 + depends on MACH_DECSTATION && 32BIT select SERIAL_CORE help DZ11-family serial controllers for VAXstations, including the diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h index e42b3093e903..2b3dc3bed4da 100644 --- a/include/asm-mips/a.out.h +++ b/include/asm-mips/a.out.h @@ -35,10 +35,10 @@ struct exec #ifdef __KERNEL__ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define STACK_TOP TASK_SIZE #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define STACK_TOP (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE) #endif diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index 2caa8c427204..7dc2619f5006 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -48,7 +48,7 @@ #define CPHYSADDR(a) ((_ACAST32_ (a)) & 0x1fffffff) #define XPHYSADDR(a) ((_ACAST64_ (a)) & 0x000000ffffffffff) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * Memory segments (64bit kernel mode addresses) diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h index 37a460aa0378..40ceedcf454e 100644 --- a/include/asm-mips/asmmacro.h +++ b/include/asm-mips/asmmacro.h @@ -11,10 +11,10 @@ #include #include -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #include #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #include #endif diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index 7d89e87bc8c6..c0bd8d014e14 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h @@ -334,7 +334,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) */ #define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT typedef struct { volatile __s64 counter; } atomic64_t; @@ -639,7 +639,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) */ #define atomic64_add_negative(i,v) (atomic64_add_return(i, (v)) < 0) -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* * atomic*_return operations are serializing but not the non-*_return diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 779d2187a6a4..bc136dcfdbe6 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -533,14 +533,14 @@ static inline unsigned long ffz(unsigned long word) int b = 0, s; word = ~word; -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s; s = 8; if (word << 24 != 0) s = 0; b += s; word >>= s; s = 4; if (word << 28 != 0) s = 0; b += s; word >>= s; s = 2; if (word << 30 != 0) s = 0; b += s; word >>= s; s = 1; if (word << 31 != 0) s = 0; b += s; #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s; s = 16; if (word << 48 != 0) s = 0; b += s; word >>= s; s = 8; if (word << 56 != 0) s = 0; b += s; word >>= s; @@ -683,7 +683,7 @@ found_middle: */ static inline int sched_find_first_bit(const unsigned long *b) { -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT if (unlikely(b[0])) return __ffs(b[0]); if (unlikely(b[1])) @@ -694,7 +694,7 @@ static inline int sched_find_first_bit(const unsigned long *b) return __ffs(b[3]) + 96; return __ffs(b[4]) + 128; #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT if (unlikely(b[0])) return __ffs(b[0]); if (unlikely(b[1])) diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h index 18cced19cca4..b14b961c2100 100644 --- a/include/asm-mips/bugs.h +++ b/include/asm-mips/bugs.h @@ -15,7 +15,7 @@ extern void check_bugs64(void); static inline void check_bugs(void) { check_bugs32(); -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT check_bugs64(); #endif } diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h index c25cc92b9950..c1ea5a8714f3 100644 --- a/include/asm-mips/checksum.h +++ b/include/asm-mips/checksum.h @@ -128,7 +128,7 @@ static inline unsigned int csum_tcpudp_nofold(unsigned long saddr, { __asm__( ".set\tnoat\t\t\t# csum_tcpudp_nofold\n\t" -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT "addu\t%0, %2\n\t" "sltu\t$1, %0, %2\n\t" "addu\t%0, $1\n\t" @@ -141,7 +141,7 @@ static inline unsigned int csum_tcpudp_nofold(unsigned long saddr, "sltu\t$1, %0, %4\n\t" "addu\t%0, $1\n\t" #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT "daddu\t%0, %2\n\t" "daddu\t%0, %3\n\t" "daddu\t%0, %4\n\t" diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 1df2c299de82..9a2de642eee6 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -106,7 +106,7 @@ #define PLAT_TRAMPOLINE_STUFF_LINE 0UL #endif -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT # ifndef cpu_has_nofpuex # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) # endif @@ -124,7 +124,7 @@ # endif #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT # ifndef cpu_has_nofpuex # define cpu_has_nofpuex 0 # endif diff --git a/include/asm-mips/dec/prom.h b/include/asm-mips/dec/prom.h index b63e2f2317d1..a05d6d3395fe 100644 --- a/include/asm-mips/dec/prom.h +++ b/include/asm-mips/dec/prom.h @@ -48,15 +48,15 @@ */ #define REX_PROM_MAGIC 0x30464354 -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */ -#else /* !CONFIG_MIPS64 */ +#else /* !CONFIG_64BIT */ #define prom_is_rex(magic) ((magic) == REX_PROM_MAGIC) -#endif /* !CONFIG_MIPS64 */ +#endif /* !CONFIG_64BIT */ /* @@ -105,7 +105,7 @@ extern int (*__pmax_read)(int, void *, int); extern int (*__pmax_close)(int); -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * On MIPS64 we have to call PROM functions via a helper @@ -138,7 +138,7 @@ int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32; #define prom_getenv(x) _prom_getenv(__prom_getenv, x) #define prom_printf(x...) _prom_printf(__prom_printf, x) -#else /* !CONFIG_MIPS64 */ +#else /* !CONFIG_64BIT */ /* * On plain MIPS we just call PROM functions directly. @@ -160,7 +160,7 @@ int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32; #define pmax_read __pmax_read #define pmax_close __pmax_close -#endif /* !CONFIG_MIPS64 */ +#endif /* !CONFIG_64BIT */ extern void prom_meminit(u32); diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h index d0f68447e5a7..a606dbee0412 100644 --- a/include/asm-mips/delay.h +++ b/include/asm-mips/delay.h @@ -57,11 +57,11 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj) * The common rates of 1000 and 128 are rounded wrongly by the * catchall case for 64-bit. Excessive precission? Probably ... */ -#if defined(CONFIG_MIPS64) && (HZ == 128) +#if defined(CONFIG_64BIT) && (HZ == 128) usecs *= 0x0008637bd05af6c7UL; /* 2**64 / (1000000 / HZ) */ -#elif defined(CONFIG_MIPS64) && (HZ == 1000) +#elif defined(CONFIG_64BIT) && (HZ == 1000) usecs *= 0x004189374BC6A7f0UL; /* 2**64 / (1000000 / HZ) */ -#elif defined(CONFIG_MIPS64) +#elif defined(CONFIG_64BIT) usecs *= (0x8000000000000000UL / (500000 / HZ)); #else /* 32-bit junk follows here */ usecs *= (unsigned long) (((0x8000000000000000ULL / (500000 / HZ)) + diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h index 7b92c8045cc2..e48811440015 100644 --- a/include/asm-mips/elf.h +++ b/include/asm-mips/elf.h @@ -125,7 +125,7 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG]; typedef double elf_fpreg_t; typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT /* * This is used to ensure we don't load something for the wrong architecture. @@ -153,9 +153,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; */ #define ELF_CLASS ELFCLASS32 -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * This is used to ensure we don't load something for the wrong architecture. */ @@ -177,7 +177,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; */ #define ELF_CLASS ELFCLASS64 -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* * These are used to set parameters in the core dumps. @@ -193,7 +193,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #ifdef __KERNEL__ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define SET_PERSONALITY(ex, ibcs2) \ do { \ @@ -202,9 +202,9 @@ do { \ set_personality(PER_LINUX); \ } while (0) -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define SET_PERSONALITY(ex, ibcs2) \ do { current->thread.mflags &= ~MF_ABI_MASK; \ @@ -222,7 +222,7 @@ do { current->thread.mflags &= ~MF_ABI_MASK; \ set_personality(PER_LINUX); \ } while (0) -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ extern void dump_regs(elf_greg_t *, struct pt_regs *regs); extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); diff --git a/include/asm-mips/local.h b/include/asm-mips/local.h index 7eb6bf661b80..c38844f615fc 100644 --- a/include/asm-mips/local.h +++ b/include/asm-mips/local.h @@ -5,7 +5,7 @@ #include #include -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT typedef atomic_t local_t; @@ -20,7 +20,7 @@ typedef atomic_t local_t; #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT typedef atomic64_t local_t; diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h index 63c0a81c7832..5a2c1efb4eb7 100644 --- a/include/asm-mips/mach-generic/spaces.h +++ b/include/asm-mips/mach-generic/spaces.h @@ -12,7 +12,7 @@ #include -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define CAC_BASE 0x80000000 #define IO_BASE 0xa0000000 @@ -32,9 +32,9 @@ #define HIGHMEM_START 0x20000000UL #endif -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * This handles the memory map. @@ -67,6 +67,6 @@ #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ #endif /* __ASM_MACH_GENERIC_SPACES_H */ diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h index 30d42fcafe3d..e96166f27c49 100644 --- a/include/asm-mips/mach-ip22/spaces.h +++ b/include/asm-mips/mach-ip22/spaces.h @@ -12,7 +12,7 @@ #include -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define CAC_BASE 0x80000000 #define IO_BASE 0xa0000000 @@ -32,9 +32,9 @@ #define HIGHMEM_START 0x20000000UL #endif -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define PAGE_OFFSET 0xffffffff80000000UL #ifndef HIGHMEM_START @@ -50,6 +50,6 @@ #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ #endif /* __ASM_MACH_IP22_SPACES_H */ diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h index b932237f2193..04713973c6c3 100644 --- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h @@ -18,7 +18,7 @@ * so, for 64bit IP32 kernel we just don't use ll/sc. * This does not affect luserland. */ -#if defined(CONFIG_CPU_R5000) && defined(CONFIG_MIPS64) +#if defined(CONFIG_CPU_R5000) && defined(CONFIG_64BIT) #define cpu_has_llsc 0 #else #define cpu_has_llsc 1 diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h index 48b77c9fb4f2..45cd72d172e8 100644 --- a/include/asm-mips/mmu_context.h +++ b/include/asm-mips/mmu_context.h @@ -28,17 +28,17 @@ extern unsigned long pgd_current[]; #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ pgd_current[smp_processor_id()] = (unsigned long)(pgd) -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define TLBMISS_HANDLER_SETUP() \ write_c0_context((unsigned long) smp_processor_id() << 23); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) #endif -#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64) +#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) #define TLBMISS_HANDLER_SETUP() \ write_c0_context((unsigned long) &pgd_current[smp_processor_id()] << 23); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) #endif -#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64) +#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64) #define TLBMISS_HANDLER_SETUP() \ write_c0_context((unsigned long) smp_processor_id() << 23); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h index 90ee24aad955..0be58b2aeb9f 100644 --- a/include/asm-mips/module.h +++ b/include/asm-mips/module.h @@ -25,7 +25,7 @@ typedef struct Elf64_Sxword r_addend; /* Addend. */ } Elf64_Mips_Rela; -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define Elf_Shdr Elf32_Shdr #define Elf_Sym Elf32_Sym @@ -33,7 +33,7 @@ typedef struct #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define Elf_Shdr Elf64_Shdr #define Elf_Sym Elf64_Sym diff --git a/include/asm-mips/msgbuf.h b/include/asm-mips/msgbuf.h index 513b2824838b..a1533959742e 100644 --- a/include/asm-mips/msgbuf.h +++ b/include/asm-mips/msgbuf.h @@ -15,25 +15,25 @@ struct msqid64_ds { struct ipc64_perm msg_perm; -#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN) +#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) unsigned long __unused1; #endif __kernel_time_t msg_stime; /* last msgsnd time */ -#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN) +#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) unsigned long __unused1; #endif -#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN) +#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) unsigned long __unused2; #endif __kernel_time_t msg_rtime; /* last msgrcv time */ -#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN) +#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) unsigned long __unused2; #endif -#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN) +#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) unsigned long __unused3; #endif __kernel_time_t msg_ctime; /* last change time */ -#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN) +#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) unsigned long __unused3; #endif unsigned long msg_cbytes; /* current number of bytes on queue */ diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h index 36cec9e31696..309bc3099f68 100644 --- a/include/asm-mips/paccess.h +++ b/include/asm-mips/paccess.h @@ -16,10 +16,10 @@ #include #include -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define __PA_ADDR ".word" #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define __PA_ADDR ".dword" #endif diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h index 2d63f5ba403f..ce57288d43bd 100644 --- a/include/asm-mips/pgalloc.h +++ b/include/asm-mips/pgalloc.h @@ -85,7 +85,7 @@ static inline void pte_free(struct page *pte) #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define pgd_populate(mm, pmd, pte) BUG() /* @@ -97,7 +97,7 @@ static inline void pte_free(struct page *pte) #define __pmd_free_tlb(tlb,x) do { } while (0) #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define pgd_populate(mm, pgd, pmd) set_pgd(pgd, __pgd(pmd)) diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index e76ccd6e3a5d..dbe13da0bdad 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -11,10 +11,10 @@ #include #include -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #include #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #include #endif diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 13c54d5b3b48..d6466aa09fb7 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -33,7 +33,7 @@ extern void (*cpu_wait)(void); extern unsigned int vced_count, vcei_count; -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT /* * User space process size: 2GB. This is hardcoded into a few places, * so don't change it unless you know what you are doing. @@ -47,7 +47,7 @@ extern unsigned int vced_count, vcei_count; #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * User space process size: 1TB. This is hardcoded into a few places, * so don't change it unless you know what you are doing. TASK_SIZE diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h index d3c46d633826..2b5c624c3d4f 100644 --- a/include/asm-mips/ptrace.h +++ b/include/asm-mips/ptrace.h @@ -28,7 +28,7 @@ * system call/exception. As usual the registers k0/k1 aren't being saved. */ struct pt_regs { -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT /* Pad bytes for argument save space on the stack. */ unsigned long pad0[6]; #endif diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h index 7b33bbca9585..a1ebd3aa93af 100644 --- a/include/asm-mips/reg.h +++ b/include/asm-mips/reg.h @@ -14,7 +14,7 @@ #include -#if defined(CONFIG_MIPS32) || defined(WANT_COMPAT_REG_H) +#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H) #define EF_R0 6 #define EF_R1 7 @@ -70,7 +70,7 @@ #endif -#if CONFIG_MIPS64 +#if CONFIG_64BIT #define EF_R0 0 #define EF_R1 1 @@ -124,6 +124,6 @@ #define EF_SIZE 304 /* size in bytes */ -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ #endif /* __ASM_MIPS_REG_H */ diff --git a/include/asm-mips/resource.h b/include/asm-mips/resource.h index fd3c6d17a5f6..1fba00c22077 100644 --- a/include/asm-mips/resource.h +++ b/include/asm-mips/resource.h @@ -27,7 +27,7 @@ * but we keep the old value on MIPS32, * for compatibility: */ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT # define RLIM_INFINITY 0x7fffffffUL #endif diff --git a/include/asm-mips/sgiarcs.h b/include/asm-mips/sgiarcs.h index 59450335f049..722b77a8c5e5 100644 --- a/include/asm-mips/sgiarcs.h +++ b/include/asm-mips/sgiarcs.h @@ -367,7 +367,7 @@ struct linux_smonblock { * Macros for calling a 32-bit ARC implementation from 64-bit code */ -#if defined(CONFIG_MIPS64) && defined(CONFIG_ARC32) +#if defined(CONFIG_64BIT) && defined(CONFIG_ARC32) #define __arc_clobbers \ "$2","$3" /* ... */, "$8","$9","$10","$11", \ @@ -476,10 +476,10 @@ struct linux_smonblock { __res; \ }) -#endif /* defined(CONFIG_MIPS64) && defined(CONFIG_ARC32) */ +#endif /* defined(CONFIG_64BIT) && defined(CONFIG_ARC32) */ -#if (defined(CONFIG_MIPS32) && defined(CONFIG_ARC32)) || \ - (defined(CONFIG_MIPS64) && defined(CONFIG_ARC64)) +#if (defined(CONFIG_32BIT) && defined(CONFIG_ARC32)) || \ + (defined(CONFIG_64BIT) && defined(CONFIG_ARC64)) #define ARC_CALL0(dest) \ ({ long __res; \ diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h index a0e26e6c994d..698becab5a9e 100644 --- a/include/asm-mips/siginfo.h +++ b/include/asm-mips/siginfo.h @@ -25,10 +25,10 @@ struct siginfo; /* * Careful to keep union _sifields from shifting ... */ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int)) #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) #endif diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h index 6333169be329..3ccfe09fa744 100644 --- a/include/asm-mips/sim.h +++ b/include/asm-mips/sim.h @@ -16,7 +16,7 @@ #define __str2(x) #x #define __str(x) __str2(x) -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define save_static_function(symbol) \ __asm__ ( \ @@ -42,9 +42,9 @@ __asm__ ( \ #define nabi_no_regargs -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define save_static_function(symbol) \ __asm__ ( \ @@ -78,6 +78,6 @@ __asm__ ( \ unsigned long __dummy6, \ unsigned long __dummy7, -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ #endif /* _ASM_SIM_H */ diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index 86283c25fd5b..fb42f99f8527 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -26,7 +26,7 @@ .macro SAVE_TEMP mfhi v1 -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT LONG_S $8, PT_R8(sp) LONG_S $9, PT_R9(sp) #endif @@ -56,7 +56,7 @@ #ifdef CONFIG_SMP .macro get_saved_sp /* SMP variation */ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT mfc0 k0, CP0_CONTEXT lui k1, %hi(kernelsp) srl k0, k0, 23 @@ -64,7 +64,7 @@ addu k1, k0 LONG_L k1, %lo(kernelsp)(k1) #endif -#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64) +#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) MFC0 k1, CP0_CONTEXT dsra k1, 23 lui k0, %hi(pgd_current) @@ -74,7 +74,7 @@ daddu k1, k0 LONG_L k1, %lo(kernelsp)(k1) #endif -#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64) +#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64) MFC0 k1, CP0_CONTEXT dsrl k1, 23 dsll k1, k1, 3 @@ -83,20 +83,20 @@ .endm .macro set_saved_sp stackp temp temp2 -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT mfc0 \temp, CP0_CONTEXT srl \temp, 23 sll \temp, 2 LONG_S \stackp, kernelsp(\temp) #endif -#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64) +#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) lw \temp, TI_CPU(gp) dsll \temp, 3 lui \temp2, %hi(kernelsp) daddu \temp, \temp2 LONG_S \stackp, %lo(kernelsp)(\temp) #endif -#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64) +#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64) lw \temp, TI_CPU(gp) dsll \temp, 3 LONG_S \stackp, kernelsp(\temp) @@ -140,7 +140,7 @@ LONG_S $6, PT_R6(sp) MFC0 v1, CP0_EPC LONG_S $7, PT_R7(sp) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT LONG_S $8, PT_R8(sp) LONG_S $9, PT_R9(sp) #endif @@ -169,7 +169,7 @@ .macro RESTORE_TEMP LONG_L $24, PT_LO(sp) -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT LONG_L $8, PT_R8(sp) LONG_L $9, PT_R9(sp) #endif @@ -217,7 +217,7 @@ LONG_L $31, PT_R31(sp) LONG_L $28, PT_R28(sp) LONG_L $25, PT_R25(sp) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT LONG_L $8, PT_R8(sp) LONG_L $9, PT_R9(sp) #endif @@ -262,7 +262,7 @@ LONG_L $31, PT_R31(sp) LONG_L $28, PT_R28(sp) LONG_L $25, PT_R25(sp) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT LONG_L $8, PT_R8(sp) LONG_L $9, PT_R9(sp) #endif diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h index b18345504f8a..5a06f6d13899 100644 --- a/include/asm-mips/string.h +++ b/include/asm-mips/string.h @@ -16,7 +16,7 @@ * Most of the inline functions are rather naive implementations so I just * didn't bother updating them for 64-bit ... */ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #ifndef IN_STRING_C @@ -130,7 +130,7 @@ strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count) return __res; } -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ #define __HAVE_ARCH_MEMSET extern void *memset(void *__s, int __c, size_t __count); @@ -141,7 +141,7 @@ extern void *memcpy(void *__to, __const__ void *__from, size_t __n); #define __HAVE_ARCH_MEMMOVE extern void *memmove(void *__dest, __const__ void *__src, size_t __n); -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define __HAVE_ARCH_MEMSCAN static __inline__ void *memscan(void *__addr, int __c, size_t __size) { @@ -161,6 +161,6 @@ static __inline__ void *memscan(void *__addr, int __c, size_t __size) return __addr; } -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ #endif /* _ASM_STRING_H */ diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 169f3d4265b1..6663efd49b27 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -208,7 +208,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) return retval; } -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) { __u64 retval; @@ -330,7 +330,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, return retval; } -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, unsigned long new) { diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h index 42fcd6f2c206..a70cb0854c8a 100644 --- a/include/asm-mips/thread_info.h +++ b/include/asm-mips/thread_info.h @@ -62,10 +62,10 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define current_thread_info() __current_thread_info /* thread information allocation */ -#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_MIPS32) +#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT) #define THREAD_SIZE_ORDER (1) #endif -#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_MIPS64) +#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_64BIT) #define THREAD_SIZE_ORDER (2) #endif #ifdef CONFIG_PAGE_SIZE_8KB diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h index b949ab33e8e2..421b3aea14cc 100644 --- a/include/asm-mips/types.h +++ b/include/asm-mips/types.h @@ -78,7 +78,7 @@ typedef unsigned long long u64; #endif #if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \ - || defined(CONFIG_MIPS64) + || defined(CONFIG_64BIT) typedef u64 dma_addr_t; #else typedef u32 dma_addr_t; diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h index 07114898e065..a543ead72ecf 100644 --- a/include/asm-mips/uaccess.h +++ b/include/asm-mips/uaccess.h @@ -22,7 +22,7 @@ * * For historical reasons, these macros are grossly misnamed. */ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define __UA_LIMIT 0x80000000UL @@ -32,9 +32,9 @@ #define __UA_t0 "$8" #define __UA_t1 "$9" -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define __UA_LIMIT (- TASK_SIZE) @@ -44,7 +44,7 @@ #define __UA_t0 "$12" #define __UA_t1 "$13" -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* * USER_DS is a bitmask that has the bits set that may not be set in a valid diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index 6d21cc964f76..ad4d48056307 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h @@ -1124,7 +1124,7 @@ type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \ # ifndef __mips64 # define __ARCH_WANT_STAT64 # endif -# ifdef CONFIG_MIPS32 +# ifdef CONFIG_32BIT # define __ARCH_WANT_SYS_TIME # endif # ifdef CONFIG_MIPS32_O32 -- cgit v1.2.3 From 42a3b4f25af8f8d77feddf27f839fa0628dbff1a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 3 Sep 2005 15:56:17 -0700 Subject: [PATCH] mips: nuke trailing whitespace Signed-off-by: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/Makefile | 4 +- arch/mips/au1000/common/pci.c | 8 +-- arch/mips/au1000/common/setup.c | 2 +- arch/mips/au1000/common/time.c | 14 ++--- arch/mips/au1000/csb250/board_setup.c | 4 +- arch/mips/au1000/csb250/init.c | 2 +- arch/mips/au1000/db1x00/init.c | 2 +- arch/mips/au1000/hydrogen3/init.c | 2 +- arch/mips/au1000/pb1000/board_setup.c | 2 +- arch/mips/au1000/xxs1500/board_setup.c | 6 +- arch/mips/au1000/xxs1500/init.c | 2 +- arch/mips/au1000/xxs1500/irqmap.c | 2 +- arch/mips/ddb5xxx/ddb5477/irq.c | 6 +- arch/mips/ddb5xxx/ddb5477/setup.c | 22 +++---- arch/mips/dec/ecc-berr.c | 2 +- arch/mips/ite-boards/generic/it8172_setup.c | 2 +- arch/mips/ite-boards/generic/time.c | 16 ++--- arch/mips/kernel/binfmt_elfn32.c | 2 +- arch/mips/kernel/binfmt_elfo32.c | 2 +- arch/mips/kernel/cpu-bugs64.c | 4 +- arch/mips/kernel/gdb-stub.c | 12 ++-- arch/mips/kernel/genex.S | 4 +- arch/mips/kernel/ioctl32.c | 2 +- arch/mips/kernel/irq.c | 2 +- arch/mips/kernel/linux32.c | 22 +++---- arch/mips/kernel/r2300_switch.S | 4 +- arch/mips/kernel/r4k_switch.S | 4 +- arch/mips/kernel/signal32.c | 2 +- arch/mips/kernel/vmlinux.lds.S | 2 +- arch/mips/lasat/at93c.c | 16 ++--- arch/mips/lasat/at93c.h | 4 +- arch/mips/lasat/ds1603.c | 12 ++-- arch/mips/lasat/ds1603.h | 6 +- arch/mips/lasat/image/Makefile | 2 +- arch/mips/lasat/image/head.S | 2 +- arch/mips/lasat/interrupt.c | 4 +- arch/mips/lasat/lasat_board.c | 8 +-- arch/mips/lasat/picvue.c | 12 ++-- arch/mips/lasat/picvue.h | 4 +- arch/mips/lasat/picvue_proc.c | 10 ++-- arch/mips/lasat/prom.c | 2 +- arch/mips/lasat/reset.c | 2 +- arch/mips/lasat/setup.c | 4 +- arch/mips/lasat/sysctl.c | 26 ++++----- arch/mips/lib-32/Makefile | 2 +- arch/mips/lib-64/Makefile | 2 +- arch/mips/lib/memcpy.S | 4 +- arch/mips/mips-boards/atlas/atlas_int.c | 2 +- arch/mips/mips-boards/generic/init.c | 6 +- arch/mips/mips-boards/generic/time.c | 2 +- arch/mips/mips-boards/malta/malta_setup.c | 6 +- arch/mips/mm/c-r4k.c | 16 ++--- arch/mips/mm/c-sb1.c | 2 +- arch/mips/mm/cerr-sb1.c | 24 ++++---- arch/mips/mm/dma-noncoherent.c | 10 ++-- arch/mips/mm/pg-sb1.c | 2 +- arch/mips/momentum/jaguar_atx/int-handler.S | 12 ++-- arch/mips/momentum/jaguar_atx/prom.c | 2 +- arch/mips/momentum/jaguar_atx/setup.c | 2 +- arch/mips/momentum/ocelot_c/int-handler.S | 8 +-- arch/mips/momentum/ocelot_c/prom.c | 2 +- arch/mips/pci/fixup-ddb5074.c | 2 +- arch/mips/pci/fixup-ddb5477.c | 2 +- arch/mips/pci/fixup-malta.c | 2 +- arch/mips/pci/fixup-rbtx4927.c | 2 +- arch/mips/pci/fixup-sni.c | 2 +- arch/mips/pci/ops-ddb5477.c | 4 +- arch/mips/pci/ops-tx4927.c | 6 +- arch/mips/pci/pci-ddb5477.c | 8 +-- arch/mips/pci/pci.c | 4 +- arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c | 14 ++--- arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h | 4 +- arch/mips/sgi-ip22/ip22-eisa.c | 2 +- arch/mips/sgi-ip22/ip22-hpc.c | 2 +- arch/mips/sgi-ip22/ip22-int.c | 12 ++-- arch/mips/sgi-ip22/ip22-nvram.c | 8 +-- arch/mips/sgi-ip22/ip22-reset.c | 2 +- arch/mips/sgi-ip22/ip22-time.c | 2 +- arch/mips/sgi-ip27/ip27-memory.c | 2 +- arch/mips/sgi-ip32/ip32-reset.c | 2 +- arch/mips/sibyte/cfe/cfe_error.h | 10 ++-- arch/mips/sibyte/cfe/console.c | 2 +- arch/mips/sibyte/cfe/setup.c | 2 +- arch/mips/sibyte/cfe/smp.c | 2 +- arch/mips/sibyte/sb1250/bus_watcher.c | 6 +- arch/mips/sibyte/sb1250/irq.c | 4 +- arch/mips/sibyte/swarm/rtc_m41t81.c | 10 ++-- arch/mips/sibyte/swarm/setup.c | 2 +- arch/mips/sni/irq.c | 2 +- arch/mips/sni/setup.c | 2 +- arch/mips/tx4927/common/tx4927_irq_handler.S | 6 +- arch/mips/tx4927/common/tx4927_setup.c | 2 +- arch/mips/tx4927/toshiba_rbtx4927/Makefile | 6 +- .../tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | 42 ++++++------- .../toshiba_rbtx4927/toshiba_rbtx4927_setup.c | 2 +- arch/mips/vr41xx/common/vrc4173.c | 2 +- include/asm-mips/asmmacro.h | 4 +- include/asm-mips/bitops.h | 4 +- include/asm-mips/ddb5xxx/ddb5477.h | 6 +- include/asm-mips/fpregdef.h | 4 +- include/asm-mips/fpu.h | 8 +-- include/asm-mips/ip32/mace.h | 8 +-- include/asm-mips/lasat/serial.h | 4 +- include/asm-mips/mach-au1x00/au1000.h | 2 +- include/asm-mips/mach-db1x00/db1x00.h | 2 +- include/asm-mips/mach-jazz/floppy.h | 2 +- include/asm-mips/mach-pb1x00/pb1500.h | 4 +- include/asm-mips/r4kcache.h | 68 +++++++++++----------- include/asm-mips/rtc.h | 2 +- include/asm-mips/sgi/gio.h | 2 +- include/asm-mips/sgi/hpc3.h | 4 +- include/asm-mips/sgi/ioc.h | 4 +- include/asm-mips/sgi/ip22.h | 2 +- include/asm-mips/sgi/mc.h | 6 +- include/asm-mips/sibyte/carmel.h | 12 ++-- include/asm-mips/sibyte/sb1250_defs.h | 38 ++++++------ include/asm-mips/sibyte/sb1250_dma.h | 42 ++++++------- include/asm-mips/sibyte/sb1250_genbus.h | 24 ++++---- include/asm-mips/sibyte/sb1250_int.h | 24 ++++---- include/asm-mips/sibyte/sb1250_l2c.h | 22 +++---- include/asm-mips/sibyte/sb1250_ldt.h | 32 +++++----- include/asm-mips/sibyte/sb1250_mac.h | 26 ++++----- include/asm-mips/sibyte/sb1250_mc.h | 28 ++++----- include/asm-mips/sibyte/sb1250_regs.h | 68 +++++++++++----------- include/asm-mips/sibyte/sb1250_scd.h | 36 ++++++------ include/asm-mips/sibyte/sb1250_smbus.h | 24 ++++---- include/asm-mips/sibyte/sb1250_syncser.h | 12 ++-- include/asm-mips/sibyte/sb1250_uart.h | 30 +++++----- include/asm-mips/sigcontext.h | 4 +- include/asm-mips/socket.h | 2 +- include/asm-mips/statfs.h | 2 +- include/asm-mips/titan_dep.h | 2 +- include/asm-mips/tx4927/tx4927.h | 52 ++++++++--------- include/asm-mips/tx4927/tx4927_pci.h | 4 +- include/asm-mips/vr41xx/vrc4173.h | 4 +- include/asm-mips/war.h | 4 +- include/asm-mips/xxs1500.h | 2 +- 137 files changed, 596 insertions(+), 596 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Makefile b/arch/mips/Makefile index a33328ef86f7..d27b82595485 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -177,7 +177,7 @@ cflags-$(CONFIG_CPU_MIPS64) += \ cflags-$(CONFIG_CPU_R5000) += \ $(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \ - -Wa,--trap + -Wa,--trap cflags-$(CONFIG_CPU_R5432) += \ $(call set_gccflags,r5400,mips4,r5000,mips4,mips2) \ @@ -720,7 +720,7 @@ archclean: @$(MAKE) $(clean)=arch/mips/boot @$(MAKE) $(clean)=arch/mips/lasat -# Generate = USECS_PER_JIFFY) @@ -375,8 +375,8 @@ static unsigned long do_fast_pm_gettimeoffset(void) au_sync(); offset = pc0 - last_pc0; if (offset > 2*MATCH20_INC) { - printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n", - (unsigned)offset, (unsigned)last_pc0, + printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n", + (unsigned)offset, (unsigned)last_pc0, (unsigned)last_match20, (unsigned)pc0); } offset = (unsigned long)((offset * 305) / 10); @@ -394,11 +394,11 @@ void au1xxx_timer_setup(struct irqaction *irq) r4k_offset = cal_r4koff(); printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); - //est_freq = 2*r4k_offset*HZ; - est_freq = r4k_offset*HZ; + //est_freq = 2*r4k_offset*HZ; + est_freq = r4k_offset*HZ; est_freq += 5000; /* round */ est_freq -= est_freq%10000; - printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, (est_freq%1000000)*100/1000000); set_au1x00_speed(est_freq); set_au1x00_lcd_clock(); // program the LCD clock diff --git a/arch/mips/au1000/csb250/board_setup.c b/arch/mips/au1000/csb250/board_setup.c index 90426eaffb23..1c55c5f59d75 100644 --- a/arch/mips/au1000/csb250/board_setup.c +++ b/arch/mips/au1000/csb250/board_setup.c @@ -182,7 +182,7 @@ void __init board_setup(void) au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV); au_writel(0, Au1500_PCI_MWBASE_REV_CCL); au_writel(0x02a00356, Au1500_PCI_STATCMD); - au_writel(0x00003c04, Au1500_PCI_HDRTYPE); + au_writel(0x00003c04, Au1500_PCI_HDRTYPE); au_writel(0x00000008, Au1500_PCI_MBAR); au_sync(); @@ -216,7 +216,7 @@ csb250_pci_idsel(unsigned int devsel, int assert) unsigned int gpio2_pins; retval = 1; - + /* First, disable both selects, then assert the one requested. */ au_writel(0xc000c000, GPIO2_OUTPUT); diff --git a/arch/mips/au1000/csb250/init.c b/arch/mips/au1000/csb250/init.c index 4320057fc439..bd99733abc0b 100644 --- a/arch/mips/au1000/csb250/init.c +++ b/arch/mips/au1000/csb250/init.c @@ -81,7 +81,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) csb_env[0] = env1; mips_machgroup = MACH_GROUP_ALCHEMY; - mips_machtype = MACH_CSB250; + mips_machtype = MACH_CSB250; prom_init_cmdline(); memsize_str = prom_getenv("memsize"); diff --git a/arch/mips/au1000/db1x00/init.c b/arch/mips/au1000/db1x00/init.c index 51eee94a5e82..4b9d5e46edbb 100644 --- a/arch/mips/au1000/db1x00/init.c +++ b/arch/mips/au1000/db1x00/init.c @@ -61,7 +61,7 @@ void __init prom_init(void) prom_envp = (char **) fw_arg2; mips_machgroup = MACH_GROUP_ALCHEMY; - mips_machtype = MACH_DB1000; /* set the platform # */ + mips_machtype = MACH_DB1000; /* set the platform # */ prom_init_cmdline(); diff --git a/arch/mips/au1000/hydrogen3/init.c b/arch/mips/au1000/hydrogen3/init.c index eee4adf98711..8cc9879dd582 100644 --- a/arch/mips/au1000/hydrogen3/init.c +++ b/arch/mips/au1000/hydrogen3/init.c @@ -63,7 +63,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) prom_envp = envp; mips_machgroup = MACH_GROUP_ALCHEMY; - mips_machtype = MACH_DB1000; /* set the platform # */ + mips_machtype = MACH_DB1000; /* set the platform # */ prom_init_cmdline(); memsize_str = prom_getenv("memsize"); diff --git a/arch/mips/au1000/pb1000/board_setup.c b/arch/mips/au1000/pb1000/board_setup.c index 2fa211b69329..0b4807dc9f44 100644 --- a/arch/mips/au1000/pb1000/board_setup.c +++ b/arch/mips/au1000/pb1000/board_setup.c @@ -174,7 +174,7 @@ void __init board_setup(void) case 0x02: /* HB */ break; default: /* HC and newer */ - /* Enable sys bus clock divider when IDLE state or no bus + /* Enable sys bus clock divider when IDLE state or no bus activity. */ au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); break; diff --git a/arch/mips/au1000/xxs1500/board_setup.c b/arch/mips/au1000/xxs1500/board_setup.c index 9dadc82536f4..1e59433dfd66 100644 --- a/arch/mips/au1000/xxs1500/board_setup.c +++ b/arch/mips/au1000/xxs1500/board_setup.c @@ -49,7 +49,7 @@ void board_reset (void) void __init board_setup(void) { u32 pin_func; - + // set multiple use pins (UART3/GPIO) to UART (it's used as UART too) pin_func = au_readl(SYS_PINFUNC) & (u32)(~SYS_PF_UR3); pin_func |= SYS_PF_UR3; @@ -75,11 +75,11 @@ void __init board_setup(void) au_writel(1, GPIO2_ENABLE); /* gpio2 208/9/10/11 are inputs */ au_writel((1<<8) | (1<<9) | (1<<10) | (1<<11), GPIO2_DIR); - + /* turn off power */ au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<14))|(1<<30), GPIO2_OUTPUT); #endif - + #ifdef CONFIG_PCI #if defined(__MIPSEB__) diff --git a/arch/mips/au1000/xxs1500/init.c b/arch/mips/au1000/xxs1500/init.c index 03f755291b51..f1c76533b6fc 100644 --- a/arch/mips/au1000/xxs1500/init.c +++ b/arch/mips/au1000/xxs1500/init.c @@ -55,7 +55,7 @@ void __init prom_init(void) prom_envp = (char **) fw_arg2; mips_machgroup = MACH_GROUP_ALCHEMY; - mips_machtype = MACH_XXS1500; /* set the platform # */ + mips_machtype = MACH_XXS1500; /* set the platform # */ prom_init_cmdline(); diff --git a/arch/mips/au1000/xxs1500/irqmap.c b/arch/mips/au1000/xxs1500/irqmap.c index 954800a0ab52..52f2f7daeb05 100644 --- a/arch/mips/au1000/xxs1500/irqmap.c +++ b/arch/mips/au1000/xxs1500/irqmap.c @@ -56,7 +56,7 @@ au1xxx_irq_map_t au1xxx_irq_map[] = { { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, - { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, + { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* CF interrupt */ diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c index 5f027bfa4af8..9ffe1a9142ca 100644 --- a/arch/mips/ddb5xxx/ddb5477/irq.c +++ b/arch/mips/ddb5xxx/ddb5477/irq.c @@ -76,7 +76,7 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger) extern void vrc5477_irq_init(u32 base); extern void mips_cpu_irq_init(u32 base); extern asmlinkage void ddb5477_handle_int(void); -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); +extern int setup_irq(unsigned int irq, struct irqaction *irqaction); static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; void __init arch_init_irq(void) @@ -94,7 +94,7 @@ void __init arch_init_irq(void) /* setup PCI interrupt attributes */ set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE); - if (mips_machtype == MACH_NEC_ROCKHOPPERII) + if (mips_machtype == MACH_NEC_ROCKHOPPERII) set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE); else set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE); @@ -134,7 +134,7 @@ void __init arch_init_irq(void) /* setup cascade interrupts */ setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade); - setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); + setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); /* hook up the first-level interrupt handler */ set_except_vector(0, ddb5477_handle_int); diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c index 15c6e543b56f..d62f5a789b05 100644 --- a/arch/mips/ddb5xxx/ddb5477/setup.c +++ b/arch/mips/ddb5xxx/ddb5477/setup.c @@ -141,7 +141,7 @@ static void __init ddb_time_init(void) /* mips_hpt_frequency is 1/2 of the cpu core freq */ i = (read_c0_config() >> 28 ) & 7; - if ((current_cpu_data.cputype == CPU_R5432) && (i == 3)) + if ((current_cpu_data.cputype == CPU_R5432) && (i == 3)) i = 4; mips_hpt_frequency = bus_frequency*(i+4)/4; } @@ -298,11 +298,11 @@ static void __init ddb5477_board_init(void) if (mips_machtype == MACH_NEC_ROCKHOPPER || mips_machtype == MACH_NEC_ROCKHOPPERII) { - /* Disable bus diagnostics. */ + /* Disable bus diagnostics. */ ddb_out32(DDB_PCICTL0_L, 0); ddb_out32(DDB_PCICTL0_H, 0); ddb_out32(DDB_PCICTL1_L, 0); - ddb_out32(DDB_PCICTL1_H, 0); + ddb_out32(DDB_PCICTL1_H, 0); } if (mips_machtype == MACH_NEC_ROCKHOPPER) { @@ -354,7 +354,7 @@ static void __init ddb5477_board_init(void) */ pci_write_config_byte(&dev_m1533, 0x58, 0x74); - /* + /* * positive decode (bit6 -0) * enable IDE controler interrupt (bit 4 -1) * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101) @@ -364,31 +364,31 @@ static void __init ddb5477_board_init(void) /* Setup M5229 registers */ dev_m5229.bus = &bus; dev_m5229.sysdata = NULL; - dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE + dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE /* * enable IDE in the M5229 config register 0x50 (bit 0 - 1) - * M5229 IDSEL is addr:15; see above setting + * M5229 IDSEL is addr:15; see above setting */ pci_read_config_byte(&dev_m5229, 0x50, &temp8); pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1); - /* - * enable bus master (bit 2) and IO decoding (bit 0) + /* + * enable bus master (bit 2) and IO decoding (bit 0) */ pci_read_config_byte(&dev_m5229, 0x04, &temp8); pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5); /* * enable native, copied from arch/ppc/k2boot/head.S - * TODO - need volatile, need to be portable + * TODO - need volatile, need to be portable */ pci_write_config_byte(&dev_m5229, 0x09, 0xef); - /* Set Primary Channel Command Block Timing */ + /* Set Primary Channel Command Block Timing */ pci_write_config_byte(&dev_m5229, 0x59, 0x31); - /* + /* * Enable primary channel 40-pin cable * M5229 register 0x4a (bit 0) */ diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c index 133fb7c48e6c..6dbce92eb068 100644 --- a/arch/mips/dec/ecc-berr.c +++ b/arch/mips/dec/ecc-berr.c @@ -253,7 +253,7 @@ static inline void dec_kn03_be_init(void) kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR); kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN); - + /* * Set normal ECC detection and generation, enable ECC correction. * For KN05 we also need to make sure EE (?) is enabled in the MB. diff --git a/arch/mips/ite-boards/generic/it8172_setup.c b/arch/mips/ite-boards/generic/it8172_setup.c index d808a67294b8..a5f6d84bc181 100644 --- a/arch/mips/ite-boards/generic/it8172_setup.c +++ b/arch/mips/ite-boards/generic/it8172_setup.c @@ -129,7 +129,7 @@ static void __init it8172_setup(void) /* * IO/MEM resources. - * + * * revisit this area. */ set_io_port_base(KSEG1); diff --git a/arch/mips/ite-boards/generic/time.c b/arch/mips/ite-boards/generic/time.c index 30a6c0d5fc50..f5d67ee21ac6 100644 --- a/arch/mips/ite-boards/generic/time.c +++ b/arch/mips/ite-boards/generic/time.c @@ -72,7 +72,7 @@ static inline int rtc_dm_binary(void) { return saved_control & RTC_DM_BINARY; } static inline unsigned char bin_to_hw(unsigned char c) { - if (rtc_dm_binary()) + if (rtc_dm_binary()) return c; else return ((c/10) << 4) + (c%10); @@ -91,9 +91,9 @@ hw_to_bin(unsigned char c) static inline unsigned char hour_bin_to_hw(unsigned char c) { - if (rtc_24h()) + if (rtc_24h()) return bin_to_hw(c); - if (c >= 12) + if (c >= 12) return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */ else return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */ @@ -105,9 +105,9 @@ hour_hw_to_bin(unsigned char c) unsigned char tmp = hw_to_bin(c&0x3f); if (rtc_24h()) return tmp; - if (c & 0x80) + if (c & 0x80) return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */ - else + else return (tmp==12)?0:tmp; /* 12am is 0 */ } @@ -145,7 +145,7 @@ static unsigned long __init cal_r4koff(void) return (mips_hpt_frequency / HZ); } -static unsigned long +static unsigned long it8172_rtc_get_time(void) { unsigned int year, mon, day, hour, min, sec; @@ -166,12 +166,12 @@ it8172_rtc_get_time(void) hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS)); day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH)); mon = hw_to_bin(CMOS_READ(RTC_MONTH)); - year = hw_to_bin(CMOS_READ(RTC_YEAR)) + + year = hw_to_bin(CMOS_READ(RTC_YEAR)) + hw_to_bin(*rtc_century_reg) * 100; /* restore interrupts */ local_irq_restore(flags); - + return mktime(year, mon, day, hour, min, sec); } diff --git a/arch/mips/kernel/binfmt_elfn32.c b/arch/mips/kernel/binfmt_elfn32.c index ed47041f3030..6b645fbb1ddc 100644 --- a/arch/mips/kernel/binfmt_elfn32.c +++ b/arch/mips/kernel/binfmt_elfn32.c @@ -103,7 +103,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value) * Convert jiffies to nanoseconds and seperate with * one divide. */ - u64 nsec = (u64)jiffies * TICK_NSEC; + u64 nsec = (u64)jiffies * TICK_NSEC; value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec); value->tv_usec /= NSEC_PER_USEC; } diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c index ee21b18c37a8..b4075e99c452 100644 --- a/arch/mips/kernel/binfmt_elfo32.c +++ b/arch/mips/kernel/binfmt_elfo32.c @@ -105,7 +105,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value) * Convert jiffies to nanoseconds and seperate with * one divide. */ - u64 nsec = (u64)jiffies * TICK_NSEC; + u64 nsec = (u64)jiffies * TICK_NSEC; value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec); value->tv_usec /= NSEC_PER_USEC; } diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c index 11ebe5d4c446..47a087b6c11b 100644 --- a/arch/mips/kernel/cpu-bugs64.c +++ b/arch/mips/kernel/cpu-bugs64.c @@ -137,7 +137,7 @@ static inline void check_mult_sh(void) for (i = 0; i < 8; i++) if (v1[i] != w[i]) bug = 1; - + if (bug == 0) { printk("no.\n"); return; @@ -149,7 +149,7 @@ static inline void check_mult_sh(void) for (i = 0; i < 8; i++) if (v2[i] != w[i]) fix = 0; - + if (fix == 1) { printk("yes.\n"); return; diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c index 269889302a27..d3fd1ab14274 100644 --- a/arch/mips/kernel/gdb-stub.c +++ b/arch/mips/kernel/gdb-stub.c @@ -687,8 +687,8 @@ void handle_exception (struct gdb_regs *regs) * acquire the big kgdb spinlock */ if (!spin_trylock(&kgdb_lock)) { - /* - * some other CPU has the lock, we should go back to + /* + * some other CPU has the lock, we should go back to * receive the gdb_wait IPC */ return; @@ -703,7 +703,7 @@ void handle_exception (struct gdb_regs *regs) async_bp.addr = 0; } - /* + /* * acquire the CPU spinlocks */ for (i = num_online_cpus()-1; i >= 0; i--) @@ -894,7 +894,7 @@ void handle_exception (struct gdb_regs *regs) ptr = &input_buffer[1]; if (hexToLong(&ptr, &addr)) regs->cp0_epc = addr; - + goto exit_kgdb_exception; break; @@ -1001,7 +1001,7 @@ void breakpoint(void) return; __asm__ __volatile__( - ".globl breakinst\n\t" + ".globl breakinst\n\t" ".set\tnoreorder\n\t" "nop\n" "breakinst:\tbreak\n\t" @@ -1014,7 +1014,7 @@ void breakpoint(void) void async_breakpoint(void) { __asm__ __volatile__( - ".globl async_breakinst\n\t" + ".globl async_breakinst\n\t" ".set\tnoreorder\n\t" "nop\n" "async_breakinst:\tbreak\n\t" diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 3a1a3e7586f6..9bb2caaf7fc6 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -246,10 +246,10 @@ NESTED(nmi_handler, PT_SIZE, sp) LONG_L a1, PT_EPC(sp) #if CONFIG_32BIT PRINT("Got \nexception at %08lx\012") -#endif +#endif #if CONFIG_64BIT PRINT("Got \nexception at %016lx\012") -#endif +#endif .endm .macro __BUILD_count exception diff --git a/arch/mips/kernel/ioctl32.c b/arch/mips/kernel/ioctl32.c index 519cd5d0aebb..c069719ff0d8 100644 --- a/arch/mips/kernel/ioctl32.c +++ b/arch/mips/kernel/ioctl32.c @@ -27,7 +27,7 @@ long sys_ioctl(unsigned int fd, unsigned int cmd, unsigned long arg); #include "compat_ioctl.c" typedef int (* ioctl32_handler_t)(unsigned int, unsigned int, unsigned long, struct file *); - + #define COMPATIBLE_IOCTL(cmd) HANDLE_IOCTL((cmd),sys_ioctl) #define HANDLE_IOCTL(cmd,handler) { (cmd), (ioctl32_handler_t)(handler), NULL }, #define IOCTL_TABLE_START \ diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 441157a1f994..7d93992e462c 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -77,7 +77,7 @@ int show_interrupts(struct seq_file *p, void *v) if (i < NR_IRQS) { spin_lock_irqsave(&irq_desc[i].lock, flags); action = irq_desc[i].action; - if (!action) + if (!action) goto skip; seq_printf(p, "%3d: ",i); #ifndef CONFIG_SMP diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index 993abc868e54..4613219dd73e 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -313,7 +313,7 @@ asmlinkage int sys32_sysinfo(struct sysinfo32 *info) struct sysinfo s; int ret, err; mm_segment_t old_fs = get_fs (); - + set_fs (KERNEL_DS); ret = sys_sysinfo(&s); set_fs (old_fs); @@ -560,7 +560,7 @@ struct ipc64_perm32 { compat_gid_t gid; compat_uid_t cuid; compat_gid_t cgid; - compat_mode_t mode; + compat_mode_t mode; unsigned short seq; unsigned short __pad1; unsigned int __unused1; @@ -1334,17 +1334,17 @@ asmlinkage int sys32_sendfile(int out_fd, int in_fd, compat_off_t *offset, mm_segment_t old_fs = get_fs(); int ret; off_t of; - + if (offset && get_user(of, offset)) return -EFAULT; - + set_fs(KERNEL_DS); ret = sys_sendfile(out_fd, in_fd, offset ? &of : NULL, count); set_fs(old_fs); - + if (offset && put_user(of, offset)) return -EFAULT; - + return ret; } @@ -1362,11 +1362,11 @@ static unsigned char socketcall_nargs[18]={AL(0),AL(3),AL(3),AL(3),AL(2),AL(3), #undef AL /* - * System call vectors. + * System call vectors. * * Argument checking cleaned up. Saved 20% in size. * This function doesn't need to set the kernel lock because - * it is set by the callees. + * it is set by the callees. */ asmlinkage long sys32_socketcall(int call, unsigned int *args32) @@ -1402,11 +1402,11 @@ asmlinkage long sys32_socketcall(int call, unsigned int *args32) /* copy_from_user should be SMP safe. */ if (copy_from_user(a, args32, socketcall_nargs[call])) return -EFAULT; - + a0=a[0]; a1=a[1]; - - switch(call) + + switch(call) { case SYS_SOCKET: err = sys_socket(a0,a1,a[2]); diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S index 243e7b629af6..f10019640ee9 100644 --- a/arch/mips/kernel/r2300_switch.S +++ b/arch/mips/kernel/r2300_switch.S @@ -35,7 +35,7 @@ /* * FPU context is saved iff the process has used it's FPU in the current * time slice as indicated by TIF_USEDFPU. In any case, the CU1 bit for user - * space STATUS register should be 0, so that a process *always* starts its + * space STATUS register should be 0, so that a process *always* starts its * userland with FPU disabled after each context switch. * * FPU will be enabled as soon as the process accesses FPU again, through @@ -55,7 +55,7 @@ LEAF(resume) cpu_save_nonscratch a0 sw ra, THREAD_REG31(a0) - /* + /* * check if we need to save FPU registers */ lw t3, TASK_THREAD_INFO(a0) diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index 175dd1fcbb33..e02b7722ccb8 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -33,7 +33,7 @@ /* * FPU context is saved iff the process has used it's FPU in the current * time slice as indicated by _TIF_USEDFPU. In any case, the CU1 bit for user - * space STATUS register should be 0, so that a process *always* starts its + * space STATUS register should be 0, so that a process *always* starts its * userland with FPU disabled after each context switch. * * FPU will be enabled as soon as the process accesses FPU again, through @@ -164,7 +164,7 @@ LEAF(_init_fpu) dmtc1 t1, $f31 1: #endif - + #ifdef CONFIG_CPU_MIPS32 mtc1 t1, $f0 mtc1 t1, $f1 diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index f6875f023a29..8ddfbd8d425a 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -558,7 +558,7 @@ static inline int setup_sigcontext32(struct pt_regs *regs, if (!used_math()) goto out; - /* + /* * Save FPU state to signal context. Signal handler will "inherit" * current FPU state. */ diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index e830d788c106..482ac310c937 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -15,7 +15,7 @@ SECTIONS /* This is the value for an Origin kernel, taken from an IRIX kernel. */ /* . = 0xc00000000001c000; */ - /* Set the vaddr for the text segment to a value + /* Set the vaddr for the text segment to a value >= 0xa800 0000 0001 9000 if no symmon is going to configured >= 0xa800 0000 0030 0000 otherwise */ diff --git a/arch/mips/lasat/at93c.c b/arch/mips/lasat/at93c.c index f6add041ebec..ca26e554615e 100644 --- a/arch/mips/lasat/at93c.c +++ b/arch/mips/lasat/at93c.c @@ -1,7 +1,7 @@ -/* +/* * Atmel AT93C46 serial eeprom driver * - * Brian Murphy + * Brian Murphy * */ #include @@ -21,12 +21,12 @@ struct at93c_defs *at93c; -static void at93c_reg_write(u32 val) +static void at93c_reg_write(u32 val) { *at93c->reg = val; } -static u32 at93c_reg_read(void) +static u32 at93c_reg_read(void) { u32 tmp = *at93c->reg; return tmp; @@ -81,7 +81,7 @@ static u8 at93c_read_byte(void) } static void at93c_write_bits(u32 data, int size) -{ +{ int i; int shift = size - 1; u32 mask = (1 << shift); @@ -90,7 +90,7 @@ static void at93c_write_bits(u32 data, int size) at93c_write_databit((data & mask) >> shift); data <<= 1; } -} +} static void at93c_init_op(void) { @@ -104,8 +104,8 @@ static void at93c_end_op(void) lasat_ndelay(250); } -static void at93c_wait(void) -{ +static void at93c_wait(void) +{ at93c_init_op(); while (!at93c_read_databit()) ; diff --git a/arch/mips/lasat/at93c.h b/arch/mips/lasat/at93c.h index a912ac2171b0..cfe2f99b1d44 100644 --- a/arch/mips/lasat/at93c.h +++ b/arch/mips/lasat/at93c.h @@ -1,7 +1,7 @@ -/* +/* * Atmel AT93C46 serial eeprom driver * - * Brian Murphy + * Brian Murphy * */ diff --git a/arch/mips/lasat/ds1603.c b/arch/mips/lasat/ds1603.c index 7bbf6cf923c9..9d7812e03dcd 100644 --- a/arch/mips/lasat/ds1603.c +++ b/arch/mips/lasat/ds1603.c @@ -1,7 +1,7 @@ -/* - * Dallas Semiconductors 1603 RTC driver +/* + * Dallas Semiconductors 1603 RTC driver * - * Brian Murphy + * Brian Murphy * */ #include @@ -20,12 +20,12 @@ struct ds_defs *ds1603 = NULL; /* HW specific register functions */ -static void rtc_reg_write(unsigned long val) +static void rtc_reg_write(unsigned long val) { *ds1603->reg = val; } -static unsigned long rtc_reg_read(void) +static unsigned long rtc_reg_read(void) { unsigned long tmp = *ds1603->reg; return tmp; @@ -80,7 +80,7 @@ static unsigned int rtc_read_databit(void) { unsigned int data; - data = (rtc_datareg_read() & (1 << ds1603->data_read_shift)) + data = (rtc_datareg_read() & (1 << ds1603->data_read_shift)) >> ds1603->data_read_shift; rtc_cycle_clock(rtc_reg_read()); return data; diff --git a/arch/mips/lasat/ds1603.h b/arch/mips/lasat/ds1603.h index 55f3b0423c20..c2e5c76a379d 100644 --- a/arch/mips/lasat/ds1603.h +++ b/arch/mips/lasat/ds1603.h @@ -1,7 +1,7 @@ -/* - * Dallas Semiconductors 1603 RTC driver +/* + * Dallas Semiconductors 1603 RTC driver * - * Brian Murphy + * Brian Murphy * */ #ifndef __DS1603_H diff --git a/arch/mips/lasat/image/Makefile b/arch/mips/lasat/image/Makefile index 18b6430f11be..35ecd6483ef6 100644 --- a/arch/mips/lasat/image/Makefile +++ b/arch/mips/lasat/image/Makefile @@ -21,7 +21,7 @@ LDSCRIPT= -L$(obj) -Tromscript.normal HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \ -D_kernel_entry=0x$(KERNEL_ENTRY) \ -D VERSION="\"$(Version)\"" \ - -D TIMESTAMP=$(shell date +%s) + -D TIMESTAMP=$(shell date +%s) $(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE) $(CC) -fno-pic $(HEAD_DEFINES) -I$(TOPDIR)/include -c -o $@ $< diff --git a/arch/mips/lasat/image/head.S b/arch/mips/lasat/image/head.S index 426bd7de17bb..efb95f2609c2 100644 --- a/arch/mips/lasat/image/head.S +++ b/arch/mips/lasat/image/head.S @@ -27,5 +27,5 @@ reldate: .word TIMESTAMP .org 0x50 -release: +release: .string VERSION diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index 1148a2d20aa7..c90da1639440 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c @@ -15,7 +15,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * Routines for generic manipulation of the interrupts found on the + * Routines for generic manipulation of the interrupts found on the * Lasat boards. */ #include @@ -101,7 +101,7 @@ static unsigned long get_int_status_100(void) return *lasat_int_status & *lasat_int_mask; } -static unsigned long get_int_status_200(void) +static unsigned long get_int_status_200(void) { unsigned long int_status; diff --git a/arch/mips/lasat/lasat_board.c b/arch/mips/lasat/lasat_board.c index 8c784bcf1111..fc9b0e2a6be1 100644 --- a/arch/mips/lasat/lasat_board.c +++ b/arch/mips/lasat/lasat_board.c @@ -67,7 +67,7 @@ static void init_flash_sizes(void) if (mips_machtype == MACH_LASAT_100) { lasat_board_info.li_flash_base = 0x1e000000; - + lb[LASAT_MTD_BOOTLOADER] = 0x1e400000; if (lasat_board_info.li_flash_size > 0x200000) { @@ -103,7 +103,7 @@ int lasat_init_board_info(void) memset(&lasat_board_info, 0, sizeof(lasat_board_info)); /* First read the EEPROM info */ - EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info, + EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info, sizeof(struct lasat_eeprom_struct)); /* Check the CRC */ @@ -188,7 +188,7 @@ int lasat_init_board_info(void) case 0x1: lasat_board_info.li_cpu_hz = lasat_board_info.li_bus_hz + - (lasat_board_info.li_bus_hz >> 1); + (lasat_board_info.li_bus_hz >> 1); break; case 0x2: lasat_board_info.li_cpu_hz = @@ -271,7 +271,7 @@ void lasat_write_eeprom_info(void) lasat_board_info.li_eeprom_info.crc32 = crc; /* Write the EEPROM info */ - EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info, + EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info, sizeof(struct lasat_eeprom_struct)); } diff --git a/arch/mips/lasat/picvue.c b/arch/mips/lasat/picvue.c index 5637cd153926..9ae82c3ffb07 100644 --- a/arch/mips/lasat/picvue.c +++ b/arch/mips/lasat/picvue.c @@ -1,7 +1,7 @@ -/* +/* * Picvue PVC160206 display driver * - * Brian Murphy + * Brian Murphy * */ #include @@ -24,12 +24,12 @@ struct pvc_defs *picvue = NULL; DECLARE_MUTEX(pvc_sem); -static void pvc_reg_write(u32 val) +static void pvc_reg_write(u32 val) { *picvue->reg = val; } -static u32 pvc_reg_read(void) +static u32 pvc_reg_read(void) { u32 tmp = *picvue->reg; return tmp; @@ -65,12 +65,12 @@ static u8 pvc_read_data(void) { u32 data = pvc_reg_read(); u8 byte; - data |= picvue->rw; + data |= picvue->rw; data &= ~picvue->rs; pvc_reg_write(data); ndelay(40); byte = pvc_read_byte(data); - data |= picvue->rs; + data |= picvue->rs; pvc_reg_write(data); return byte; } diff --git a/arch/mips/lasat/picvue.h b/arch/mips/lasat/picvue.h index 74a39039135d..2a96bf971897 100644 --- a/arch/mips/lasat/picvue.h +++ b/arch/mips/lasat/picvue.h @@ -1,7 +1,7 @@ -/* +/* * Picvue PVC160206 display driver * - * Brian Murphy + * Brian Murphy * */ #include diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c index eaa2b4625124..cce7cddcdb08 100644 --- a/arch/mips/lasat/picvue_proc.c +++ b/arch/mips/lasat/picvue_proc.c @@ -1,7 +1,7 @@ -/* +/* * Picvue PVC160206 display driver * - * Brian Murphy + * Brian Murphy * */ #include @@ -51,10 +51,10 @@ static int pvc_proc_read_line(char *page, char **start, page += sprintf(page, "%s\n", pvc_lines[lineno]); up(&pvc_sem); - return page - origpage; + return page - origpage; } -static int pvc_proc_write_line(struct file *file, const char *buffer, +static int pvc_proc_write_line(struct file *file, const char *buffer, unsigned long count, void *data) { int origcount = count; @@ -119,7 +119,7 @@ static int pvc_proc_read_scroll(char *page, char **start, page += sprintf(page, "%d\n", scroll_dir * scroll_interval); up(&pvc_sem); - return page - origpage; + return page - origpage; } diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c index ca62881c9e52..88c7ab871ec4 100644 --- a/arch/mips/lasat/prom.c +++ b/arch/mips/lasat/prom.c @@ -42,7 +42,7 @@ static void null_prom_putc(char c) /* these are functions provided by the bootloader */ static void (* prom_putc)(char c) = null_prom_putc; void (* prom_printf)(const char * fmt, ...) = null_prom_printf; -void (* prom_display)(const char *string, int pos, int clear) = +void (* prom_display)(const char *string, int pos, int clear) = null_prom_display; void (* prom_monitor)(void) = null_prom_monitor; diff --git a/arch/mips/lasat/reset.c b/arch/mips/lasat/reset.c index 37e4912ee1c8..8d7d7a454f9a 100644 --- a/arch/mips/lasat/reset.c +++ b/arch/mips/lasat/reset.c @@ -1,4 +1,4 @@ -/* +/* * Thomas Horsten * Copyright (C) 2000 LASAT Networks A/S. * diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c index e371ed5cbe34..f2604fab9a99 100644 --- a/arch/mips/lasat/setup.c +++ b/arch/mips/lasat/setup.c @@ -105,7 +105,7 @@ static int lasat_panic_prom_monitor(struct notifier_block *this, return NOTIFY_DONE; } -static struct notifier_block lasat_panic_block[] = +static struct notifier_block lasat_panic_block[] = { { lasat_panic_display, NULL, INT_MAX }, { lasat_panic_prom_monitor, NULL, INT_MIN } @@ -120,7 +120,7 @@ static void lasat_timer_setup(struct irqaction *irq) { write_c0_compare( - read_c0_count() + + read_c0_count() + mips_hpt_frequency / HZ); change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5); } diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c index 1c0cc620a43f..8ff43a1c1e99 100644 --- a/arch/mips/lasat/sysctl.c +++ b/arch/mips/lasat/sysctl.c @@ -37,14 +37,14 @@ static DECLARE_MUTEX(lasat_info_sem); -/* Strategy function to write EEPROM after changing string entry */ +/* Strategy function to write EEPROM after changing string entry */ int sysctl_lasatstring(ctl_table *table, int *name, int nlen, void *oldval, size_t *oldlenp, void *newval, size_t newlen, void **context) { int r; down(&lasat_info_sem); - r = sysctl_string(table, name, + r = sysctl_string(table, name, nlen, oldval, oldlenp, newval, newlen, context); if (r < 0) { up(&lasat_info_sem); @@ -74,7 +74,7 @@ int proc_dolasatstring(ctl_table *table, int write, struct file *filp, return 0; } -/* proc function to write EEPROM after changing int entry */ +/* proc function to write EEPROM after changing int entry */ int proc_dolasatint(ctl_table *table, int write, struct file *filp, void *buffer, size_t *lenp, loff_t *ppos) { @@ -93,7 +93,7 @@ int proc_dolasatint(ctl_table *table, int write, struct file *filp, static int rtctmp; #ifdef CONFIG_DS1603 -/* proc function to read/write RealTime Clock */ +/* proc function to read/write RealTime Clock */ int proc_dolasatrtc(ctl_table *table, int write, struct file *filp, void *buffer, size_t *lenp, loff_t *ppos) { @@ -165,9 +165,9 @@ static char lasat_bcastaddr[16]; void update_bcastaddr(void) { unsigned int ip; - - ip = (lasat_board_info.li_eeprom_info.ipaddr & - lasat_board_info.li_eeprom_info.netmask) | + + ip = (lasat_board_info.li_eeprom_info.ipaddr & + lasat_board_info.li_eeprom_info.netmask) | ~lasat_board_info.li_eeprom_info.netmask; sprintf(lasat_bcastaddr, "%d.%d.%d.%d", @@ -205,7 +205,7 @@ int proc_lasat_ip(ctl_table *table, int write, struct file *filp, break; len++; } - if (len >= sizeof(proc_lasat_ipbuf)-1) + if (len >= sizeof(proc_lasat_ipbuf)-1) len = sizeof(proc_lasat_ipbuf) - 1; if (copy_from_user(proc_lasat_ipbuf, buffer, len)) { @@ -249,8 +249,8 @@ int proc_lasat_ip(ctl_table *table, int write, struct file *filp, } #endif /* defined(CONFIG_INET) */ -static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen, - void *oldval, size_t *oldlenp, +static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen, + void *oldval, size_t *oldlenp, void *newval, size_t newlen, void **context) { @@ -293,7 +293,7 @@ int proc_lasat_eeprom_value(ctl_table *table, int write, struct file *filp, if (!strcmp(filp->f_dentry->d_name.name, "debugaccess")) lasat_board_info.li_eeprom_info.debugaccess = lasat_board_info.li_debugaccess; } - lasat_write_eeprom_info(); + lasat_write_eeprom_info(); up(&lasat_info_sem); return 0; } @@ -316,8 +316,8 @@ static ctl_table lasat_table[] = { 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec}, {LASAT_NETMASK, "netmask", &lasat_board_info.li_eeprom_info.netmask, sizeof(int), 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec}, - {LASAT_BCAST, "bcastaddr", &lasat_bcastaddr, - sizeof(lasat_bcastaddr), 0600, NULL, + {LASAT_BCAST, "bcastaddr", &lasat_bcastaddr, + sizeof(lasat_bcastaddr), 0600, NULL, &proc_dostring, &sysctl_string}, #endif {LASAT_PASSWORD, "passwd_hash", &lasat_board_info.li_eeprom_info.passwd_hash, sizeof(lasat_board_info.li_eeprom_info.passwd_hash), diff --git a/arch/mips/lib-32/Makefile b/arch/mips/lib-32/Makefile index fd6a2bafdfcf..ad285786e74b 100644 --- a/arch/mips/lib-32/Makefile +++ b/arch/mips/lib-32/Makefile @@ -2,7 +2,7 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial.o memset.o watch.o +lib-y += csum_partial.o memset.o watch.o obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o diff --git a/arch/mips/lib-64/Makefile b/arch/mips/lib-64/Makefile index fd6a2bafdfcf..ad285786e74b 100644 --- a/arch/mips/lib-64/Makefile +++ b/arch/mips/lib-64/Makefile @@ -2,7 +2,7 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial.o memset.o watch.o +lib-y += csum_partial.o memset.o watch.o obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S index 00d73be7dc27..90ee8d43261f 100644 --- a/arch/mips/lib/memcpy.S +++ b/arch/mips/lib/memcpy.S @@ -101,7 +101,7 @@ #define NBYTES 8 #define LOG_NBYTES 3 -/* +/* * As we are sharing code base with the mips32 tree (which use the o32 ABI * register definitions). We need to redefine the register definitions from * the n64 ABI register naming to the o32 ABI register naming. @@ -118,7 +118,7 @@ #define t5 $13 #define t6 $14 #define t7 $15 - + #else #define LOAD lw diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c index 8f1d875217a2..19d4b0792460 100644 --- a/arch/mips/mips-boards/atlas/atlas_int.c +++ b/arch/mips/mips-boards/atlas/atlas_int.c @@ -122,7 +122,7 @@ void __init arch_init_irq(void) int i; atlas_hw0_icregs = (struct atlas_ictrl_regs *)ioremap (ATLAS_ICTRL_REGS_BASE, sizeof(struct atlas_ictrl_regs *)); - + /* * Mask out all interrupt by writing "1" to all bit position in * the interrupt reset reg. diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index 31caf0603a3f..311155d1d3ed 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -200,7 +200,7 @@ void __init kgdb_config (void) generic_putDebugChar = saa9730_putDebugChar; generic_getDebugChar = saa9730_getDebugChar; } - else + else #endif { speed = rs_kgdb_hook(line, speed); @@ -243,7 +243,7 @@ void __init prom_init(void) mips_revision_corid = MIPS_REVISION_CORID; if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { - if (BONITO_PCIDID == 0x0001df53 || + if (BONITO_PCIDID == 0x0001df53 || BONITO_PCIDID == 0x0003df53) mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; else @@ -310,7 +310,7 @@ void __init prom_init(void) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_EMUL_MSC: - _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); + _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); #ifdef CONFIG_CPU_LITTLE_ENDIAN MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index fe7fc17305a6..16315444dd5a 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -89,7 +89,7 @@ static unsigned int __init estimate_cpu_frequency(void) * really calculate the timer frequency * For now we hardwire the SEAD board frequency to 12MHz. */ - + if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) count = 12000000; diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c index 3377e66de9eb..df6db6419ae9 100644 --- a/arch/mips/mips-boards/malta/malta_setup.c +++ b/arch/mips/mips-boards/malta/malta_setup.c @@ -149,15 +149,15 @@ static int __init malta_setup(void) argptr = prom_getcmdline(); if (strstr(argptr, "iobcuncached")) { BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; - BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); printk("Disabled Bonito IOBC coherency\n"); } else { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; - BONITO_PCIMEMBASECFG |= - (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); printk("Disabled Bonito IOBC coherency\n"); } diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 20d40725e5bb..5ea84bc98c6a 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -126,13 +126,13 @@ static inline void tx49_blast_icache32(void) CACHE32_UNROLL32_ALIGN2; /* I'm in even chunk. blast odd chunks */ - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start + 0x400; addr < end; addr += 0x400 * 2) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start + 0x400; addr < end; addr += 0x400 * 2) cache32_unroll32(addr|ws,Index_Invalidate_I); CACHE32_UNROLL32_ALIGN; /* I'm in odd chunk. blast even chunks */ - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400 * 2) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400 * 2) cache32_unroll32(addr|ws,Index_Invalidate_I); } @@ -156,13 +156,13 @@ static inline void tx49_blast_icache32_page_indexed(unsigned long page) CACHE32_UNROLL32_ALIGN2; /* I'm in even chunk. blast odd chunks */ - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start + 0x400; addr < end; addr += 0x400 * 2) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start + 0x400; addr < end; addr += 0x400 * 2) cache32_unroll32(addr|ws,Index_Invalidate_I); CACHE32_UNROLL32_ALIGN; /* I'm in odd chunk. blast even chunks */ - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400 * 2) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400 * 2) cache32_unroll32(addr|ws,Index_Invalidate_I); } diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c index ab30afd63b32..502f68c664b2 100644 --- a/arch/mips/mm/c-sb1.c +++ b/arch/mips/mm/c-sb1.c @@ -270,7 +270,7 @@ static void local_sb1_flush_icache_range(unsigned long start, __sb1_writeback_inv_dcache_all(); else __sb1_writeback_inv_dcache_range(start, end); - + /* Just flush the whole icache if the range is big enough */ if ((end - start) > icache_range_cutoff) __sb1_flush_icache_all(); diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c index 13d96d62764e..7166ffe63502 100644 --- a/arch/mips/mm/cerr-sb1.c +++ b/arch/mips/mm/cerr-sb1.c @@ -25,7 +25,7 @@ #include #include #endif - + /* SB1 definitions */ /* XXX should come from config1 XXX */ @@ -136,14 +136,14 @@ static inline void breakout_cerrd(unsigned int val) #ifndef CONFIG_SIBYTE_BUS_WATCHER -static void check_bus_watcher(void) -{ +static void check_bus_watcher(void) +{ uint32_t status, l2_err, memio_err; /* Destructive read, clears register and interrupt */ status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); /* Bit 31 is always on, but there's no #define for that */ - if (status & ~(1UL << 31)) { + if (status & ~(1UL << 31)) { l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); @@ -153,14 +153,14 @@ static void check_bus_watcher(void) (int)(G_SCD_BERR_TID(status) >> 6), (int)G_SCD_BERR_RID(status), (int)G_SCD_BERR_DCODE(status)); - } else { - prom_printf("Bus watcher indicates no error\n"); - } -} -#else -extern void check_bus_watcher(void); -#endif - + } else { + prom_printf("Bus watcher indicates no error\n"); + } +} +#else +extern void check_bus_watcher(void); +#endif + asmlinkage void sb1_cache_error(void) { uint64_t cerr_dpa; diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c index 9895e32b0fce..59e54f12212e 100644 --- a/arch/mips/mm/dma-noncoherent.c +++ b/arch/mips/mm/dma-noncoherent.c @@ -162,7 +162,7 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, for (i = 0; i < nents; i++, sg++) { unsigned long addr; - + addr = (unsigned long) page_address(sg->page); if (addr) __dma_sync(addr + sg->offset, sg->length, direction); @@ -230,9 +230,9 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { unsigned long addr; - + BUG_ON(direction == DMA_NONE); - + addr = dma_handle + PAGE_OFFSET; __dma_sync(addr, size, direction); } @@ -282,9 +282,9 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction direction) { int i; - + BUG_ON(direction == DMA_NONE); - + /* Make sure that gcc doesn't leave the empty loop body. */ for (i = 0; i < nelems; i++, sg++) __dma_sync((unsigned long)page_address(sg->page), diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c index b63e1ca350f5..1b6df7133c1e 100644 --- a/arch/mips/mm/pg-sb1.c +++ b/arch/mips/mm/pg-sb1.c @@ -198,7 +198,7 @@ static inline void copy_page_cpu(void *to, void *from) /* * Pad descriptors to cacheline, since each is exclusively owned by a - * particular CPU. + * particular CPU. */ typedef struct dmadscr_s { u64 dscr_a; diff --git a/arch/mips/momentum/jaguar_atx/int-handler.S b/arch/mips/momentum/jaguar_atx/int-handler.S index 43fd5a58077c..55bc789733f2 100644 --- a/arch/mips/momentum/jaguar_atx/int-handler.S +++ b/arch/mips/momentum/jaguar_atx/int-handler.S @@ -27,11 +27,11 @@ SAVE_ALL CLI .set at - mfc0 t0, CP0_CAUSE + mfc0 t0, CP0_CAUSE mfc0 t2, CP0_STATUS and t0, t2 - + andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */ bnez t1, ll_sw0_irq andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */ @@ -103,25 +103,25 @@ ll_pcia_irq: move a1, sp jal do_IRQ j ret_from_irq - + ll_pcib_irq: li a0, 5 move a1, sp jal do_IRQ j ret_from_irq - + ll_uart_irq: li a0, 6 move a1, sp jal do_IRQ j ret_from_irq - + ll_cputimer_irq: li a0, 7 move a1, sp jal ll_timer_interrupt j ret_from_irq - + ll_mv64340_decode_irq: move a0, sp jal ll_mv64340_irq diff --git a/arch/mips/momentum/jaguar_atx/prom.c b/arch/mips/momentum/jaguar_atx/prom.c index 827960802b8f..14ae2e713585 100644 --- a/arch/mips/momentum/jaguar_atx/prom.c +++ b/arch/mips/momentum/jaguar_atx/prom.c @@ -64,7 +64,7 @@ static u8 exchange_bit(u8 val, u8 cs) /* turn the clock off and read-strobe */ JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); - + /* return the data */ return ((JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); } diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c index 3cf1e46aa4b8..90288cf2b1e0 100644 --- a/arch/mips/momentum/jaguar_atx/setup.c +++ b/arch/mips/momentum/jaguar_atx/setup.c @@ -451,7 +451,7 @@ static int __init momenco_jaguar_atx_setup(void) #ifdef GEMDEBUG_TRACEBUFFER { unsigned int tbControl; - tbControl = + tbControl = 0 << 26 | /* post trigger delay 0 */ 0x2 << 16 | /* sequential trace mode */ // 0x0 << 16 | /* non-sequential trace mode */ diff --git a/arch/mips/momentum/ocelot_c/int-handler.S b/arch/mips/momentum/ocelot_c/int-handler.S index 2f2430648abc..52349d9bf1be 100644 --- a/arch/mips/momentum/ocelot_c/int-handler.S +++ b/arch/mips/momentum/ocelot_c/int-handler.S @@ -27,11 +27,11 @@ SAVE_ALL CLI .set at - mfc0 t0, CP0_CAUSE + mfc0 t0, CP0_CAUSE mfc0 t2, CP0_STATUS and t0, t2 - + andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */ bnez t1, ll_sw0_irq andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */ @@ -83,7 +83,7 @@ ll_pmc_irq: move a1, sp jal do_IRQ j ret_from_irq - + ll_cpci_decode_irq: move a0, sp jal ll_cpci_irq @@ -99,4 +99,4 @@ ll_cputimer_irq: move a1, sp jal do_IRQ j ret_from_irq - + diff --git a/arch/mips/momentum/ocelot_c/prom.c b/arch/mips/momentum/ocelot_c/prom.c index 375877aebcf6..5b6809724b15 100644 --- a/arch/mips/momentum/ocelot_c/prom.c +++ b/arch/mips/momentum/ocelot_c/prom.c @@ -67,7 +67,7 @@ static u8 exchange_bit(u8 val, u8 cs) /* turn the clock off and read-strobe */ OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); - + /* return the data */ return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); } diff --git a/arch/mips/pci/fixup-ddb5074.c b/arch/mips/pci/fixup-ddb5074.c index b345e528a53c..5a4a7c239c42 100644 --- a/arch/mips/pci/fixup-ddb5074.c +++ b/arch/mips/pci/fixup-ddb5074.c @@ -5,7 +5,7 @@ static void ddb5074_fixup(struct pci_dev *dev) { extern struct pci_dev *pci_pmu; u8 t8; - + pci_pmu = dev; /* for LEDs D2 and D3 */ /* Program the lines for LEDs D2 and D3 to output */ pci_read_config_byte(dev, 0x7d, &t8); diff --git a/arch/mips/pci/fixup-ddb5477.c b/arch/mips/pci/fixup-ddb5477.c index 6abdc88bab1e..2f1444e60654 100644 --- a/arch/mips/pci/fixup-ddb5477.c +++ b/arch/mips/pci/fixup-ddb5477.c @@ -65,7 +65,7 @@ static void ddb5477_amd_lance_fixup(struct pci_dev *dev) ioaddr = pci_resource_start(dev, 0); inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */ - + /* bcr_18 |= 0x0800 */ outw(18, ioaddr + PCNET32_WIO_RAP); temp = inw(ioaddr + PCNET32_WIO_BDP); diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c index b9296d9942b3..bf2c41d1e9c5 100644 --- a/arch/mips/pci/fixup-malta.c +++ b/arch/mips/pci/fixup-malta.c @@ -56,7 +56,7 @@ static void __init malta_piix_func0_fixup(struct pci_dev *pdev) 0, 0, 0, 3, 4, 5, 6, 7, 0, 9, 10, 11, - 12, 0, 14, 15 + 12, 0, 14, 15 }; int i; diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index de4e443da208..ceeb1860895a 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -7,7 +7,7 @@ * Author: MontaVista Software, Inc. * ppopov@mvista.com or source@mvista.com * - * Copyright (C) 2000-2001 Toshiba Corporation + * Copyright (C) 2000-2001 Toshiba Corporation * * Copyright (C) 2004 MontaVista Software Inc. * Author: Manish Lachwani (mlachwani@mvista.com) diff --git a/arch/mips/pci/fixup-sni.c b/arch/mips/pci/fixup-sni.c index c8ef01a017cc..a176f2ca8656 100644 --- a/arch/mips/pci/fixup-sni.c +++ b/arch/mips/pci/fixup-sni.c @@ -32,7 +32,7 @@ * Device 4: Unused * Device 5: Slot 2 * Device 6: Slot 3 - * Device 7: Slot 4 + * Device 7: Slot 4 * * Documentation says the VGA is device 5 and device 3 is unused but that * seem to be a documentation error. At least on my RM200C the Cirrus diff --git a/arch/mips/pci/ops-ddb5477.c b/arch/mips/pci/ops-ddb5477.c index e955443fedf9..0406b50a37d8 100644 --- a/arch/mips/pci/ops-ddb5477.c +++ b/arch/mips/pci/ops-ddb5477.c @@ -127,7 +127,7 @@ static inline void ddb_close_config_base(struct pci_config_swap *swap) } static int read_config_dword(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, + struct pci_bus *bus, u32 devfn, u32 where, u32 * val) { u32 bus_num, slot_num, func_num; @@ -153,7 +153,7 @@ static int read_config_dword(struct pci_config_swap *swap, } static int read_config_word(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, + struct pci_bus *bus, u32 devfn, u32 where, u16 * val) { int status; diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index 2a9d7227fe87..7688b7711329 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c @@ -1,16 +1,16 @@ /* * Copyright 2001 MontaVista Software Inc. * Author: MontaVista Software, Inc. - * ahennessy@mvista.com + * ahennessy@mvista.com * - * Copyright (C) 2000-2001 Toshiba Corporation + * Copyright (C) 2000-2001 Toshiba Corporation * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) * * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c * * Define the pci_ops for the Toshiba rbtx4927 * - * Much of the code is derived from the original DDB5074 port by + * Much of the code is derived from the original DDB5074 port by * Geert Uytterhoeven * * Copyright 2004 MontaVista Software Inc. diff --git a/arch/mips/pci/pci-ddb5477.c b/arch/mips/pci/pci-ddb5477.c index 4ddd53eaf656..826d653184e5 100644 --- a/arch/mips/pci/pci-ddb5477.c +++ b/arch/mips/pci/pci-ddb5477.c @@ -76,7 +76,7 @@ struct pci_controller ddb5477_io_controller = { */ /* - * irq mapping : device -> pci int # -> vrc4377 irq# , + * irq mapping : device -> pci int # -> vrc4377 irq# , * ddb5477 board manual page 4 and vrc5477 manual page 46 */ @@ -137,9 +137,9 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) unsigned char *slot_irq_map; unsigned char irq; - /* + /* * We ignore the swizzled slot and pin values. The original - * pci_fixup_irq() codes largely base irq number on the dev slot + * pci_fixup_irq() codes largely base irq number on the dev slot * numbers because except for one case they are unique even * though there are multiple pci buses. */ @@ -160,7 +160,7 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) if (mips_machtype == MACH_NEC_ROCKHOPPERII) { /* hack to distinquish overlapping slot 20s, one - * on bus 0 (ALI USB on the M1535 on the backplane), + * on bus 0 (ALI USB on the M1535 on the backplane), * and one on bus 2 (NEC USB controller on the CPU board) * Make the M1535 USB - ISA IRQ number 9. */ diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 8141dffac241..8a5b52250bda 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -132,7 +132,7 @@ static int __init pcibios_init(void) hose->need_domain_info = need_domain_info; next_busno = bus->subordinate + 1; /* Don't allow 8-bit bus number overflow inside the hose - - reserve some space for bridges. */ + reserve some space for bridges. */ if (next_busno > 224) { next_busno = 0; need_domain_info = 1; @@ -260,7 +260,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { pci_read_bridge_bases(bus); pcibios_fixup_device_resources(dev, bus); - } + } for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { struct pci_dev *dev = pci_dev_b(ln); diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c index b067988614c3..97862f45496d 100644 --- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c +++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c @@ -30,7 +30,7 @@ * * This code reads the ATMEL 24CXX EEPROM. The PMC-Sierra Yosemite board uses the ATMEL * 24C32/24C64 which uses two byte addressing as compared to 24C16. Note that this program - * uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are + * uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are * expected to have a connectivity from the EEPROM to the serial port. This program does * __not__ communicate using the I2C protocol */ @@ -64,14 +64,14 @@ static void send_ack(void) static void send_byte(unsigned char byte) { int i = 0; - - for (i = 7; i >= 0; i--) + + for (i = 7; i >= 0; i--) send_bit((byte >> i) & 0x01); } - + static void send_start(void) { - sda_hi; + sda_hi; delay(TXX); scl_hi; delay(TXX); @@ -114,9 +114,9 @@ static unsigned char recv_byte(void) { int i; unsigned char byte=0; - for (i=7;i>=0;i--) + for (i=7;i>=0;i--) byte |= (recv_bit() << i); - + return byte; } diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h index d27566d99ffc..c19f01a32045 100644 --- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h +++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h @@ -27,7 +27,7 @@ */ /* - * Header file for atmel_read_eeprom.c + * Header file for atmel_read_eeprom.c */ #include @@ -46,7 +46,7 @@ #define DEFAULT_PORT "/dev/ttyS0" /* Port to open */ #define TXX 0 /* Dummy loop for spinning */ -#define BLOCK_SEL 0x00 +#define BLOCK_SEL 0x00 #define SLAVE_ADDR 0xa0 #define READ_BIT 0x01 #define WRITE_BIT 0x00 diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c index 0ab4abf65d58..fa0e719c5bd1 100644 --- a/arch/mips/sgi-ip22/ip22-eisa.c +++ b/arch/mips/sgi-ip22/ip22-eisa.c @@ -242,7 +242,7 @@ int __init ip22_eisa_init(void) int i, c; char *str; u8 *slot_addr; - + if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) { printk(KERN_INFO "EISA: bus not present.\n"); return 1; diff --git a/arch/mips/sgi-ip22/ip22-hpc.c b/arch/mips/sgi-ip22/ip22-hpc.c index c0afeccb08c4..5c00cdd20d8e 100644 --- a/arch/mips/sgi-ip22/ip22-hpc.c +++ b/arch/mips/sgi-ip22/ip22-hpc.c @@ -49,7 +49,7 @@ void __init sgihpc_init(void) sgint = &sgioc->int3; system_type = "SGI Indy"; } - + sgi_ioc_reset = (SGIOC_RESET_PPORT | SGIOC_RESET_KBDMOUSE | SGIOC_RESET_EISA | SGIOC_RESET_ISDN | SGIOC_RESET_LC0OFF); diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index ea2844d29e6e..d16fb43b1a93 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c @@ -28,7 +28,7 @@ /* #define DEBUG_SGINT */ /* So far nothing hangs here */ -#undef USE_LIO3_IRQ +#undef USE_LIO3_IRQ struct sgint_regs *sgint; @@ -272,32 +272,32 @@ void indy_buserror_irq(struct pt_regs *regs) irq_exit(); } -static struct irqaction local0_cascade = { +static struct irqaction local0_cascade = { .handler = no_action, .flags = SA_INTERRUPT, .name = "local0 cascade", }; -static struct irqaction local1_cascade = { +static struct irqaction local1_cascade = { .handler = no_action, .flags = SA_INTERRUPT, .name = "local1 cascade", }; -static struct irqaction buserr = { +static struct irqaction buserr = { .handler = no_action, .flags = SA_INTERRUPT, .name = "Bus Error", }; -static struct irqaction map0_cascade = { +static struct irqaction map0_cascade = { .handler = no_action, .flags = SA_INTERRUPT, .name = "mapable0 cascade", }; #ifdef USE_LIO3_IRQ -static struct irqaction map1_cascade = { +static struct irqaction map1_cascade = { .handler = no_action, .flags = SA_INTERRUPT, .name = "mapable1 cascade", diff --git a/arch/mips/sgi-ip22/ip22-nvram.c b/arch/mips/sgi-ip22/ip22-nvram.c index de43e86fa17c..fd29fd407ae8 100644 --- a/arch/mips/sgi-ip22/ip22-nvram.c +++ b/arch/mips/sgi-ip22/ip22-nvram.c @@ -39,7 +39,7 @@ *ptr |= EEPROM_CSEL; \ *ptr |= EEPROM_ECLK; }) - + #define eeprom_cs_off(ptr) ({ \ *ptr &= ~EEPROM_ECLK; \ *ptr &= ~EEPROM_CSEL; \ @@ -50,7 +50,7 @@ /* * clock in the nvram command and the register number. For the * national semiconductor nv ram chip the op code is 3 bits and - * the address is 6/8 bits. + * the address is 6/8 bits. */ static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd, unsigned reg) @@ -90,7 +90,7 @@ unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg) if (*ctrl & EEPROM_DATI) res |= 1; } - + eeprom_cs_off(ctrl); return res; @@ -113,7 +113,7 @@ unsigned short ip22_nvram_read(int reg) reg <<= 1; tmp = hpc3c0->bbram[reg++] & 0xff; return (tmp << 8) | (hpc3c0->bbram[reg] & 0xff); - } + } } EXPORT_SYMBOL(ip22_nvram_read); diff --git a/arch/mips/sgi-ip22/ip22-reset.c b/arch/mips/sgi-ip22/ip22-reset.c index ed5c60adce63..214ffd2e98a3 100644 --- a/arch/mips/sgi-ip22/ip22-reset.c +++ b/arch/mips/sgi-ip22/ip22-reset.c @@ -185,7 +185,7 @@ static irqreturn_t panel_int(int irq, void *dev_id, struct pt_regs *regs) add_timer(&debounce_timer); } - /* Power button was pressed + /* Power button was pressed * ioc.ps page 22: "The Panel Register is called Power Control by Full * House. Only lowest 2 bits are used. Guiness uses upper four bits * for volume control". This is not true, all bits are pulled high diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c index 173f76805ea3..df9b5694328a 100644 --- a/arch/mips/sgi-ip22/ip22-time.c +++ b/arch/mips/sgi-ip22/ip22-time.c @@ -126,7 +126,7 @@ static __init void indy_time_init(void) unsigned long r4k_ticks[3]; unsigned long r4k_tick; - /* + /* * Figure out the r4k offset, the algorithm is very simple and works in * _all_ cases as long as the 8254 counter register itself works ok (as * an interrupt driving timer it does not because of bug, this is why diff --git a/arch/mips/sgi-ip27/ip27-memory.c b/arch/mips/sgi-ip27/ip27-memory.c index a160d04f7dbe..ef20d9ac0ba3 100644 --- a/arch/mips/sgi-ip27/ip27-memory.c +++ b/arch/mips/sgi-ip27/ip27-memory.c @@ -538,7 +538,7 @@ void __init mem_init(void) for_each_online_node(node) { unsigned slot, numslots; struct page *end, *p; - + /* * This will free up the bootmem, ie, slot 0 memory. */ diff --git a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c index 281f090e48a4..88e1f52059ff 100644 --- a/arch/mips/sgi-ip32/ip32-reset.c +++ b/arch/mips/sgi-ip32/ip32-reset.c @@ -140,7 +140,7 @@ static irqreturn_t ip32_rtc_int(int irq, void *dev_id, struct pt_regs *regs) reg_c = CMOS_READ(RTC_INTR_FLAGS); if (!(reg_c & RTC_IRQF)) { - printk(KERN_WARNING + printk(KERN_WARNING "%s: RTC IRQ without RTC_IRQF\n", __FUNCTION__); } /* Wait until interrupt goes away */ diff --git a/arch/mips/sibyte/cfe/cfe_error.h b/arch/mips/sibyte/cfe/cfe_error.h index 77eb4935bfb4..975f00002cbe 100644 --- a/arch/mips/sibyte/cfe/cfe_error.h +++ b/arch/mips/sibyte/cfe/cfe_error.h @@ -17,15 +17,15 @@ */ /* ********************************************************************* - * + * * Broadcom Common Firmware Environment (CFE) - * + * * Error codes File: cfe_error.h - * + * * CFE's global error code list is here. - * + * * Author: Mitch Lichtenberg - * + * ********************************************************************* */ diff --git a/arch/mips/sibyte/cfe/console.c b/arch/mips/sibyte/cfe/console.c index 53a5c1eb5611..7721100d0275 100644 --- a/arch/mips/sibyte/cfe/console.c +++ b/arch/mips/sibyte/cfe/console.c @@ -38,7 +38,7 @@ static void cfe_console_write(struct console *cons, const char *str, last += written; } while (last < count); } - + } static int cfe_console_setup(struct console *cons, char *str) diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c index d86943f9d812..7a2c7a8510d4 100644 --- a/arch/mips/sibyte/cfe/setup.c +++ b/arch/mips/sibyte/cfe/setup.c @@ -285,7 +285,7 @@ void __init prom_init(void) while (1) ; } cfe_init(cfe_handle, cfe_ept); - /* + /* * Get the handle for (at least) prom_putchar, possibly for * boot console */ diff --git a/arch/mips/sibyte/cfe/smp.c b/arch/mips/sibyte/cfe/smp.c index 73392190d2b1..e44ce1a9eea9 100644 --- a/arch/mips/sibyte/cfe/smp.c +++ b/arch/mips/sibyte/cfe/smp.c @@ -57,7 +57,7 @@ void __init prom_prepare_cpus(unsigned int max_cpus) void prom_boot_secondary(int cpu, struct task_struct *idle) { int retval; - + retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, __KSTK_TOS(idle), (unsigned long)idle->thread_info, 0); diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c index 182a16f42e2d..1a97e3127aeb 100644 --- a/arch/mips/sibyte/sb1250/bus_watcher.c +++ b/arch/mips/sibyte/sb1250/bus_watcher.c @@ -10,13 +10,13 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* +/* * The Bus Watcher monitors internal bus transactions and maintains * counts of transactions with error status, logging details and * causing one of several interrupts. This driver provides a handler @@ -155,7 +155,7 @@ static int bw_read_proc(char *page, char **start, off_t off, static void create_proc_decoder(struct bw_stats_struct *stats) { struct proc_dir_entry *ent; - + ent = create_proc_read_entry("bus_watcher", S_IWUSR | S_IRUGO, NULL, bw_read_proc, stats); if (!ent) { diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 2728abbc94d2..2725b263cced 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -377,7 +377,7 @@ void __init arch_init_irq(void) /* * Note that the timer interrupts are also mapped, but this is - * done in sb1250_time_init(). Also, the profiling driver + * done in sb1250_time_init(). Also, the profiling driver * does its own management of IP7. */ @@ -392,7 +392,7 @@ void __init arch_init_irq(void) if (kgdb_flag) { kgdb_irq = K_INT_UART_0 + kgdb_port; -#ifdef CONFIG_SIBYTE_SB1250_DUART +#ifdef CONFIG_SIBYTE_SB1250_DUART sb1250_duart_present[kgdb_port] = 0; #endif /* Setup uart 1 settings, mapper */ diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c index 0e633ee8d83c..a686bb716ec6 100644 --- a/arch/mips/sibyte/swarm/rtc_m41t81.c +++ b/arch/mips/sibyte/swarm/rtc_m41t81.c @@ -128,7 +128,7 @@ static int m41t81_write(uint8_t addr, int b) /* Clear error bit by writing a 1 */ bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; - } + } /* read the same byte again to make sure it is written */ bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, @@ -136,7 +136,7 @@ static int m41t81_write(uint8_t addr, int b) while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - + return 0; } @@ -148,13 +148,13 @@ int m41t81_set_time(unsigned long t) /* * Note the write order matters as it ensures the correctness. - * When we write sec, 10th sec is clear. It is reasonable to + * When we write sec, 10th sec is clear. It is reasonable to * believe we should finish writing min within a second. */ tm.tm_sec = BIN2BCD(tm.tm_sec); m41t81_write(M41T81REG_SC, tm.tm_sec); - + tm.tm_min = BIN2BCD(tm.tm_min); m41t81_write(M41T81REG_MN, tm.tm_min); @@ -187,7 +187,7 @@ unsigned long m41t81_get_time(void) { unsigned int year, mon, day, hour, min, sec; - /* + /* * min is valid if two reads of sec are the same. */ for (;;) { diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 4742e4fc89f7..4daeaa413def 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -98,7 +98,7 @@ static int __init swarm_setup(void) rtc_get_time = xicor_get_time; rtc_set_time = xicor_set_time; } - + if (m41t81_probe()) { printk("swarm setup: M41T81 RTC detected.\n"); rtc_get_time = m41t81_get_time; diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c index 62c760f14674..141a310d74d8 100644 --- a/arch/mips/sni/irq.c +++ b/arch/mips/sni/irq.c @@ -103,7 +103,7 @@ static unsigned int ls1bit8(unsigned int x) /* * hwint 1 deals with EISA and SCSI interrupts, - * + * * The EISA_INT bit in CSITPEND is high active, all others are low active. */ void pciasic_hwint1(struct pt_regs *regs) diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c index 8f67cee4317b..1b3f8a0903e1 100644 --- a/arch/mips/sni/setup.c +++ b/arch/mips/sni/setup.c @@ -111,7 +111,7 @@ static struct resource sni_mem_resource = { * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used * for other purposes. Be paranoid and allocate all of the before the PCI * code gets a chance to to map anything else there ... - * + * * This leaves the following areas available: * * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory diff --git a/arch/mips/tx4927/common/tx4927_irq_handler.S b/arch/mips/tx4927/common/tx4927_irq_handler.S index ca123e28d1ef..dd3ceda9d712 100644 --- a/arch/mips/tx4927/common/tx4927_irq_handler.S +++ b/arch/mips/tx4927/common/tx4927_irq_handler.S @@ -42,13 +42,13 @@ CLI .set at - mfc0 t0, CP0_CAUSE + mfc0 t0, CP0_CAUSE mfc0 t1, CP0_STATUS and t0, t1 - + andi t1, t0, STATUSF_IP7 /* cpu timer */ bnez t1, ll_ip7 - + /* IP6..IP3 multiplexed -- do not use */ andi t1, t0, STATUSF_IP2 /* tx4927 pic */ diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c index 16bcbdc6d1cc..26d7c53612a8 100644 --- a/arch/mips/tx4927/common/tx4927_setup.c +++ b/arch/mips/tx4927/common/tx4927_setup.c @@ -152,7 +152,7 @@ dump_cp0(char *key) print_cp0(key, 16, "CONFIG ", read_c0_config()); return; } - + void print_pic(char *key, u32 reg, char *name) { printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name, diff --git a/arch/mips/tx4927/toshiba_rbtx4927/Makefile b/arch/mips/tx4927/toshiba_rbtx4927/Makefile index 86ca4cf2d587..c1a377a80a5d 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/Makefile +++ b/arch/mips/tx4927/toshiba_rbtx4927/Makefile @@ -1,5 +1,5 @@ -obj-y += toshiba_rbtx4927_prom.o -obj-y += toshiba_rbtx4927_setup.o -obj-y += toshiba_rbtx4927_irq.o +obj-y += toshiba_rbtx4927_prom.o +obj-y += toshiba_rbtx4927_setup.o +obj-y += toshiba_rbtx4927_irq.o EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index fd5b433f83b7..aee07ff2212a 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -31,7 +31,7 @@ /* -IRQ Device +IRQ Device 00 RBTX4927-ISA/00 01 RBTX4927-ISA/01 PS2/Keyboard 02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15) @@ -52,15 +52,15 @@ IRQ Device 16 TX4927-CP0/00 Software 0 17 TX4927-CP0/01 Software 1 18 TX4927-CP0/02 Cascade TX4927-CP0 -19 TX4927-CP0/03 Multiplexed -- do not use -20 TX4927-CP0/04 Multiplexed -- do not use -21 TX4927-CP0/05 Multiplexed -- do not use -22 TX4927-CP0/06 Multiplexed -- do not use +19 TX4927-CP0/03 Multiplexed -- do not use +20 TX4927-CP0/04 Multiplexed -- do not use +21 TX4927-CP0/05 Multiplexed -- do not use +22 TX4927-CP0/06 Multiplexed -- do not use 23 TX4927-CP0/07 CPU TIMER 24 TX4927-PIC/00 25 TX4927-PIC/01 -26 TX4927-PIC/02 +26 TX4927-PIC/02 27 TX4927-PIC/03 Cascade RBTX4927-IOC 28 TX4927-PIC/04 29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet @@ -80,7 +80,7 @@ IRQ Device 43 TX4927-PIC/19 44 TX4927-PIC/20 45 TX4927-PIC/21 -46 TX4927-PIC/22 TX4927 PCI PCI-ERR +46 TX4927-PIC/22 TX4927 PCI PCI-ERR 47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used) 48 TX4927-PIC/24 49 TX4927-PIC/25 @@ -100,7 +100,7 @@ IRQ Device 62 RBTX4927-IOC/06 63 RBTX4927-IOC/07 -NOTES: +NOTES: SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 SouthBridge/ISA/pin=0 no pci irq used by this device SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14 @@ -175,19 +175,19 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB static const u32 toshiba_rbtx4927_irq_debug_flag = (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO | TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR -// | TOSHIBA_RBTX4927_IRQ_IOC_INIT -// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP -// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN -// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE -// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE -// | TOSHIBA_RBTX4927_IRQ_IOC_MASK -// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ -// | TOSHIBA_RBTX4927_IRQ_ISA_INIT -// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP -// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN -// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE -// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE -// | TOSHIBA_RBTX4927_IRQ_ISA_MASK +// | TOSHIBA_RBTX4927_IRQ_IOC_INIT +// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP +// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN +// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE +// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE +// | TOSHIBA_RBTX4927_IRQ_IOC_MASK +// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ +// | TOSHIBA_RBTX4927_IRQ_ISA_INIT +// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP +// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN +// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE +// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE +// | TOSHIBA_RBTX4927_IRQ_ISA_MASK // | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ ); #endif diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c index 8724ea3ae04e..fc0720599fd9 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c @@ -395,7 +395,7 @@ static int __init tx4927_pcibios_init(void) /* enable secondary ide */ v08_43 |= 0x80; - /* + /* * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! * * This line of code is intended to provide the user with a work diff --git a/arch/mips/vr41xx/common/vrc4173.c b/arch/mips/vr41xx/common/vrc4173.c index 5475dd72e264..ba58764ef8ea 100644 --- a/arch/mips/vr41xx/common/vrc4173.c +++ b/arch/mips/vr41xx/common/vrc4173.c @@ -476,7 +476,7 @@ static inline int vrc4173_icu_init(int cascade_irq) if (cascade_irq < GIU_IRQ(0) || cascade_irq > GIU_IRQ(15)) return -EINVAL; - + vrc4173_outw(0, VRC4173_MSYSINT1REG); vr41xx_set_irq_trigger(GIU_IRQ_TO_PIN(cascade_irq), TRIGGER_LEVEL, SIGNAL_THROUGH); diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h index 40ceedcf454e..30b18ea6cb11 100644 --- a/include/asm-mips/asmmacro.h +++ b/include/asm-mips/asmmacro.h @@ -7,10 +7,10 @@ */ #ifndef _ASM_ASMMACRO_H #define _ASM_ASMMACRO_H - + #include #include - + #ifdef CONFIG_32BIT #include #endif diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index bc136dcfdbe6..eb8d79dba11c 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -20,13 +20,13 @@ #define SZLONG_MASK 31UL #define __LL "ll " #define __SC "sc " -#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) +#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) #elif (_MIPS_SZLONG == 64) #define SZLONG_LOG 6 #define SZLONG_MASK 63UL #define __LL "lld " #define __SC "scd " -#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) +#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) #endif #ifdef __KERNEL__ diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h index ae3e2a38fd5f..a438548e6ef3 100644 --- a/include/asm-mips/ddb5xxx/ddb5477.h +++ b/include/asm-mips/ddb5xxx/ddb5477.h @@ -247,7 +247,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); * All PCI irq but INTC are active low. */ -/* +/* * irq number block assignment */ @@ -285,7 +285,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); #define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */ #define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */ #define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */ -#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE) +#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE) #define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */ #define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */ #define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */ @@ -301,7 +301,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); /* * i2859 irq assignment */ -#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE) +#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE) #define I8259_IRQ_KEYBOARD (1 + I8259_IRQ_BASE) /* M1543 default */ #define I8259_IRQ_CASCADE (2 + I8259_IRQ_BASE) #define I8259_IRQ_UART_B (3 + I8259_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */ diff --git a/include/asm-mips/fpregdef.h b/include/asm-mips/fpregdef.h index 1d9aa0979181..2b5fddc8f487 100644 --- a/include/asm-mips/fpregdef.h +++ b/include/asm-mips/fpregdef.h @@ -13,7 +13,7 @@ #define _ASM_FPREGDEF_H #include - + #if _MIPS_SIM == _MIPS_SIM_ABI32 /* @@ -56,7 +56,7 @@ #define fcr31 $31 /* FPU status register */ #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - + #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 #define fv0 $f0 /* return value */ diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index 6cb38d5c0407..ea24e733b1bc 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -82,7 +82,7 @@ do { \ static inline int is_fpu_owner(void) { - return cpu_has_fpu && test_thread_flag(TIF_USEDFPU); + return cpu_has_fpu && test_thread_flag(TIF_USEDFPU); } static inline void own_fpu(void) @@ -90,7 +90,7 @@ static inline void own_fpu(void) if (cpu_has_fpu) { __enable_fpu(); KSTK_STATUS(current) |= ST0_CU1; - set_thread_flag(TIF_USEDFPU); + set_thread_flag(TIF_USEDFPU); } } @@ -98,7 +98,7 @@ static inline void lose_fpu(void) { if (cpu_has_fpu) { KSTK_STATUS(current) &= ~ST0_CU1; - clear_thread_flag(TIF_USEDFPU); + clear_thread_flag(TIF_USEDFPU); __disable_fpu(); } } @@ -127,7 +127,7 @@ static inline void restore_fp(struct task_struct *tsk) static inline fpureg_t *get_fpu_regs(struct task_struct *tsk) { if (cpu_has_fpu) { - if ((tsk == current) && is_fpu_owner()) + if ((tsk == current) && is_fpu_owner()) _save_fp(current); return tsk->thread.fpu.hard.fpr; } diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h index 2b7b0fdeac19..432011b16c26 100644 --- a/include/asm-mips/ip32/mace.h +++ b/include/asm-mips/ip32/mace.h @@ -94,7 +94,7 @@ struct mace_video { unsigned long xxx; /* later... */ }; -/* +/* * Ethernet interface */ struct mace_ethernet { @@ -129,7 +129,7 @@ struct mace_ethernet { volatile unsigned long rx_fifo; }; -/* +/* * Peripherals */ @@ -251,7 +251,7 @@ struct mace_timers { timer_reg audio_out2; timer_reg video_in1; timer_reg video_in2; - timer_reg video_out; + timer_reg video_out; }; struct mace_perif { @@ -272,7 +272,7 @@ struct mace_perif { }; -/* +/* * ISA peripherals */ diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h index 21d0fb7cee64..9e88c7669c7a 100644 --- a/include/asm-mips/lasat/serial.h +++ b/include/asm-mips/lasat/serial.h @@ -1,13 +1,13 @@ #include /* Lasat 100 boards serial configuration */ -#define LASAT_BASE_BAUD_100 ( 7372800 / 16 ) +#define LASAT_BASE_BAUD_100 ( 7372800 / 16 ) #define LASAT_UART_REGS_BASE_100 0x1c8b0000 #define LASAT_UART_REGS_SHIFT_100 2 #define LASATINT_UART_100 8 /* * LASAT 200 boards serial configuration */ -#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) +#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) #define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300) #define LASAT_UART_REGS_SHIFT_200 3 #define LASATINT_UART_200 13 diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 2b36ea346910..148bae2fa7d3 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -1383,7 +1383,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define PCI_IO_START 0 #define PCI_IO_END 0 #define PCI_MEM_START 0 -#define PCI_MEM_END 0 +#define PCI_MEM_END 0 #define PCI_FIRST_DEVFN 0 #define PCI_LAST_DEVFN 0 #endif diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h index 4691398a414f..efafe65258b6 100644 --- a/include/asm-mips/mach-db1x00/db1x00.h +++ b/include/asm-mips/mach-db1x00/db1x00.h @@ -23,7 +23,7 @@ * * ######################################################################## * - * + * */ #ifndef __ASM_DB1X00_H #define __ASM_DB1X00_H diff --git a/include/asm-mips/mach-jazz/floppy.h b/include/asm-mips/mach-jazz/floppy.h index 8cf0d042c864..c9dad99b1232 100644 --- a/include/asm-mips/mach-jazz/floppy.h +++ b/include/asm-mips/mach-jazz/floppy.h @@ -92,7 +92,7 @@ static inline int fd_request_irq(void) return request_irq(FLOPPY_IRQ, floppy_interrupt, SA_INTERRUPT | SA_SAMPLE_RANDOM, "floppy", NULL); } - + static inline void fd_free_irq(void) { free_irq(FLOPPY_IRQ, NULL); diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h index d6c779747b3c..ff6d40c87a25 100644 --- a/include/asm-mips/mach-pb1x00/pb1500.h +++ b/include/asm-mips/mach-pb1x00/pb1500.h @@ -33,11 +33,11 @@ #define PCI_BOARD_REG 0xAE000010 #define PCMCIA_BOARD_REG 0xAE000010 #define PC_DEASSERT_RST 0x80 - #define PC_DRV_EN 0x10 + #define PC_DRV_EN 0x10 #define PB1500_G_CONTROL 0xAE000014 #define PB1500_RST_VDDI 0xAE00001C #define PB1500_LEDS 0xAE000018 - + #define PB1500_HEX_LED 0xAF000004 #define PB1500_HEX_LED_BLANK 0xAF000008 diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index da03a32c1ca7..5bea49feec66 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -171,11 +171,11 @@ static inline void blast_dcache16(void) unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.dcache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; - unsigned long ws_end = current_cpu_data.dcache.ways << + unsigned long ws_end = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) + for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_D); } @@ -200,8 +200,8 @@ static inline void blast_dcache16_page_indexed(unsigned long page) current_cpu_data.dcache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_D); } @@ -214,8 +214,8 @@ static inline void blast_icache16(void) current_cpu_data.icache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Invalidate_I); } @@ -239,8 +239,8 @@ static inline void blast_icache16_page_indexed(unsigned long page) current_cpu_data.icache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Invalidate_I); } @@ -249,11 +249,11 @@ static inline void blast_scache16(void) unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << + unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) + for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -278,8 +278,8 @@ static inline void blast_scache16_page_indexed(unsigned long page) current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -318,8 +318,8 @@ static inline void blast_dcache32(void) current_cpu_data.dcache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_D); } @@ -343,8 +343,8 @@ static inline void blast_dcache32_page_indexed(unsigned long page) current_cpu_data.dcache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_D); } @@ -357,8 +357,8 @@ static inline void blast_icache32(void) current_cpu_data.icache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Invalidate_I); } @@ -383,7 +383,7 @@ static inline void blast_icache32_page_indexed(unsigned long page) unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) + for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Invalidate_I); } @@ -392,11 +392,11 @@ static inline void blast_scache32(void) unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << + unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) + for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -421,8 +421,8 @@ static inline void blast_scache32_page_indexed(unsigned long page) current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -461,8 +461,8 @@ static inline void blast_icache64(void) current_cpu_data.icache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Invalidate_I); } @@ -487,7 +487,7 @@ static inline void blast_icache64_page_indexed(unsigned long page) unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) + for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Invalidate_I); } @@ -496,11 +496,11 @@ static inline void blast_scache64(void) unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << + unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) + for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -525,8 +525,8 @@ static inline void blast_scache64_page_indexed(unsigned long page) current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -561,11 +561,11 @@ static inline void blast_scache128(void) unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << + unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) + for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x1000) cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -590,8 +590,8 @@ static inline void blast_scache128_page_indexed(unsigned long page) current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x1000) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x1000) cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); } diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h index 31c0c2347f4f..3c4b637fd925 100644 --- a/include/asm-mips/rtc.h +++ b/include/asm-mips/rtc.h @@ -1,5 +1,5 @@ /* - * include/asm-mips/rtc.h + * include/asm-mips/rtc.h * * (Really an interface for drivers/char/genrtc.c) * diff --git a/include/asm-mips/sgi/gio.h b/include/asm-mips/sgi/gio.h index a38d66f99872..889cf028c95d 100644 --- a/include/asm-mips/sgi/gio.h +++ b/include/asm-mips/sgi/gio.h @@ -16,7 +16,7 @@ * * The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have * three physical connectors, but only two slots, GFX and EXP0. - * + * * There is 10MB of GIO address space for GIO64 slot devices * slot# slot type address range size * ----- --------- ----------------------- ----- diff --git a/include/asm-mips/sgi/hpc3.h b/include/asm-mips/sgi/hpc3.h index a5b988d7327a..ac3dfc7af5b0 100644 --- a/include/asm-mips/sgi/hpc3.h +++ b/include/asm-mips/sgi/hpc3.h @@ -221,7 +221,7 @@ struct hpc3_regs { #define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */ u32 _unused1[0x14000/4 - 5]; /* padding */ - + /* Now direct PIO per-HPC3 peripheral access to external regs. */ volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */ u32 _unused2[0x7c00/4]; @@ -304,7 +304,7 @@ struct hpc3_regs { volatile u32 bbram[8192-50-14]; /* Battery backed ram */ }; -/* +/* * It is possible to have two HPC3's within the address space on * one machine, though only having one is more likely on an Indy. */ diff --git a/include/asm-mips/sgi/ioc.h b/include/asm-mips/sgi/ioc.h index 169187f53fbc..f3e3dc9bb732 100644 --- a/include/asm-mips/sgi/ioc.h +++ b/include/asm-mips/sgi/ioc.h @@ -16,7 +16,7 @@ #include #include -/* +/* * All registers are 8-bit wide alligned on 32-bit boundary. Bad things * happen if you try word access them. You have been warned. */ @@ -138,7 +138,7 @@ struct sgioc_regs { u8 _sysid[3]; volatile u8 sysid; #define SGIOC_SYSID_FULLHOUSE 0x01 -#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5) +#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5) #define SGIOC_SYSID_CHIPREV(x) ((x & 0x1e) > 1) u32 _unused2; u8 _read[3]; diff --git a/include/asm-mips/sgi/ip22.h b/include/asm-mips/sgi/ip22.h index 97d73adb4e40..bbfc05c3cab9 100644 --- a/include/asm-mips/sgi/ip22.h +++ b/include/asm-mips/sgi/ip22.h @@ -12,7 +12,7 @@ #ifndef _SGI_IP22_H #define _SGI_IP22_H -/* +/* * These are the virtual IRQ numbers, we divide all IRQ's into * 'spaces', the 'space' determines where and how to enable/disable * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups diff --git a/include/asm-mips/sgi/mc.h b/include/asm-mips/sgi/mc.h index fd98f930607c..c52f7834c7c8 100644 --- a/include/asm-mips/sgi/mc.h +++ b/include/asm-mips/sgi/mc.h @@ -182,14 +182,14 @@ struct sgimc_regs { volatile u32 dtlb_hi3; u32 _unused33; volatile u32 dtlb_lo3; - + u32 _unused34[0x0392]; - + u32 _unused35; volatile u32 rpsscounter; /* Chirps at 100ns */ u32 _unused36[0x1000/4-2*4]; - + u32 _unused37; volatile u32 maddronly; /* Address DMA goes at */ u32 _unused38; diff --git a/include/asm-mips/sibyte/carmel.h b/include/asm-mips/sibyte/carmel.h index 7ac5da13ce8a..b5e7dae19f0f 100644 --- a/include/asm-mips/sibyte/carmel.h +++ b/include/asm-mips/sibyte/carmel.h @@ -25,12 +25,12 @@ #define SIBYTE_BOARD_NAME "Carmel" -#define GPIO_PHY_INTERRUPT 2 -#define GPIO_NONMASKABLE_INT 3 -#define GPIO_CF_INSERTED 6 -#define GPIO_MONTEREY_RESET 7 -#define GPIO_QUADUART_INT 8 -#define GPIO_CF_INT 9 +#define GPIO_PHY_INTERRUPT 2 +#define GPIO_NONMASKABLE_INT 3 +#define GPIO_CF_INSERTED 6 +#define GPIO_MONTEREY_RESET 7 +#define GPIO_QUADUART_INT 8 +#define GPIO_CF_INT 9 #define GPIO_FPGA_CCLK 10 #define GPIO_FPGA_DOUT 11 #define GPIO_FPGA_DIN 12 diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h index 96088fb074a4..40ef97c76c8b 100644 --- a/include/asm-mips/sibyte/sb1250_defs.h +++ b/include/asm-mips/sibyte/sb1250_defs.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * - * Global constants and macros File: sb1250_defs.h - * + * + * Global constants and macros File: sb1250_defs.h + * * This file contains macros and definitions used by the other * include files. * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -105,7 +105,7 @@ #define SIBYTE_HDR_FMASK_112x_ALL 0x0000f00 #define SIBYTE_HDR_FMASK_112x_PASS1 0x0000100 -/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ +/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ #define SIBYTE_HDR_FMASK(chip, pass) \ (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass) #define SIBYTE_HDR_FMASK_ALLREVS(chip) \ @@ -150,31 +150,31 @@ /* ********************************************************************* * Naming schemes for constants in these files: - * - * M_xxx MASK constant (identifies bits in a register). + * + * M_xxx MASK constant (identifies bits in a register). * For multi-bit fields, all bits in the field will * be set. * * K_xxx "Code" constant (value for data in a multi-bit * field). The value is right justified. * - * V_xxx "Value" constant. This is the same as the + * V_xxx "Value" constant. This is the same as the * corresponding "K_xxx" constant, except it is * shifted to the correct position in the register. * * S_xxx SHIFT constant. This is the number of bits that - * a field value (code) needs to be shifted + * a field value (code) needs to be shifted * (towards the left) to put the value in the right * position for the register. * - * A_xxx ADDRESS constant. This will be a physical + * A_xxx ADDRESS constant. This will be a physical * address. Use the PHYS_TO_K1 macro to generate * a K1SEG address. * * R_xxx RELATIVE offset constant. This is an offset from * an A_xxx constant (usually the first register in * a group). - * + * * G_xxx(X) GET value. This macro obtains a multi-bit field * from a register, masks it, and shifts it to * the bottom of the register (retrieving a K_xxx @@ -189,7 +189,7 @@ /* - * Cast to 64-bit number. Presumably the syntax is different in + * Cast to 64-bit number. Presumably the syntax is different in * assembly language. * * Note: you'll need to define uint32_t and uint64_t in your headers. diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h index f1b08d32338d..3cdb48f50ed0 100644 --- a/include/asm-mips/sibyte/sb1250_dma.h +++ b/include/asm-mips/sibyte/sb1250_dma.h @@ -1,24 +1,24 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * DMA definitions File: sb1250_dma.h - * + * * This module contains constants and macros useful for * programming the SB1250's DMA controllers, both the data mover * and the Ethernet DMA. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -28,7 +28,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -43,9 +43,9 @@ * DMA Registers ********************************************************************* */ -/* +/* * Ethernet and Serial DMA Configuration Register 0 (Table 7-4) - * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 + * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 * Registers: DMA_CONFIG0_MAC_x_TX_CH_0 * Registers: DMA_CONFIG0_SER_x_RX * Registers: DMA_CONFIG0_SER_x_TX @@ -98,7 +98,7 @@ /* * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) - * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 + * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 * Registers: DMA_CONFIG1_DMA_x_TX_CH_0 * Registers: DMA_CONFIG1_SER_x_RX * Registers: DMA_CONFIG1_SER_x_TX @@ -152,11 +152,11 @@ /* * DMA Descriptor Count Registers (Table 7-8) */ - + /* No bitfields */ -/* +/* * Current Descriptor Address Register (Table 7-11) */ @@ -275,14 +275,14 @@ #define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS) #define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS) -/* +/* * Ethernet Descriptor Status Bits (Table 7-15) */ #define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) #define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) /* Note: BADTCPCS is actually in DSCR_B options field */ #define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) #endif /* 1250 PASS2 || 112x PASS1 */ @@ -324,7 +324,7 @@ #define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63) -/* +/* * Ethernet Transmit Options (Table 7-17) */ @@ -377,7 +377,7 @@ * Data Mover Registers ********************************************************************* */ -/* +/* * Data Mover Descriptor Base Address Register (Table 7-22) * Register: DM_DSCR_BASE_0 * Register: DM_DSCR_BASE_1 @@ -414,7 +414,7 @@ #define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62) #define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63) -/* +/* * Data Mover Descriptor Count Register (Table 7-25) */ diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h index 0d9dfac3d7db..f1f509f295c4 100644 --- a/include/asm-mips/sibyte/sb1250_genbus.h +++ b/include/asm-mips/sibyte/sb1250_genbus.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * Generic Bus Constants File: sb1250_genbus.h - * - * This module contains constants and macros useful for + * + * This module contains constants and macros useful for * manipulating the SB1250's Generic Bus interface - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h index c3f74df211f4..e173e2ea4c98 100644 --- a/include/asm-mips/sibyte/sb1250_int.h +++ b/include/asm-mips/sibyte/sb1250_int.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * Interrupt Mapper definitions File: sb1250_int.h - * + * * This module contains constants for manipulating the SB1250's * interrupt mapper and definitions for the interrupt sources. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -43,7 +43,7 @@ /* * Interrupt sources (Table 4-8, UM 0.2) - * + * * First, the interrupt numbers. */ diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h index 799db828d963..8afe8e01581b 100644 --- a/include/asm-mips/sibyte/sb1250_l2c.h +++ b/include/asm-mips/sibyte/sb1250_l2c.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * L2 Cache constants and macros File: sb1250_l2c.h - * + * * This module contains constants useful for manipulating the * level 2 cache. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h index d8753885df17..f2617ded0a8f 100644 --- a/include/asm-mips/sibyte/sb1250_ldt.h +++ b/include/asm-mips/sibyte/sb1250_ldt.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * LDT constants File: sb1250_ldt.h - * - * This module contains constants and macros to describe - * the LDT interface on the SB1250. - * + * + * This module contains constants and macros to describe + * the LDT interface on the SB1250. + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -155,7 +155,7 @@ /* * LDT Status Register (Table 8-14). Note that these constants - * assume you've read the command and status register + * assume you've read the command and status register * together (32-bit read at offset 0x04) * * These bits also apply to the secondary status @@ -183,8 +183,8 @@ #define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31) /* - * Bridge Control Register (Table 8-16). Note that these - * constants assume you've read the register as a 32-bit + * Bridge Control Register (Table 8-16). Note that these + * constants assume you've read the register as a 32-bit * read (offset 0x3C) */ diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h index 81f603f03a98..18e74e43f4a2 100644 --- a/include/asm-mips/sibyte/sb1250_mac.h +++ b/include/asm-mips/sibyte/sb1250_mac.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * MAC constants and macros File: sb1250_mac.h - * + * * This module contains constants and macros for the SB1250's * ethernet controllers. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -311,7 +311,7 @@ /* * These constants are used to configure the fields within the Frame - * Configuration Register. + * Configuration Register. */ #define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ @@ -393,7 +393,7 @@ * Register: MAC_INT_MASK_2 */ -/* +/* * Use these constants to shift the appropriate channel * into the CH0 position so the same tests can be used * on each channel. diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h index 93a48334b874..1dd41c927996 100644 --- a/include/asm-mips/sibyte/sb1250_mc.h +++ b/include/asm-mips/sibyte/sb1250_mc.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * - * Memory Controller constants File: sb1250_mc.h - * + * + * Memory Controller constants File: sb1250_mc.h + * * This module contains constants and macros useful for * programming the memory controller. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -166,7 +166,7 @@ #define K_MC_REF_RATE_100MHz 0x62 #define K_MC_REF_RATE_133MHz 0x81 -#define K_MC_REF_RATE_200MHz 0xC4 +#define K_MC_REF_RATE_200MHz 0xC4 #define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz) #define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz) @@ -228,7 +228,7 @@ V_MC_ADDR_DRIVE_DEFAULT | \ V_MC_DATA_DRIVE_DEFAULT | \ V_MC_CLOCK_DRIVE_DEFAULT | \ - V_MC_REF_RATE_DEFAULT + V_MC_REF_RATE_DEFAULT diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h index 5d496c6faba6..9db80cd13a79 100644 --- a/include/asm-mips/sibyte/sb1250_regs.h +++ b/include/asm-mips/sibyte/sb1250_regs.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * Register Definitions File: sb1250_regs.h - * + * * This module contains the addresses of the on-chip peripherals * on the SB1250. - * + * * SB1250 specification level: 01/02/2002 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -40,20 +40,20 @@ /* ********************************************************************* * Some general notes: - * + * * For the most part, when there is more than one peripheral * of the same type on the SOC, the constants below will be * offsets from the base of each peripheral. For example, * the MAC registers are described as offsets from the first * MAC register, and there will be a MAC_REGISTER() macro - * to calculate the base address of a given MAC. - * + * to calculate the base address of a given MAC. + * * The information in this file is based on the SB1250 SOC * manual version 0.2, July 2000. ********************************************************************* */ -/* ********************************************************************* +/* ********************************************************************* * Memory Controller Registers ********************************************************************* */ @@ -101,7 +101,7 @@ #define R_MC_TEST_ECC 0x0000000420 #define R_MC_MCLK_CFG 0x0000000500 -/* ********************************************************************* +/* ********************************************************************* * L2 Cache Control Registers ********************************************************************* */ @@ -126,7 +126,7 @@ #define A_L2_EEC_ADDRESS A_L2_ECC_TAG -/* ********************************************************************* +/* ********************************************************************* * PCI Interface Registers ********************************************************************* */ @@ -134,7 +134,7 @@ #define A_PCI_TYPE01_HEADER 0x00DE000800 -/* ********************************************************************* +/* ********************************************************************* * Ethernet DMA and MACs ********************************************************************* */ @@ -184,7 +184,7 @@ (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ (reg)) -/* +/* * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE */ @@ -259,7 +259,7 @@ #define MAC_CHMAP_COUNT 4 -/* ********************************************************************* +/* ********************************************************************* * DUART Registers ********************************************************************* */ @@ -363,7 +363,7 @@ #endif /* 1250 PASS2 || 112x PASS1 */ -/* ********************************************************************* +/* ********************************************************************* * Synchronous Serial Registers ********************************************************************* */ @@ -397,7 +397,7 @@ (reg)) -/* +/* * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE */ @@ -457,7 +457,7 @@ #define R_SER_RMON_RX_ERRORS 0x000001F0 #define R_SER_RMON_RX_BADADDR 0x000001F8 -/* ********************************************************************* +/* ********************************************************************* * Generic Bus Registers ********************************************************************* */ @@ -513,7 +513,7 @@ #define R_IO_PCMCIA_CFG 0x0A60 #define R_IO_PCMCIA_STATUS 0x0A70 -/* ********************************************************************* +/* ********************************************************************* * GPIO Registers ********************************************************************* */ @@ -537,7 +537,7 @@ #define R_GPIO_PIN_CLR 0x30 #define R_GPIO_PIN_SET 0x38 -/* ********************************************************************* +/* ********************************************************************* * SMBus Registers ********************************************************************* */ @@ -573,7 +573,7 @@ #define R_SMB_CONTROL 0x0000000060 #define R_SMB_PEC 0x0000000070 -/* ********************************************************************* +/* ********************************************************************* * Timer Registers ********************************************************************* */ @@ -641,7 +641,7 @@ #endif /* 1250 PASS2 || 112x PASS1 */ -/* ********************************************************************* +/* ********************************************************************* * System Control Registers ********************************************************************* */ @@ -649,7 +649,7 @@ #define A_SCD_SYSTEM_CFG 0x0010020008 #define A_SCD_SYSTEM_MANUF 0x0010038000 -/* ********************************************************************* +/* ********************************************************************* * System Address Trap Registers ********************************************************************* */ @@ -672,7 +672,7 @@ #endif /* 1250 PASS2 || 112x PASS1 */ -/* ********************************************************************* +/* ********************************************************************* * System Interrupt Mapper Registers ********************************************************************* */ @@ -701,7 +701,7 @@ #define R_IMR_INTERRUPT_MAP_BASE 0x0200 #define R_IMR_INTERRUPT_MAP_COUNT 64 -/* ********************************************************************* +/* ********************************************************************* * System Performance Counter Registers ********************************************************************* */ @@ -711,7 +711,7 @@ #define A_SCD_PERF_CNT_2 0x00100204E0 #define A_SCD_PERF_CNT_3 0x00100204E8 -/* ********************************************************************* +/* ********************************************************************* * System Bus Watcher Registers ********************************************************************* */ @@ -726,13 +726,13 @@ #define A_BUS_L2_ERRORS 0x00100208C0 #define A_BUS_MEM_IO_ERRORS 0x00100208C8 -/* ********************************************************************* +/* ********************************************************************* * System Debug Controller Registers ********************************************************************* */ #define A_SCD_JTAG_BASE 0x0010000000 -/* ********************************************************************* +/* ********************************************************************* * System Trace Buffer Registers ********************************************************************* */ @@ -755,7 +755,7 @@ #define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 #define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 -/* ********************************************************************* +/* ********************************************************************* * System Generic DMA Registers ********************************************************************* */ diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h index 22e8041959e2..dbbd682fb47e 100644 --- a/include/asm-mips/sibyte/sb1250_scd.h +++ b/include/asm-mips/sibyte/sb1250_scd.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * SCD Constants and Macros File: sb1250_scd.h - * + * * This module contains constants and macros useful for * manipulating the System Control and Debug module on the 1250. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -130,40 +130,40 @@ /* System Manufacturing Register * Register: SCD_SYSTEM_MANUF */ - + /* Wafer ID: bits 31:0 */ #define S_SYS_WAFERID1_200 _SB_MAKE64(0) #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) #define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) #define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) - + #define S_SYS_BIN _SB_MAKE64(32) #define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) #define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN) #define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) - + /* Wafer ID: bits 39:36 */ #define S_SYS_WAFERID2_200 _SB_MAKE64(36) #define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) #define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) #define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) - + /* Wafer ID: bits 39:0 */ #define S_SYS_WAFERID_300 _SB_MAKE64(0) #define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) #define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) #define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) - + #define S_SYS_XPOS _SB_MAKE64(40) #define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) #define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) #define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) - + #define S_SYS_YPOS _SB_MAKE64(46) #define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) #define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) #define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) - + /* * System Config Register (Table 4-2) * Register: SCD_SYSTEM_CFG diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h index 287cbfe9efa2..335c53e92936 100644 --- a/include/asm-mips/sibyte/sb1250_smbus.h +++ b/include/asm-mips/sibyte/sb1250_smbus.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * SMBUS Constants File: sb1250_smbus.h - * - * This module contains constants and macros useful for + * + * This module contains constants and macros useful for * manipulating the SB1250's SMbus devices. - * + * * SB1250 specification level: 01/02/2002 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h index 8d5e8edd3c4b..fa2760d38b8b 100644 --- a/include/asm-mips/sibyte/sb1250_syncser.h +++ b/include/asm-mips/sibyte/sb1250_syncser.h @@ -7,17 +7,17 @@ * manipulating the SB1250's Synchronous Serial * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg * ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h index 7655d6945cca..923ea4f44e0f 100644 --- a/include/asm-mips/sibyte/sb1250_uart.h +++ b/include/asm-mips/sibyte/sb1250_uart.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * UART Constants File: sb1250_uart.h - * - * This module contains constants and macros useful for + * + * This module contains constants and macros useful for * manipulating the SB1250's UARTs * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -37,7 +37,7 @@ #include "sb1250_defs.h" -/* ********************************************************************** +/* ********************************************************************** * DUART Registers ********************************************************************** */ @@ -145,7 +145,7 @@ #define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) #define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) -#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) +#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) /* * DUART Status Register (Table 10-6) @@ -165,7 +165,7 @@ /* * DUART Baud Rate Register (Table 10-7) - * Register: DUART_CLK_SEL_A + * Register: DUART_CLK_SEL_A * Register: DUART_CLK_SEL_B */ @@ -332,7 +332,7 @@ (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -/* +/* * Full Interrupt Control Register */ diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h index 18939e84b6f2..f7fbebaa0744 100644 --- a/include/asm-mips/sigcontext.h +++ b/include/asm-mips/sigcontext.h @@ -10,7 +10,7 @@ #define _ASM_SIGCONTEXT_H #include - + #if _MIPS_SIM == _MIPS_SIM_ABI32 /* @@ -38,7 +38,7 @@ struct sigcontext { }; #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - + #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 /* diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h index d478a86294ee..753b6620e6fa 100644 --- a/include/asm-mips/socket.h +++ b/include/asm-mips/socket.h @@ -82,7 +82,7 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ * @SOCK_STREAM - stream (connection) socket * @SOCK_RAW - raw socket * @SOCK_RDM - reliably-delivered message - * @SOCK_SEQPACKET - sequential packet socket + * @SOCK_SEQPACKET - sequential packet socket * @SOCK_PACKET - linux specific way of getting packets at the dev level. * For writing rarp and other similar things on the user level. */ diff --git a/include/asm-mips/statfs.h b/include/asm-mips/statfs.h index 5076fec65780..c3ddf973c1c0 100644 --- a/include/asm-mips/statfs.h +++ b/include/asm-mips/statfs.h @@ -57,7 +57,7 @@ struct statfs64 { }; #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - + #if _MIPS_SIM == _MIPS_SIM_ABI64 struct statfs64 { /* Same as struct statfs */ diff --git a/include/asm-mips/titan_dep.h b/include/asm-mips/titan_dep.h index fd9599e40a0a..fee1908c65d2 100644 --- a/include/asm-mips/titan_dep.h +++ b/include/asm-mips/titan_dep.h @@ -228,4 +228,4 @@ extern unsigned long ocd_base; #define RM9K_READ_8(ofs, val) *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) #define RM9K_READ_16(ofs, val) *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) -#endif +#endif diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h index 5d939db6e220..3bb7f0087d68 100644 --- a/include/asm-mips/tx4927/tx4927.h +++ b/include/asm-mips/tx4927/tx4927.h @@ -45,14 +45,14 @@ /* TX4927 SDRAM controller (64-bit registers) */ -#define TX4927_SDRAMC_BASE 0x8000 -#define TX4927_SDRAMC_SDCCR0 0x8000 +#define TX4927_SDRAMC_BASE 0x8000 +#define TX4927_SDRAMC_SDCCR0 0x8000 #define TX4927_SDRAMC_SDCCR1 0x8008 #define TX4927_SDRAMC_SDCCR2 0x8010 #define TX4927_SDRAMC_SDCCR3 0x8018 #define TX4927_SDRAMC_SDCTR 0x8040 #define TX4927_SDRAMC_SDCMD 0x8058 -#define TX4927_SDRAMC_LIMIT 0x8fff +#define TX4927_SDRAMC_LIMIT 0x8fff /* TX4927 external bus controller (64-bit registers) */ @@ -289,8 +289,8 @@ /* TX4927 serial port 0 (32-bit registers) */ -#define TX4927_SIO0_BASE 0xf300 -#define TX4927_SIO0_SILCR0 0xf300 +#define TX4927_SIO0_BASE 0xf300 +#define TX4927_SIO0_SILCR0 0xf300 #define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31 #define TX4927_SIO0_SILCR0_RWUB BM_15_15 #define TX4927_SIO0_SILCR0_TWUB BM_14_14 @@ -309,7 +309,7 @@ #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01) #define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01 #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01 -#define TX4927_SIO0_SIDICR0 0xf304 +#define TX4927_SIO0_SIDICR0 0xf304 #define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31 #define TX4927_SIO0_SIDICR0_TDE BM_15_15 #define TX4927_SIO0_SIDICR0_RDE BM_14_14 @@ -330,7 +330,7 @@ #define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02 #define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01 #define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00 -#define TX4927_SIO0_SIDISR0 0xf308 +#define TX4927_SIO0_SIDISR0 0xf308 #define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31 #define TX4927_SIO0_SIDISR0_UBRK BM_15_15 #define TX4927_SIO0_SIDISR0_UVALID BM_14_14 @@ -344,7 +344,7 @@ #define TX4927_SIO0_SIDISR0_STIS BM_06_06 #define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05 #define TX4927_SIO0_SIDISR0_RFDN BM_00_04 -#define TX4927_SIO0_SISCISR0 0xf30c +#define TX4927_SIO0_SISCISR0 0xf30c #define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31 #define TX4927_SIO0_SISCISR0_OERS BM_05_05 #define TX4927_SIO0_SISCISR0_CTSS BM_04_04 @@ -352,7 +352,7 @@ #define TX4927_SIO0_SISCISR0_TRDY BM_02_02 #define TX4927_SIO0_SISCISR0_TXALS BM_01_01 #define TX4927_SIO0_SISCISR0_UBRKD BM_00_00 -#define TX4927_SIO0_SIFCR0 0xf310 +#define TX4927_SIO0_SIFCR0 0xf310 #define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31 #define TX4927_SIO0_SIFCR0_SWRST BM_16_31 #define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14 @@ -370,7 +370,7 @@ #define TX4927_SIO0_SIFCR0_TFRST BM_02_02 #define TX4927_SIO0_SIFCR0_RFRST BM_01_01 #define TX4927_SIO0_SIFCR0_FRSTE BM_00_00 -#define TX4927_SIO0_SIFLCR0 0xf314 +#define TX4927_SIO0_SIFLCR0 0xf314 #define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31 #define TX4927_SIO0_SIFLCR0_RCS BM_12_12 #define TX4927_SIO0_SIFLCR0_TES BM_11_11 @@ -381,7 +381,7 @@ #define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06 #define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04 #define TX4927_SIO0_SIFLCR0_TBRK BM_00_00 -#define TX4927_SIO0_SIBGR0 0xf318 +#define TX4927_SIO0_SIBGR0 0xf318 #define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31 #define TX4927_SIO0_SIBGR0_BCLK BM_08_09 #define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09) @@ -389,28 +389,28 @@ #define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09 #define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09 #define TX4927_SIO0_SIBGR0_BRD BM_00_07 -#define TX4927_SIO0_SITFIF00 0xf31c +#define TX4927_SIO0_SITFIF00 0xf31c #define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31 #define TX4927_SIO0_SITFIF00_TXD BM_00_07 -#define TX4927_SIO0_SIRFIFO0 0xf320 +#define TX4927_SIO0_SIRFIFO0 0xf320 #define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31 #define TX4927_SIO0_SIRFIFO0_RXD BM_00_07 -#define TX4927_SIO0_SIRFIFO0 0xf320 -#define TX4927_SIO0_LIMIT 0xf3ff +#define TX4927_SIO0_SIRFIFO0 0xf320 +#define TX4927_SIO0_LIMIT 0xf3ff /* TX4927 serial port 1 (32-bit registers) */ -#define TX4927_SIO1_BASE 0xf400 -#define TX4927_SIO1_SILCR1 0xf400 -#define TX4927_SIO1_SIDICR1 0xf404 -#define TX4927_SIO1_SIDISR1 0xf408 -#define TX4927_SIO1_SISCISR1 0xf40c -#define TX4927_SIO1_SIFCR1 0xf410 -#define TX4927_SIO1_SIFLCR1 0xf414 -#define TX4927_SIO1_SIBGR1 0xf418 -#define TX4927_SIO1_SITFIF01 0xf41c -#define TX4927_SIO1_SIRFIFO1 0xf420 -#define TX4927_SIO1_LIMIT 0xf4ff +#define TX4927_SIO1_BASE 0xf400 +#define TX4927_SIO1_SILCR1 0xf400 +#define TX4927_SIO1_SIDICR1 0xf404 +#define TX4927_SIO1_SIDISR1 0xf408 +#define TX4927_SIO1_SISCISR1 0xf40c +#define TX4927_SIO1_SIFCR1 0xf410 +#define TX4927_SIO1_SIFLCR1 0xf414 +#define TX4927_SIO1_SIBGR1 0xf418 +#define TX4927_SIO1_SITFIF01 0xf41c +#define TX4927_SIO1_SIRFIFO1 0xf420 +#define TX4927_SIO1_LIMIT 0xf4ff /* TX4927 parallel port (32-bit registers) */ diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h index 170433492246..165f6b8b217f 100644 --- a/include/asm-mips/tx4927/tx4927_pci.h +++ b/include/asm-mips/tx4927/tx4927_pci.h @@ -5,8 +5,8 @@ * * Copyright (C) 2000-2001 Toshiba Corporation */ -#ifndef __ASM_TX4927_TX4927_PCI_H -#define __ASM_TX4927_TX4927_PCI_H +#ifndef __ASM_TX4927_TX4927_PCI_H +#define __ASM_TX4927_TX4927_PCI_H #define TX4927_CCFG_TOE 0x00004000 diff --git a/include/asm-mips/vr41xx/vrc4173.h b/include/asm-mips/vr41xx/vrc4173.h index 58e193c51b45..bb7a85c186e4 100644 --- a/include/asm-mips/vr41xx/vrc4173.h +++ b/include/asm-mips/vr41xx/vrc4173.h @@ -21,8 +21,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __NEC_VRC4173_H -#define __NEC_VRC4173_H +#ifndef __NEC_VRC4173_H +#define __NEC_VRC4173_H #include #include diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c4a704121343..04ee53b34c2e 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -113,7 +113,7 @@ */ #define BCM1250_M3_WAR 1 -/* +/* * This is a DUART workaround related to glitches around register accesses */ #define SIBYTE_1956_WAR 1 @@ -122,7 +122,7 @@ /* * Fill buffers not flushed on CACHE instructions - * + * * Hit_Invalidate_I cacheops invalidate an icache line but the refill * for that line can get stale data from the fill buffer instead of * accessing memory if the previous icache miss was also to that line. diff --git a/include/asm-mips/xxs1500.h b/include/asm-mips/xxs1500.h index 75c0ddfeca13..4d84a90b0f20 100644 --- a/include/asm-mips/xxs1500.h +++ b/include/asm-mips/xxs1500.h @@ -22,7 +22,7 @@ * * ######################################################################## * - * + * */ #ifndef __ASM_XXS1500_H #define __ASM_XXS1500_H -- cgit v1.2.3 From 4ce588cd563e6b817adb0c7d03b3ed9c74cadc27 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 3 Sep 2005 15:56:19 -0700 Subject: [PATCH] mips: fix coherency configuration Fix the MIPS coherency configuration such that we always keep the mapping state in when we need to on non-coherent platforms. Signed-off-by: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/Kconfig | 14 +++++++++++--- arch/mips/configs/atlas_defconfig | 1 + arch/mips/configs/capcella_defconfig | 1 + arch/mips/configs/cobalt_defconfig | 1 + arch/mips/configs/db1000_defconfig | 1 + arch/mips/configs/db1100_defconfig | 1 + arch/mips/configs/ddb5476_defconfig | 1 + arch/mips/configs/ddb5477_defconfig | 1 + arch/mips/configs/decstation_defconfig | 1 + arch/mips/configs/e55_defconfig | 1 + arch/mips/configs/ev64120_defconfig | 1 + arch/mips/configs/ev96100_defconfig | 1 + arch/mips/configs/ip22_defconfig | 1 + arch/mips/configs/ip32_defconfig | 1 + arch/mips/configs/it8172_defconfig | 1 + arch/mips/configs/ivr_defconfig | 1 + arch/mips/configs/jaguar-atx_defconfig | 1 + arch/mips/configs/jmr3927_defconfig | 1 + arch/mips/configs/lasat200_defconfig | 1 + arch/mips/configs/malta_defconfig | 1 + arch/mips/configs/mpc30x_defconfig | 1 + arch/mips/configs/ocelot_3_defconfig | 1 + arch/mips/configs/ocelot_c_defconfig | 1 + arch/mips/configs/ocelot_defconfig | 1 + arch/mips/configs/ocelot_g_defconfig | 1 + arch/mips/configs/pb1100_defconfig | 1 + arch/mips/configs/rm200_defconfig | 1 + arch/mips/configs/sead_defconfig | 1 + arch/mips/configs/tb0226_defconfig | 1 + arch/mips/configs/tb0229_defconfig | 1 + arch/mips/configs/workpad_defconfig | 1 + arch/mips/defconfig | 1 + include/asm-mips/pci.h | 6 +++--- 33 files changed, 45 insertions(+), 6 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d892a23fa978..60ba382ea7f3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -951,13 +951,21 @@ config ARC depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP27 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 default y -config DMA_COHERENT +config DMA_COHERENT bool -config DMA_IP27 +config DMA_IP27 bool -config DMA_NONCOHERENT +config DMA_IP32 + bool + select DMA_NEED_PCI_MAP_STATE + +config DMA_NONCOHERENT + bool + select DMA_NEED_PCI_MAP_STATE + +config DMA_NEED_PCI_MAP_STATE bool config EARLY_PRINTK diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig index 4084ca3a7581..3120a02b8670 100644 --- a/arch/mips/configs/atlas_defconfig +++ b/arch/mips/configs/atlas_defconfig @@ -88,6 +88,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_MIPS_BONITO64=y CONFIG_MIPS_MSC=y # CONFIG_CPU_LITTLE_ENDIAN is not set diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig index 9abdcbc20a9e..158e7165f4e3 100644 --- a/arch/mips/configs/capcella_defconfig +++ b/arch/mips/configs/capcella_defconfig @@ -97,6 +97,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index ddcfcfbe098a..4302c6f914f5 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig @@ -82,6 +82,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_I8259=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index 05905dfec1e6..962fc14b58c2 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -104,6 +104,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index 610ff73a6706..6a528d479d70 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig @@ -104,6 +104,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/configs/ddb5476_defconfig b/arch/mips/configs/ddb5476_defconfig index 345cc8b078fc..70addc73f699 100644 --- a/arch/mips/configs/ddb5476_defconfig +++ b/arch/mips/configs/ddb5476_defconfig @@ -82,6 +82,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_I8259=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig index 4acb9e48d24e..60292808b384 100644 --- a/arch/mips/configs/ddb5477_defconfig +++ b/arch/mips/configs/ddb5477_defconfig @@ -83,6 +83,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_I8259=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index 27b21fb4f13a..66ec1f41d122 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig @@ -88,6 +88,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_EARLY_PRINTK=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig index 3812e5f10c9b..ba2ec01defb1 100644 --- a/arch/mips/configs/e55_defconfig +++ b/arch/mips/configs/e55_defconfig @@ -96,6 +96,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/configs/ev64120_defconfig b/arch/mips/configs/ev64120_defconfig index 705cdbd682d6..17e87f70f602 100644 --- a/arch/mips/configs/ev64120_defconfig +++ b/arch/mips/configs/ev64120_defconfig @@ -89,6 +89,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_MIPS_GT64120=y # CONFIG_SYSCLK_75 is not set diff --git a/arch/mips/configs/ev96100_defconfig b/arch/mips/configs/ev96100_defconfig index 4c89dfef8e78..9da4140eae00 100644 --- a/arch/mips/configs/ev96100_defconfig +++ b/arch/mips/configs/ev96100_defconfig @@ -88,6 +88,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y CONFIG_MIPS_GT64120=y diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index 2990802899da..17fa5c4e3ad1 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -90,6 +90,7 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_ARC=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y CONFIG_SWAP_IO_SPACE=y diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index 2759162f173b..b26e1173365d 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -84,6 +84,7 @@ CONFIG_ARC=y CONFIG_DMA_IP32=y CONFIG_OWN_DMA=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_ARC32=y CONFIG_BOOT_ELF32=y diff --git a/arch/mips/configs/it8172_defconfig b/arch/mips/configs/it8172_defconfig index 09c83a01dd92..08bd3ad64761 100644 --- a/arch/mips/configs/it8172_defconfig +++ b/arch/mips/configs/it8172_defconfig @@ -90,6 +90,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_ITE_BOARD_GEN=y CONFIG_IT8172_CIR=y diff --git a/arch/mips/configs/ivr_defconfig b/arch/mips/configs/ivr_defconfig index 121d0c029c5d..583ef5c5b1cd 100644 --- a/arch/mips/configs/ivr_defconfig +++ b/arch/mips/configs/ivr_defconfig @@ -89,6 +89,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_ITE_BOARD_GEN=y CONFIG_IT8172_CIR=y diff --git a/arch/mips/configs/jaguar-atx_defconfig b/arch/mips/configs/jaguar-atx_defconfig index d4e19da57d70..8abb5a0c6c12 100644 --- a/arch/mips/configs/jaguar-atx_defconfig +++ b/arch/mips/configs/jaguar-atx_defconfig @@ -81,6 +81,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_LIMITED_DMA=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index c95e52a9d8bb..da5d9ee2ecce 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig @@ -82,6 +82,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_MIPS_TX3927=y CONFIG_SWAP_IO_SPACE=y diff --git a/arch/mips/configs/lasat200_defconfig b/arch/mips/configs/lasat200_defconfig index 3b4d7e6afac4..8d600ae890f4 100644 --- a/arch/mips/configs/lasat200_defconfig +++ b/arch/mips/configs/lasat200_defconfig @@ -92,6 +92,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_MIPS_NILE4=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_MIPS_GT64120=y diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 33e6bb62f2ea..79519ac5af4a 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -88,6 +88,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_GENERIC_ISA_DMA=y CONFIG_I8259=y CONFIG_MIPS_BONITO64=y diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig index ed44a1a660f7..0fea57ef18f2 100644 --- a/arch/mips/configs/mpc30x_defconfig +++ b/arch/mips/configs/mpc30x_defconfig @@ -97,6 +97,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/configs/ocelot_3_defconfig b/arch/mips/configs/ocelot_3_defconfig index daa5b8828f57..b4cf97a732bc 100644 --- a/arch/mips/configs/ocelot_3_defconfig +++ b/arch/mips/configs/ocelot_3_defconfig @@ -89,6 +89,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y diff --git a/arch/mips/configs/ocelot_c_defconfig b/arch/mips/configs/ocelot_c_defconfig index bdefd4f1310a..a38903db85a0 100644 --- a/arch/mips/configs/ocelot_c_defconfig +++ b/arch/mips/configs/ocelot_c_defconfig @@ -80,6 +80,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y CONFIG_IRQ_MV64340=y diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig index 7526b4748dfe..920d59b56a4e 100644 --- a/arch/mips/configs/ocelot_defconfig +++ b/arch/mips/configs/ocelot_defconfig @@ -82,6 +82,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/ocelot_g_defconfig index f372508bc25b..ef5ea50893d1 100644 --- a/arch/mips/configs/ocelot_g_defconfig +++ b/arch/mips/configs/ocelot_g_defconfig @@ -80,6 +80,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index b7b95789fefb..813e3a8b480b 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig @@ -104,6 +104,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SWAP_IO_SPACE=y # CONFIG_AU1X00_USB_DEVICE is not set diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index 021cfe38371a..17d4fce6c4c6 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -91,6 +91,7 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_ARC=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_GENERIC_ISA_DMA=y CONFIG_I8259=y CONFIG_CPU_LITTLE_ENDIAN=y diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig index 4d2fde827f01..dd07e866b128 100644 --- a/arch/mips/configs/sead_defconfig +++ b/arch/mips/configs/sead_defconfig @@ -80,6 +80,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_BOARDS_GEN=y diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index 53e3d4adf1dd..c9d3f83caf0f 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig @@ -95,6 +95,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/configs/tb0229_defconfig b/arch/mips/configs/tb0229_defconfig index 0fe7f505226e..2cb669188aa9 100644 --- a/arch/mips/configs/tb0229_defconfig +++ b/arch/mips/configs/tb0229_defconfig @@ -98,6 +98,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig index d793616effbb..16e07fca446f 100644 --- a/arch/mips/configs/workpad_defconfig +++ b/arch/mips/configs/workpad_defconfig @@ -96,6 +96,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/defconfig b/arch/mips/defconfig index 2081583daabc..20f84b119b4c 100644 --- a/arch/mips/defconfig +++ b/arch/mips/defconfig @@ -90,6 +90,7 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_ARC=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y CONFIG_SWAP_IO_SPACE=y diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index d70dc355c1f3..092900f11654 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -94,7 +94,7 @@ struct pci_dev; */ extern unsigned int PCI_DMA_BUS_IS_PHYS; -#ifdef CONFIG_MAPPED_DMA_IO +#ifdef CONFIG_DMA_NEED_PCI_MAP_STATE /* pci_unmap_{single,page} is not a nop, thus... */ #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME; @@ -104,7 +104,7 @@ extern unsigned int PCI_DMA_BUS_IS_PHYS; #define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) -#else /* CONFIG_MAPPED_DMA_IO */ +#else /* CONFIG_DMA_NEED_PCI_MAP_STATE */ /* pci_unmap_{page,single} is a nop so... */ #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) @@ -114,7 +114,7 @@ extern unsigned int PCI_DMA_BUS_IS_PHYS; #define pci_unmap_len(PTR, LEN_NAME) (0) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) -#endif /* CONFIG_MAPPED_DMA_IO */ +#endif /* CONFIG_DMA_NEED_PCI_MAP_STATE */ /* This is always fine. */ #define pci_dac_dma_supported(pci_dev, mask) (1) -- cgit v1.2.3 From e63ea56fe2669c20f4668d89522500f4ab439b04 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sat, 3 Sep 2005 15:56:20 -0700 Subject: [PATCH] mips: add pcibios_bus_to_resource This patch has added pcibios_bus_to_resource to MIPS. Signed-off-by: Yoichi Yuasa Cc: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/pci/pci.c | 17 +++++++++++++++++ include/asm-mips/pci.h | 2 ++ 2 files changed, 19 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 8a5b52250bda..a8d499b0a36f 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -292,8 +292,25 @@ pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, region->end = res->end - offset; } +void __devinit +pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, + struct pci_bus_region *region) +{ + struct pci_controller *hose = (struct pci_controller *)dev->sysdata; + unsigned long offset = 0; + + if (res->flags & IORESOURCE_IO) + offset = hose->io_offset; + else if (res->flags & IORESOURCE_MEM) + offset = hose->mem_offset; + + res->start = region->start + offset; + res->end = region->end + offset; +} + #ifdef CONFIG_HOTPLUG EXPORT_SYMBOL(pcibios_resource_to_bus); +EXPORT_SYMBOL(pcibios_bus_to_resource); EXPORT_SYMBOL(PCIBIOS_MIN_IO); EXPORT_SYMBOL(PCIBIOS_MIN_MEM); #endif diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index 049f01f648ed..c9a00ca1c012 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -142,6 +142,8 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, extern void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res); +extern void pcibios_bus_to_resource(struct pci_dev *dev, + struct resource *res, struct pci_bus_region *region); #ifdef CONFIG_PCI_DOMAINS -- cgit v1.2.3 From ed5ba2fbc6d03c41c4c3334648a6569bc42da764 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sat, 3 Sep 2005 15:56:21 -0700 Subject: [PATCH] mips: add more SYS_SUPPORT_*_KERNEL and CPU_SUPPORTS_*_KERNEL The addtion of SYS_SUPPORTS_*_KERNEL and CPU_SUPPORTS_*_KERNEL is halfway. This patch has added more SYS_SUPPORTS_*_KERNEL and CPU_SUPPORTS_*_KERNEL to arch/mips/Kconfig. Please apply. Signed-off-by: Yoichi Yuasa Cc: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/Kconfig | 105 ++++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 94 insertions(+), 11 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 60ba382ea7f3..d79fba0aa8bf 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -8,6 +8,15 @@ mainmenu "Linux/MIPS Kernel Configuration" source "init/Kconfig" +config SYS_SUPPORTS_32BIT_KERNEL + bool +config SYS_SUPPORTS_64BIT_KERNEL + bool +config CPU_SUPPORTS_32BIT_KERNEL + bool +config CPU_SUPPORTS_64BIT_KERNEL + bool + menu "Kernel type" choice @@ -45,6 +54,8 @@ config MACH_JAZZ select GENERIC_ISA_DMA select I8259 select ISA + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL help This a family of machines based on the MIPS R4030 chipset which was used by several vendors to build RISC/os and Windows NT workstations. @@ -83,6 +94,8 @@ config OLIVETTI_M700 config MACH_VR41XX bool "Support for NEC VR4100 series based machines" + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL config NEC_CMBVR4133 bool "Support for NEC CMB-VR4133" @@ -166,25 +179,28 @@ config VRC4173 config TOSHIBA_JMR3927 bool "Support for Toshiba JMR-TX3927 board" - depends on 32BIT select DMA_NONCOHERENT select HW_HAS_PCI select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL config MIPS_COBALT - bool "Support for Cobalt Server (EXPERIMENTAL)" + bool "Support for Cobalt Server" depends on EXPERIMENTAL select DMA_NONCOHERENT select HW_HAS_PCI select I8259 select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL config MACH_DECSTATION bool "Support for DECstations" select BOOT_ELF32 select DMA_NONCOHERENT select IRQ_CPU - depends on 32BIT || EXPERIMENTAL + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL ---help--- This enables support for DEC's MIPS based workstations. For details see the Linux/MIPS FAQ on and the @@ -206,6 +222,8 @@ config MIPS_EV64120 select DMA_NONCOHERENT select HW_HAS_PCI select MIPS_GT64120 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help This is an evaluation board based on the Galileo GT-64120 single-chip system controller that contains a MIPS R5000 compatible @@ -226,6 +244,8 @@ config MIPS_EV96100 select MIPS_GT96100 select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help This is an evaluation board based on the Galileo GT-96100 LAN/WAN communications controllers containing a MIPS R5000 compatible core @@ -236,6 +256,8 @@ config MIPS_IVR bool "Support for Globespan IVR board" select DMA_NONCOHERENT select HW_HAS_PCI + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL help This is an evaluation board built by Globespan to showcase thir iVR (Internet Video Recorder) design. It utilizes a QED RM5231 @@ -249,6 +271,8 @@ config LASAT select HW_HAS_PCI select MIPS_GT64120 select R5000_CPU_SCACHE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL config PICVUE tristate "PICVUE LCD display driver" @@ -270,6 +294,8 @@ config MIPS_ITE8172 bool "Support for ITE 8172G board" select DMA_NONCOHERENT select HW_HAS_PCI + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL help Ths is an evaluation board made by ITE with ATX form factor that utilizes a MIPS R5000 to work with its @@ -293,6 +319,8 @@ config MIPS_ATLAS select HW_HAS_PCI select MIPS_GT64120 select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help This enables support for the QED R5231-based MIPS Atlas evaluation board. @@ -307,6 +335,8 @@ config MIPS_MALTA select I8259 select MIPS_GT64120 select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help This enables support for the VR5000-based MIPS Malta evaluation board. @@ -316,6 +346,8 @@ config MIPS_SEAD depends on EXPERIMENTAL select IRQ_CPU select DMA_NONCOHERENT + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL config MOMENCO_OCELOT bool "Support for Momentum Ocelot board" @@ -326,6 +358,8 @@ config MOMENCO_OCELOT select MIPS_GT64120 select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help The Ocelot is a MIPS-based Single Board Computer (SBC) made by Momentum Computer . @@ -339,6 +373,8 @@ config MOMENCO_OCELOT_G select PCI_MARVELL select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help The Ocelot is a MIPS-based Single Board Computer (SBC) made by Momentum Computer . @@ -352,6 +388,8 @@ config MOMENCO_OCELOT_C select PCI_MARVELL select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help The Ocelot is a MIPS-based Single Board Computer (SBC) made by Momentum Computer . @@ -367,6 +405,8 @@ config MOMENCO_OCELOT_3 select PCI_MARVELL select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help The Ocelot-3 is based off Discovery III System Controller and PMC-Sierra Rm79000 core. @@ -383,6 +423,8 @@ config MOMENCO_JAGUAR_ATX select PCI_MARVELL select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by Momentum Computer . @@ -402,6 +444,8 @@ config PMC_YOSEMITE select IRQ_CPU_RM7K select IRQ_CPU_RM9K select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help Yosemite is an evaluation board for the RM9000x2 processor manufactured by PMC-Sierra @@ -419,6 +463,8 @@ config DDB5074 select IRQ_CPU select I8259 select ISA + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help This enables support for the VR5000-based NEC DDB Vrc-5074 evaluation board. @@ -431,6 +477,8 @@ config DDB5476 select IRQ_CPU select I8259 select ISA + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL help This enables support for the R5432-based NEC DDB Vrc-5476 evaluation board. @@ -445,6 +493,8 @@ config DDB5477 select HW_HAS_PCI select I8259 select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL help This enables support for the R5432-based NEC DDB Vrc-5477, or Rockhopper/SolutionGear boards with R5432/R5500 CPUs. @@ -484,6 +534,8 @@ config SGI_IP22 select IP22_CPU_SCACHE select IRQ_CPU select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help This are the SGI Indy, Challenge S and Indigo2, as well as certain OEM variants like the Tandem CMN B006S. To compile a Linux kernel @@ -491,12 +543,12 @@ config SGI_IP22 config SGI_IP27 bool "Support for SGI IP27 (Origin200/2000)" - depends on 64BIT select ARC select ARC64 select DMA_IP27 select HW_HAS_PCI select PCI_DOMAINS + select SYS_SUPPORTS_64BIT_KERNEL help This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics workstations. To compile a Linux kernel that runs on these, say Y @@ -559,7 +611,7 @@ config REPLICATE_EXHANDLERS config SGI_IP32 bool "Support for SGI IP32 (O2) (EXPERIMENTAL)" - depends on 64BIT && EXPERIMENTAL + depends on EXPERIMENTAL select ARC select ARC32 select BOOT_ELF32 @@ -569,12 +621,13 @@ config SGI_IP32 select HW_HAS_PCI select R5000_CPU_SCACHE select RM7000_CPU_SCACHE + select SYS_SUPPORTS_64BIT_KERNEL help If you want this kernel to run on SGI O2 workstation, say Y here. config SOC_AU1X00 - depends on 32BIT bool "Support for AMD/Alchemy Au1X00 SOCs" + select SYS_SUPPORTS_32BIT_KERNEL choice prompt "Au1X00 SOC Type" @@ -686,6 +739,8 @@ config SIBYTE_SB1xxx_SOC select BOOT_ELF32 select DMA_COHERENT select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL choice prompt "BCM1xxx SOC-based board" @@ -905,6 +960,8 @@ config SNI_RM200_PCI select HW_HAS_PCI select I8259 select ISA + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL help The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid @@ -913,13 +970,14 @@ config SNI_RM200_PCI config TOSHIBA_RBTX4927 bool "Support for Toshiba TBTX49[23]7 board" - depends on 32BIT select DMA_NONCOHERENT select HAS_TXX9_SERIAL select HW_HAS_PCI select I8259 select ISA select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help This Toshiba board is based on the TX4927 processor. Say Y here to support this machine type @@ -1173,13 +1231,16 @@ choice config CPU_MIPS32 bool "MIPS32" + select CPU_SUPPORTS_32BIT_KERNEL config CPU_MIPS64 bool "MIPS64" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL config CPU_R3000 bool "R3000" - depends on MIPS32 + select CPU_SUPPORTS_32BIT_KERNEL help Please make sure to pick the right CPU type. Linux/MIPS is not designed to be generic, i.e. Kernels compiled for R3000 CPUs will @@ -1190,10 +1251,12 @@ config CPU_R3000 config CPU_TX39XX bool "R39XX" - depends on 32BIT + select CPU_SUPPORTS_32BIT_KERNEL config CPU_VR41XX bool "R41xx" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL help The options selects support for the NEC VR41xx series of processors. Only choose this option if you have one of these processors as a @@ -1202,20 +1265,28 @@ config CPU_VR41XX config CPU_R4300 bool "R4300" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL help MIPS Technologies R4300-series processors. config CPU_R4X00 bool "R4x00" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL help MIPS Technologies R4000-series processors other than 4300, including the R4000, R4400, R4600, and 4700. config CPU_TX49XX bool "R49XX" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL config CPU_R5000 bool "R5000" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL help MIPS Technologies R5000-series processors other than the Nevada. @@ -1224,36 +1295,48 @@ config CPU_R5432 config CPU_R6000 bool "R6000" - depends on 32BIT && EXPERIMENTAL + depends on EXPERIMENTAL + select CPU_SUPPORTS_32BIT_KERNEL help MIPS Technologies R6000 and R6000A series processors. Note these processors are extremly rare and the support for them is incomplete. config CPU_NEVADA bool "RM52xx" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL help QED / PMC-Sierra RM52xx-series ("Nevada") processors. config CPU_R8000 bool "R8000" - depends on 64BIT && EXPERIMENTAL + depends on EXPERIMENTAL + select CPU_SUPPORTS_64BIT_KERNEL help MIPS Technologies R8000 processors. Note these processors are uncommon and the support for them is incomplete. config CPU_R10000 bool "R10000" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL help MIPS Technologies R10000-series processors. config CPU_RM7000 bool "RM7000" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL config CPU_RM9000 bool "RM9000" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL config CPU_SB1 bool "SB1" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL endchoice -- cgit v1.2.3 From 766160c29fadbafad1d6eb5e965922c7e78beb88 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sat, 3 Sep 2005 15:56:22 -0700 Subject: [PATCH] mips: fix build warnings This patch has fixed the following warnings. arch/mips/kernel/genex.S:250:5: warning: "CONFIG_64BIT" is not defined arch/mips/math-emu/cp1emu.c:1128:5: warning: "__mips64" is not defined arch/mips/math-emu/cp1emu.c:1206:5: warning: "__mips64" is not defined arch/mips/math-emu/cp1emu.c:1270:5: warning: "__mips64" is not defined arch/mips/math-emu/cp1emu.c:323:5: warning: "__mips64" is not defined arch/mips/math-emu/cp1emu.c:808:5: warning: "__mips64" is not defined arch/mips/math-emu/cp1emu.c:953:5: warning: "__mips64" is not defined arch/mips/mm/tlbex.c:519:5: warning: "CONFIG_64BIT" is not defined include/asm/reg.h:73:5: warning: "CONFIG_64BIT" is not defined Signed-off-by: Yoichi Yuasa Cc: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/kernel/genex.S | 4 ++-- arch/mips/math-emu/cp1emu.c | 12 ++++++------ arch/mips/mm/tlbex.c | 2 +- include/asm-mips/reg.h | 2 +- 4 files changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 9bb2caaf7fc6..e7f6c1b90806 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -244,10 +244,10 @@ NESTED(nmi_handler, PT_SIZE, sp) start with an n and gas will believe \n is ok ... */ .macro __BUILD_verbose nexception LONG_L a1, PT_EPC(sp) -#if CONFIG_32BIT +#ifdef CONFIG_32BIT PRINT("Got \nexception at %08lx\012") #endif -#if CONFIG_64BIT +#ifdef CONFIG_64BIT PRINT("Got \nexception at %016lx\012") #endif .endm diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 20a552be02ee..99c550632d44 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -320,7 +320,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) case cop1_op: switch (MIPSInst_RS(ir)) { -#if __mips64 && !defined(SINGLE_ONLY_FPU) +#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) case dmfc_op: /* copregister fs -> gpr[rt] */ if (MIPSInst_RT(ir) != 0) { @@ -805,7 +805,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, ieee754dp d; ieee754sp s; int w; -#if __mips64 +#ifdef __mips64 s64 l; #endif } rv; /* resulting value */ @@ -950,7 +950,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, } #endif /* __mips >= 2 */ -#if __mips64 && !defined(SINGLE_ONLY_FPU) +#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) case fcvtl_op:{ ieee754sp fs; @@ -1125,7 +1125,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, } #endif -#if __mips64 && !defined(SINGLE_ONLY_FPU) +#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) case fcvtl_op:{ ieee754dp fs; @@ -1203,7 +1203,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, break; } -#if __mips64 && !defined(SINGLE_ONLY_FPU) +#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) case l_fmt:{ switch (MIPSInst_FUNC(ir)) { case fcvts_op: @@ -1267,7 +1267,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, case w_fmt: SITOREG(rv.w, MIPSInst_FD(ir)); break; -#if __mips64 && !defined(SINGLE_ONLY_FPU) +#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) case l_fmt: DITOREG(rv.l, MIPSInst_FD(ir)); break; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 592377fa694d..6569be3983c7 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -516,7 +516,7 @@ static __init int rel_lo(long val) static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) { -#if CONFIG_64BIT +#ifdef CONFIG_64BIT if (!in_compat_space_p(addr)) { i_lui(buf, rs, rel_highest(addr)); if (rel_higher(addr)) diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h index a1ebd3aa93af..6173004cc88e 100644 --- a/include/asm-mips/reg.h +++ b/include/asm-mips/reg.h @@ -70,7 +70,7 @@ #endif -#if CONFIG_64BIT +#ifdef CONFIG_64BIT #define EF_R0 0 #define EF_R1 1 -- cgit v1.2.3 From 202e5979af4d91c7ca05892641131dee22653259 Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Tue, 6 Sep 2005 15:16:40 -0700 Subject: [PATCH] compat: be more consistent about [ug]id_t When I first wrote the compat layer patches, I was somewhat cavalier about the definition of compat_uid_t and compat_gid_t (or maybe I just misunderstood :-)). This patch makes the compat types much more consistent with the types we are being compatible with and hopefully will fix a few bugs along the way. compat type type in compat arch __compat_[ug]id_t __kernel_[ug]id_t __compat_[ug]id32_t __kernel_[ug]id32_t compat_[ug]id_t [ug]id_t The difference is that compat_uid_t is always 32 bits (for the archs we care about) but __compat_uid_t may be 16 bits on some. Signed-off-by: Stephen Rothwell Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/kernel/linux32.c | 16 ++++++++-------- fs/compat.c | 16 ++++++++-------- include/asm-ia64/compat.h | 20 ++++++++++---------- include/asm-mips/compat.h | 10 ++++++---- include/asm-parisc/compat.h | 10 ++++++---- include/asm-ppc64/compat.h | 18 ++++++++++-------- include/asm-s390/compat.h | 20 ++++++++++---------- include/asm-sparc64/compat.h | 18 ++++++++++-------- include/asm-x86_64/compat.h | 20 ++++++++++---------- include/linux/compat.h | 3 +++ ipc/compat.c | 12 ++++++------ 11 files changed, 87 insertions(+), 76 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index 4613219dd73e..ece4564919d8 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -546,20 +546,20 @@ struct msgbuf32 { s32 mtype; char mtext[1]; }; struct ipc_perm32 { key_t key; - compat_uid_t uid; - compat_gid_t gid; - compat_uid_t cuid; - compat_gid_t cgid; + __compat_uid_t uid; + __compat_gid_t gid; + __compat_uid_t cuid; + __compat_gid_t cgid; compat_mode_t mode; unsigned short seq; }; struct ipc64_perm32 { key_t key; - compat_uid_t uid; - compat_gid_t gid; - compat_uid_t cuid; - compat_gid_t cgid; + __compat_uid_t uid; + __compat_gid_t gid; + __compat_uid_t cuid; + __compat_gid_t cgid; compat_mode_t mode; unsigned short seq; unsigned short __pad1; diff --git a/fs/compat.c b/fs/compat.c index 6b06b6bae35e..8e03d31eec3b 100644 --- a/fs/compat.c +++ b/fs/compat.c @@ -720,14 +720,14 @@ compat_sys_io_submit(aio_context_t ctx_id, int nr, u32 __user *iocb) struct compat_ncp_mount_data { compat_int_t version; compat_uint_t ncp_fd; - compat_uid_t mounted_uid; + __compat_uid_t mounted_uid; compat_pid_t wdog_pid; unsigned char mounted_vol[NCP_VOLNAME_LEN + 1]; compat_uint_t time_out; compat_uint_t retry_count; compat_uint_t flags; - compat_uid_t uid; - compat_gid_t gid; + __compat_uid_t uid; + __compat_gid_t gid; compat_mode_t file_mode; compat_mode_t dir_mode; }; @@ -784,9 +784,9 @@ static void *do_ncp_super_data_conv(void *raw_data) struct compat_smb_mount_data { compat_int_t version; - compat_uid_t mounted_uid; - compat_uid_t uid; - compat_gid_t gid; + __compat_uid_t mounted_uid; + __compat_uid_t uid; + __compat_gid_t gid; compat_mode_t file_mode; compat_mode_t dir_mode; }; @@ -1808,8 +1808,8 @@ struct compat_nfsctl_export { compat_dev_t ex32_dev; compat_ino_t ex32_ino; compat_int_t ex32_flags; - compat_uid_t ex32_anon_uid; - compat_gid_t ex32_anon_gid; + __compat_uid_t ex32_anon_uid; + __compat_gid_t ex32_anon_gid; }; struct compat_nfsctl_fdparm { diff --git a/include/asm-ia64/compat.h b/include/asm-ia64/compat.h index 0c05e5bad8a0..aaf11f4e9169 100644 --- a/include/asm-ia64/compat.h +++ b/include/asm-ia64/compat.h @@ -13,10 +13,10 @@ typedef s32 compat_time_t; typedef s32 compat_clock_t; typedef s32 compat_key_t; typedef s32 compat_pid_t; -typedef u16 compat_uid_t; -typedef u16 compat_gid_t; -typedef u32 compat_uid32_t; -typedef u32 compat_gid32_t; +typedef u16 __compat_uid_t; +typedef u16 __compat_gid_t; +typedef u32 __compat_uid32_t; +typedef u32 __compat_gid32_t; typedef u16 compat_mode_t; typedef u32 compat_ino_t; typedef u16 compat_dev_t; @@ -50,8 +50,8 @@ struct compat_stat { compat_ino_t st_ino; compat_mode_t st_mode; compat_nlink_t st_nlink; - compat_uid_t st_uid; - compat_gid_t st_gid; + __compat_uid_t st_uid; + __compat_gid_t st_gid; compat_dev_t st_rdev; u16 __pad2; u32 st_size; @@ -120,10 +120,10 @@ typedef u32 compat_sigset_word; struct compat_ipc64_perm { compat_key_t key; - compat_uid32_t uid; - compat_gid32_t gid; - compat_uid32_t cuid; - compat_gid32_t cgid; + __compat_uid32_t uid; + __compat_gid32_t gid; + __compat_uid32_t cuid; + __compat_gid32_t cgid; unsigned short mode; unsigned short __pad1; unsigned short seq; diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h index d78002afb1e1..2c084cd4bc0a 100644 --- a/include/asm-mips/compat.h +++ b/include/asm-mips/compat.h @@ -15,8 +15,10 @@ typedef s32 compat_clock_t; typedef s32 compat_suseconds_t; typedef s32 compat_pid_t; -typedef s32 compat_uid_t; -typedef s32 compat_gid_t; +typedef u32 __compat_uid_t; +typedef u32 __compat_gid_t; +typedef u32 __compat_uid32_t; +typedef u32 __compat_gid32_t; typedef u32 compat_mode_t; typedef u32 compat_ino_t; typedef u32 compat_dev_t; @@ -52,8 +54,8 @@ struct compat_stat { compat_ino_t st_ino; compat_mode_t st_mode; compat_nlink_t st_nlink; - compat_uid_t st_uid; - compat_gid_t st_gid; + __compat_uid32_t st_uid; + __compat_gid32_t st_gid; compat_dev_t st_rdev; s32 st_pad2[2]; compat_off_t st_size; diff --git a/include/asm-parisc/compat.h b/include/asm-parisc/compat.h index 7630d1ad2391..38b918feead9 100644 --- a/include/asm-parisc/compat.h +++ b/include/asm-parisc/compat.h @@ -13,8 +13,10 @@ typedef s32 compat_ssize_t; typedef s32 compat_time_t; typedef s32 compat_clock_t; typedef s32 compat_pid_t; -typedef u32 compat_uid_t; -typedef u32 compat_gid_t; +typedef u32 __compat_uid_t; +typedef u32 __compat_gid_t; +typedef u32 __compat_uid32_t; +typedef u32 __compat_gid32_t; typedef u16 compat_mode_t; typedef u32 compat_ino_t; typedef u32 compat_dev_t; @@ -67,8 +69,8 @@ struct compat_stat { compat_dev_t st_realdev; u16 st_basemode; u16 st_spareshort; - compat_uid_t st_uid; - compat_gid_t st_gid; + __compat_uid32_t st_uid; + __compat_gid32_t st_gid; u32 st_spare4[3]; }; diff --git a/include/asm-ppc64/compat.h b/include/asm-ppc64/compat.h index 12414f5fc666..6ec62cd2d1d1 100644 --- a/include/asm-ppc64/compat.h +++ b/include/asm-ppc64/compat.h @@ -13,8 +13,10 @@ typedef s32 compat_ssize_t; typedef s32 compat_time_t; typedef s32 compat_clock_t; typedef s32 compat_pid_t; -typedef u32 compat_uid_t; -typedef u32 compat_gid_t; +typedef u32 __compat_uid_t; +typedef u32 __compat_gid_t; +typedef u32 __compat_uid32_t; +typedef u32 __compat_gid32_t; typedef u32 compat_mode_t; typedef u32 compat_ino_t; typedef u32 compat_dev_t; @@ -48,8 +50,8 @@ struct compat_stat { compat_ino_t st_ino; compat_mode_t st_mode; compat_nlink_t st_nlink; - compat_uid_t st_uid; - compat_gid_t st_gid; + __compat_uid32_t st_uid; + __compat_gid32_t st_gid; compat_dev_t st_rdev; compat_off_t st_size; compat_off_t st_blksize; @@ -144,10 +146,10 @@ static inline void __user *compat_alloc_user_space(long len) */ struct compat_ipc64_perm { compat_key_t key; - compat_uid_t uid; - compat_gid_t gid; - compat_uid_t cuid; - compat_gid_t cgid; + __compat_uid_t uid; + __compat_gid_t gid; + __compat_uid_t cuid; + __compat_gid_t cgid; compat_mode_t mode; unsigned int seq; unsigned int __pad2; diff --git a/include/asm-s390/compat.h b/include/asm-s390/compat.h index 7f8f544eb262..a007715f4aea 100644 --- a/include/asm-s390/compat.h +++ b/include/asm-s390/compat.h @@ -13,10 +13,10 @@ typedef s32 compat_ssize_t; typedef s32 compat_time_t; typedef s32 compat_clock_t; typedef s32 compat_pid_t; -typedef u16 compat_uid_t; -typedef u16 compat_gid_t; -typedef u32 compat_uid32_t; -typedef u32 compat_gid32_t; +typedef u16 __compat_uid_t; +typedef u16 __compat_gid_t; +typedef u32 __compat_uid32_t; +typedef u32 __compat_gid32_t; typedef u16 compat_mode_t; typedef u32 compat_ino_t; typedef u16 compat_dev_t; @@ -51,8 +51,8 @@ struct compat_stat { compat_ino_t st_ino; compat_mode_t st_mode; compat_nlink_t st_nlink; - compat_uid_t st_uid; - compat_gid_t st_gid; + __compat_uid_t st_uid; + __compat_gid_t st_gid; compat_dev_t st_rdev; u16 __pad2; u32 st_size; @@ -140,10 +140,10 @@ static inline void __user *compat_alloc_user_space(long len) struct compat_ipc64_perm { compat_key_t key; - compat_uid32_t uid; - compat_gid32_t gid; - compat_uid32_t cuid; - compat_gid32_t cgid; + __compat_uid32_t uid; + __compat_gid32_t gid; + __compat_uid32_t cuid; + __compat_gid32_t cgid; compat_mode_t mode; unsigned short __pad1; unsigned short seq; diff --git a/include/asm-sparc64/compat.h b/include/asm-sparc64/compat.h index b59122dd176d..c73935dc7ba1 100644 --- a/include/asm-sparc64/compat.h +++ b/include/asm-sparc64/compat.h @@ -12,8 +12,10 @@ typedef s32 compat_ssize_t; typedef s32 compat_time_t; typedef s32 compat_clock_t; typedef s32 compat_pid_t; -typedef u16 compat_uid_t; -typedef u16 compat_gid_t; +typedef u16 __compat_uid_t; +typedef u16 __compat_gid_t; +typedef u32 __compat_uid32_t; +typedef u32 __compat_gid32_t; typedef u16 compat_mode_t; typedef u32 compat_ino_t; typedef u16 compat_dev_t; @@ -47,8 +49,8 @@ struct compat_stat { compat_ino_t st_ino; compat_mode_t st_mode; compat_nlink_t st_nlink; - compat_uid_t st_uid; - compat_gid_t st_gid; + __compat_uid_t st_uid; + __compat_gid_t st_gid; compat_dev_t st_rdev; compat_off_t st_size; compat_time_t st_atime; @@ -177,10 +179,10 @@ static __inline__ void __user *compat_alloc_user_space(long len) struct compat_ipc64_perm { compat_key_t key; - __kernel_uid_t uid; - __kernel_gid_t gid; - __kernel_uid_t cuid; - __kernel_gid_t cgid; + __compat_uid32_t uid; + __compat_gid32_t gid; + __compat_uid32_t cuid; + __compat_gid32_t cgid; unsigned short __pad1; compat_mode_t mode; unsigned short __pad2; diff --git a/include/asm-x86_64/compat.h b/include/asm-x86_64/compat.h index d0f453c5adfc..f0155c38f639 100644 --- a/include/asm-x86_64/compat.h +++ b/include/asm-x86_64/compat.h @@ -14,10 +14,10 @@ typedef s32 compat_ssize_t; typedef s32 compat_time_t; typedef s32 compat_clock_t; typedef s32 compat_pid_t; -typedef u16 compat_uid_t; -typedef u16 compat_gid_t; -typedef u32 compat_uid32_t; -typedef u32 compat_gid32_t; +typedef u16 __compat_uid_t; +typedef u16 __compat_gid_t; +typedef u32 __compat_uid32_t; +typedef u32 __compat_gid32_t; typedef u16 compat_mode_t; typedef u32 compat_ino_t; typedef u16 compat_dev_t; @@ -52,8 +52,8 @@ struct compat_stat { compat_ino_t st_ino; compat_mode_t st_mode; compat_nlink_t st_nlink; - compat_uid_t st_uid; - compat_gid_t st_gid; + __compat_uid_t st_uid; + __compat_gid_t st_gid; compat_dev_t st_rdev; u16 __pad2; u32 st_size; @@ -122,10 +122,10 @@ typedef u32 compat_sigset_word; struct compat_ipc64_perm { compat_key_t key; - compat_uid32_t uid; - compat_gid32_t gid; - compat_uid32_t cuid; - compat_gid32_t cgid; + __compat_uid32_t uid; + __compat_gid32_t gid; + __compat_uid32_t cuid; + __compat_gid32_t cgid; unsigned short mode; unsigned short __pad1; unsigned short seq; diff --git a/include/linux/compat.h b/include/linux/compat.h index b58b7d6f2fdb..f9ca534787e2 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -18,6 +18,9 @@ #define compat_jiffies_to_clock_t(x) \ (((unsigned long)(x) * COMPAT_USER_HZ) / HZ) +typedef __compat_uid32_t compat_uid_t; +typedef __compat_gid32_t compat_gid_t; + struct rusage; struct compat_itimerspec { diff --git a/ipc/compat.c b/ipc/compat.c index 3881d564c668..1fe95f6659dd 100644 --- a/ipc/compat.c +++ b/ipc/compat.c @@ -42,10 +42,10 @@ struct compat_msgbuf { struct compat_ipc_perm { key_t key; - compat_uid_t uid; - compat_gid_t gid; - compat_uid_t cuid; - compat_gid_t cgid; + __compat_uid_t uid; + __compat_gid_t gid; + __compat_uid_t cuid; + __compat_gid_t cgid; compat_mode_t mode; unsigned short seq; }; @@ -174,8 +174,8 @@ static inline int __put_compat_ipc_perm(struct ipc64_perm *p, struct compat_ipc_perm __user *up) { int err; - compat_uid_t u; - compat_gid_t g; + __compat_uid_t u; + __compat_gid_t g; err = __put_user(p->key, &up->key); SET_UID(u, p->uid); -- cgit v1.2.3 From b149ee2233edf08fb59b11e879a2c5941929bcb8 Mon Sep 17 00:00:00 2001 From: john stultz Date: Tue, 6 Sep 2005 15:17:46 -0700 Subject: [PATCH] NTP: ntp-helper functions This patch cleans up a commonly repeated set of changes to the NTP state variables by adding two helper inline functions: ntp_clear(): Clears the ntp state variables ntp_synced(): Returns 1 if the system is synced with a time server. This was compile tested for alpha, arm, i386, x86-64, ppc64, s390, sparc, sparc64. Signed-off-by: John Stultz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/alpha/kernel/time.c | 7 ++----- arch/arm/kernel/time.c | 7 ++----- arch/arm26/kernel/time.c | 7 ++----- arch/cris/arch-v10/kernel/time.c | 2 +- arch/cris/kernel/time.c | 5 +---- arch/frv/kernel/time.c | 7 ++----- arch/h8300/kernel/time.c | 5 +---- arch/i386/kernel/time.c | 7 ++----- arch/m32r/kernel/time.c | 7 ++----- arch/m68k/kernel/time.c | 5 +---- arch/m68knommu/kernel/time.c | 7 ++----- arch/mips/kernel/sysirix.c | 5 +---- arch/mips/kernel/time.c | 7 ++----- arch/mips/sgi-ip27/ip27-timer.c | 2 +- arch/parisc/kernel/time.c | 5 +---- arch/ppc/kernel/time.c | 7 ++----- arch/ppc64/kernel/time.c | 7 ++----- arch/s390/kernel/time.c | 5 +---- arch/sh/kernel/time.c | 7 ++----- arch/sh64/kernel/time.c | 7 ++----- arch/sparc/kernel/pcic.c | 5 +---- arch/sparc/kernel/time.c | 7 ++----- arch/sparc64/kernel/time.c | 2 +- arch/v850/kernel/time.c | 7 ++----- arch/x86_64/kernel/time.c | 7 ++----- arch/xtensa/kernel/time.c | 7 ++----- include/linux/timex.h | 23 +++++++++++++++++++++++ 27 files changed, 65 insertions(+), 111 deletions(-) (limited to 'arch/mips') diff --git a/arch/alpha/kernel/time.c b/arch/alpha/kernel/time.c index 8226c5cd788c..67be50b7d80a 100644 --- a/arch/alpha/kernel/time.c +++ b/arch/alpha/kernel/time.c @@ -149,7 +149,7 @@ irqreturn_t timer_interrupt(int irq, void *dev, struct pt_regs * regs) * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be * called as close as possible to 500 ms before the new second starts. */ - if ((time_status & STA_UNSYNC) == 0 + if (ntp_synced() && xtime.tv_sec > state.last_rtc_update + 660 && xtime.tv_nsec >= 500000 - ((unsigned) TICK_SIZE) / 2 && xtime.tv_nsec <= 500000 + ((unsigned) TICK_SIZE) / 2) { @@ -502,10 +502,7 @@ do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 8880482dcbff..69449a818dcc 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -102,7 +102,7 @@ static unsigned long next_rtc_update; */ static inline void do_set_rtc(void) { - if (time_status & STA_UNSYNC || set_rtc == NULL) + if (!ntp_synced() || set_rtc == NULL) return; if (next_rtc_update && @@ -292,10 +292,7 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); return 0; diff --git a/arch/arm26/kernel/time.c b/arch/arm26/kernel/time.c index 549a6b2e177e..e66aedd02fad 100644 --- a/arch/arm26/kernel/time.c +++ b/arch/arm26/kernel/time.c @@ -114,7 +114,7 @@ static unsigned long next_rtc_update; */ static inline void do_set_rtc(void) { - if (time_status & STA_UNSYNC || set_rtc == NULL) + if (!ntp_synced() || set_rtc == NULL) return; //FIXME - timespec.tv_sec is a time_t not unsigned long @@ -189,10 +189,7 @@ int do_settimeofday(struct timespec *tv) xtime.tv_sec = tv->tv_sec; xtime.tv_nsec = tv->tv_nsec; - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); return 0; diff --git a/arch/cris/arch-v10/kernel/time.c b/arch/cris/arch-v10/kernel/time.c index 6b7b4e0802e3..dc3dfe9b4a1a 100644 --- a/arch/cris/arch-v10/kernel/time.c +++ b/arch/cris/arch-v10/kernel/time.c @@ -240,7 +240,7 @@ timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) * The division here is not time critical since it will run once in * 11 minutes */ - if ((time_status & STA_UNSYNC) == 0 && + if (ntp_synced() && xtime.tv_sec > last_rtc_update + 660 && (xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 && (xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) { diff --git a/arch/cris/kernel/time.c b/arch/cris/kernel/time.c index fa2d4323da25..a2d99b4aedcd 100644 --- a/arch/cris/kernel/time.c +++ b/arch/cris/kernel/time.c @@ -114,10 +114,7 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); return 0; diff --git a/arch/frv/kernel/time.c b/arch/frv/kernel/time.c index 075db6644694..8d6558b00e44 100644 --- a/arch/frv/kernel/time.c +++ b/arch/frv/kernel/time.c @@ -85,7 +85,7 @@ static irqreturn_t timer_interrupt(int irq, void *dummy, struct pt_regs * regs) * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be * called as close as possible to 500 ms before the new second starts. */ - if ((time_status & STA_UNSYNC) == 0 && + if (ntp_synced() && xtime.tv_sec > last_rtc_update + 660 && (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2 @@ -216,10 +216,7 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); return 0; diff --git a/arch/h8300/kernel/time.c b/arch/h8300/kernel/time.c index 8a600218334d..af8c5d2057dd 100644 --- a/arch/h8300/kernel/time.c +++ b/arch/h8300/kernel/time.c @@ -116,10 +116,7 @@ int do_settimeofday(struct timespec *tv) xtime.tv_sec = tv->tv_sec; xtime.tv_nsec = tv->tv_nsec; - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); return 0; diff --git a/arch/i386/kernel/time.c b/arch/i386/kernel/time.c index 9b94d84a6c3b..eefea7c55008 100644 --- a/arch/i386/kernel/time.c +++ b/arch/i386/kernel/time.c @@ -194,10 +194,7 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); return 0; @@ -347,7 +344,7 @@ static void sync_cmos_clock(unsigned long dummy) * This code is run on a timer. If the clock is set, that timer * may not expire at the correct time. Thus, we adjust... */ - if ((time_status & STA_UNSYNC) != 0) + if (!ntp_synced()) /* * Not synced, exit, do not restart a timer (if one is * running, let it run out). diff --git a/arch/m32r/kernel/time.c b/arch/m32r/kernel/time.c index 8a2b77bc5749..539c562cd54d 100644 --- a/arch/m32r/kernel/time.c +++ b/arch/m32r/kernel/time.c @@ -171,10 +171,7 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); @@ -221,7 +218,7 @@ irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) * called as close as possible to 500 ms before the new second starts. */ write_seqlock(&xtime_lock); - if ((time_status & STA_UNSYNC) == 0 + if (ntp_synced() && xtime.tv_sec > last_rtc_update + 660 && (xtime.tv_nsec / 1000) >= 500000 - ((unsigned)TICK_SIZE) / 2 && (xtime.tv_nsec / 1000) <= 500000 + ((unsigned)TICK_SIZE) / 2) diff --git a/arch/m68k/kernel/time.c b/arch/m68k/kernel/time.c index e47e19588525..4ec95e3cb874 100644 --- a/arch/m68k/kernel/time.c +++ b/arch/m68k/kernel/time.c @@ -166,10 +166,7 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); return 0; diff --git a/arch/m68knommu/kernel/time.c b/arch/m68knommu/kernel/time.c index 5c3ca671627c..b17c1ecba966 100644 --- a/arch/m68knommu/kernel/time.c +++ b/arch/m68knommu/kernel/time.c @@ -68,7 +68,7 @@ static irqreturn_t timer_interrupt(int irq, void *dummy, struct pt_regs * regs) * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be * called as close as possible to 500 ms before the new second starts. */ - if ((time_status & STA_UNSYNC) == 0 && + if (ntp_synced() && xtime.tv_sec > last_rtc_update + 660 && (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { @@ -178,10 +178,7 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); return 0; diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c index f3bf0e43b8bb..b46595462717 100644 --- a/arch/mips/kernel/sysirix.c +++ b/arch/mips/kernel/sysirix.c @@ -632,10 +632,7 @@ asmlinkage int irix_stime(int value) write_seqlock_irq(&xtime_lock); xtime.tv_sec = value; xtime.tv_nsec = 0; - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); return 0; diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 648c82292ed6..0dd0df7a3b04 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -223,10 +223,7 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); @@ -442,7 +439,7 @@ irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) * called as close as possible to 500 ms before the new second starts. */ write_seqlock(&xtime_lock); - if ((time_status & STA_UNSYNC) == 0 && + if (ntp_synced() && xtime.tv_sec > last_rtc_update + 660 && (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 8c1b96fffa76..cddf1cedf007 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -118,7 +118,7 @@ again: * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be * called as close as possible to when a second starts. */ - if ((time_status & STA_UNSYNC) == 0 && + if (ntp_synced() && xtime.tv_sec > last_rtc_update + 660 && (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { diff --git a/arch/parisc/kernel/time.c b/arch/parisc/kernel/time.c index 6cf7407344ba..7ff67f8e9f8c 100644 --- a/arch/parisc/kernel/time.c +++ b/arch/parisc/kernel/time.c @@ -188,10 +188,7 @@ do_settimeofday (struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); } write_sequnlock_irq(&xtime_lock); clock_was_set(); diff --git a/arch/ppc/kernel/time.c b/arch/ppc/kernel/time.c index bf4ddca5e853..a3c5281a5d2d 100644 --- a/arch/ppc/kernel/time.c +++ b/arch/ppc/kernel/time.c @@ -169,7 +169,7 @@ void timer_interrupt(struct pt_regs * regs) * We should have an rtc call that only sets the minutes and * seconds like on Intel to avoid problems with non UTC clocks. */ - if ( ppc_md.set_rtc_time && (time_status & STA_UNSYNC) == 0 && + if ( ppc_md.set_rtc_time && ntp_synced() && xtime.tv_sec - last_rtc_update >= 659 && abs((xtime.tv_nsec / 1000) - (1000000-1000000/HZ)) < 500000/HZ && jiffies - wall_jiffies == 1) { @@ -271,10 +271,7 @@ int do_settimeofday(struct timespec *tv) */ last_rtc_update = new_sec - 658; - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irqrestore(&xtime_lock, flags); clock_was_set(); return 0; diff --git a/arch/ppc64/kernel/time.c b/arch/ppc64/kernel/time.c index 91ef95ccda4f..9939c206afa4 100644 --- a/arch/ppc64/kernel/time.c +++ b/arch/ppc64/kernel/time.c @@ -128,7 +128,7 @@ static __inline__ void timer_check_rtc(void) * We should have an rtc call that only sets the minutes and * seconds like on Intel to avoid problems with non UTC clocks. */ - if ( (time_status & STA_UNSYNC) == 0 && + if (ntp_synced() && xtime.tv_sec - last_rtc_update >= 659 && abs((xtime.tv_nsec/1000) - (1000000-1000000/HZ)) < 500000/HZ && jiffies - wall_jiffies == 1) { @@ -435,10 +435,7 @@ int do_settimeofday(struct timespec *tv) */ last_rtc_update = new_sec - 658; - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); delta_xsec = mulhdu( (tb_last_stamp-do_gtod.varp->tb_orig_stamp), do_gtod.varp->tb_to_xs ); diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c index 8ca485676780..2fd75da15495 100644 --- a/arch/s390/kernel/time.c +++ b/arch/s390/kernel/time.c @@ -139,10 +139,7 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); return 0; diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c index d5f5aedde0a3..02ca69918d7c 100644 --- a/arch/sh/kernel/time.c +++ b/arch/sh/kernel/time.c @@ -215,10 +215,7 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); @@ -252,7 +249,7 @@ static inline void do_timer_interrupt(int irq, struct pt_regs *regs) * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be * called as close as possible to 500 ms before the new second starts. */ - if ((time_status & STA_UNSYNC) == 0 && + if (ntp_synced() && xtime.tv_sec > last_rtc_update + 660 && (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { diff --git a/arch/sh64/kernel/time.c b/arch/sh64/kernel/time.c index 926c6fc0619c..f4a62a10053c 100644 --- a/arch/sh64/kernel/time.c +++ b/arch/sh64/kernel/time.c @@ -247,10 +247,7 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); @@ -328,7 +325,7 @@ static inline void do_timer_interrupt(int irq, struct pt_regs *regs) * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be * called as close as possible to 500 ms before the new second starts. */ - if ((time_status & STA_UNSYNC) == 0 && + if (ntp_synced() && xtime.tv_sec > last_rtc_update + 660 && (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c index 597d3ff6ad68..36a40697b8d6 100644 --- a/arch/sparc/kernel/pcic.c +++ b/arch/sparc/kernel/pcic.c @@ -840,10 +840,7 @@ static int pci_do_settimeofday(struct timespec *tv) xtime.tv_sec = tv->tv_sec; xtime.tv_nsec = tv->tv_nsec; - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); return 0; } diff --git a/arch/sparc/kernel/time.c b/arch/sparc/kernel/time.c index 3b759aefc170..bc015e980341 100644 --- a/arch/sparc/kernel/time.c +++ b/arch/sparc/kernel/time.c @@ -139,7 +139,7 @@ irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs * regs) /* Determine when to update the Mostek clock. */ - if ((time_status & STA_UNSYNC) == 0 && + if (ntp_synced() && xtime.tv_sec > last_rtc_update + 660 && (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { @@ -554,10 +554,7 @@ static int sbus_do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); return 0; } diff --git a/arch/sparc64/kernel/time.c b/arch/sparc64/kernel/time.c index 362b9c26871b..3f08a32f51a1 100644 --- a/arch/sparc64/kernel/time.c +++ b/arch/sparc64/kernel/time.c @@ -449,7 +449,7 @@ static inline void timer_check_rtc(void) static long last_rtc_update; /* Determine when to update the Mostek clock. */ - if ((time_status & STA_UNSYNC) == 0 && + if (ntp_synced() && xtime.tv_sec > last_rtc_update + 660 && (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { diff --git a/arch/v850/kernel/time.c b/arch/v850/kernel/time.c index f722a268238a..ea3fd8844ff0 100644 --- a/arch/v850/kernel/time.c +++ b/arch/v850/kernel/time.c @@ -66,7 +66,7 @@ static irqreturn_t timer_interrupt (int irq, void *dummy, struct pt_regs *regs) * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be * called as close as possible to 500 ms before the new second starts. */ - if ((time_status & STA_UNSYNC) == 0 && + if (ntp_synced() && xtime.tv_sec > last_rtc_update + 660 && (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { @@ -169,10 +169,7 @@ int do_settimeofday(struct timespec *tv) xtime.tv_sec = tv->tv_sec; xtime.tv_nsec = tv->tv_nsec; - time_adjust = 0; /* stop active adjtime () */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq (&xtime_lock); clock_was_set(); diff --git a/arch/x86_64/kernel/time.c b/arch/x86_64/kernel/time.c index 2b5d9da912a2..7b6abe058253 100644 --- a/arch/x86_64/kernel/time.c +++ b/arch/x86_64/kernel/time.c @@ -176,10 +176,7 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); @@ -471,7 +468,7 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) * off) isn't likely to go away much sooner anyway. */ - if ((~time_status & STA_UNSYNC) && xtime.tv_sec > rtc_update && + if (ntp_synced() && xtime.tv_sec > rtc_update && abs(xtime.tv_nsec - 500000000) <= tick_nsec / 2) { set_rtc_mmss(xtime.tv_sec); rtc_update = xtime.tv_sec + 660; diff --git a/arch/xtensa/kernel/time.c b/arch/xtensa/kernel/time.c index e07287db5a40..1ac7d5ce7456 100644 --- a/arch/xtensa/kernel/time.c +++ b/arch/xtensa/kernel/time.c @@ -122,10 +122,7 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); return 0; } @@ -184,7 +181,7 @@ again: next += CCOUNT_PER_JIFFY; do_timer (regs); /* Linux handler in kernel/timer.c */ - if ((time_status & STA_UNSYNC) == 0 && + if (ntp_synced() && xtime.tv_sec - last_rtc_update >= 659 && abs((xtime.tv_nsec/1000)-(1000000-1000000/HZ))<5000000/HZ && jiffies - wall_jiffies == 1) { diff --git a/include/linux/timex.h b/include/linux/timex.h index 74fdd07d3792..7e050a2cc35b 100644 --- a/include/linux/timex.h +++ b/include/linux/timex.h @@ -260,6 +260,29 @@ extern long pps_calcnt; /* calibration intervals */ extern long pps_errcnt; /* calibration errors */ extern long pps_stbcnt; /* stability limit exceeded */ +/** + * ntp_clear - Clears the NTP state variables + * + * Must be called while holding a write on the xtime_lock + */ +static inline void ntp_clear(void) +{ + time_adjust = 0; /* stop active adjtime() */ + time_status |= STA_UNSYNC; + time_maxerror = NTP_PHASE_LIMIT; + time_esterror = NTP_PHASE_LIMIT; +} + +/** + * ntp_synced - Returns 1 if the NTP status is not UNSYNC + * + */ +static inline int ntp_synced(void) +{ + return !(time_status & STA_UNSYNC); +} + + #ifdef CONFIG_TIME_INTERPOLATION #define TIME_SOURCE_CPU 0 -- cgit v1.2.3 From a08b6b7968e7a6afc75e365ac31830867275abdc Mon Sep 17 00:00:00 2001 From: "viro@ZenIV.linux.org.uk" Date: Tue, 6 Sep 2005 01:48:42 +0100 Subject: [PATCH] Kconfig fix (BLK_DEV_FD dependencies) Sanitized and fixed floppy dependencies: split the messy dependencies for BLK_DEV_FD by introducing a new symbol (ARCH_MAY_HAVE_PC_FDC), making BLK_DEV_FD depend on that one and taking declarations of ARCH_MAY_HAVE_PC_FDC to arch/*/Kconfig. While we are at it, fixed several obvious cases when BLK_DEV_FD should have been excluded (architectures lacking asm/floppy.h are *not* going to have floppy.c compile, let alone work). If you can come up with better name for that ("this architecture might have working PC-compatible floppy disk controller"), you are more than welcome - just s/ARCH_MAY_HAVE_PC_FDC/your_prefered_name/g in the patch below... Signed-off-by: Al Viro Signed-off-by: Linus Torvalds --- arch/alpha/Kconfig | 3 +++ arch/arm/Kconfig | 4 ++++ arch/arm/mach-footbridge/Kconfig | 1 + arch/arm26/Kconfig | 4 ++++ arch/i386/Kconfig | 4 ++++ arch/m68k/Kconfig | 5 +++++ arch/mips/Kconfig | 5 +++++ arch/parisc/Kconfig | 4 ++++ arch/ppc/Kconfig | 4 ++++ arch/ppc64/Kconfig | 4 ++++ arch/sh/Kconfig | 4 ++++ arch/sparc/Kconfig | 4 ++++ arch/sparc64/Kconfig | 4 ++++ arch/x86_64/Kconfig | 4 ++++ drivers/block/Kconfig | 2 +- 15 files changed, 55 insertions(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 189d5eababa8..786491f9ceb2 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -479,6 +479,9 @@ config EISA depends on ALPHA_GENERIC || ALPHA_JENSEN || ALPHA_ALCOR || ALPHA_MIKASA || ALPHA_SABLE || ALPHA_LYNX || ALPHA_NORITAKE || ALPHA_RAWHIDE default y +config ARCH_MAY_HAVE_PC_FDC + def_bool y + config SMP bool "Symmetric multi-processing support" depends on ALPHA_SABLE || ALPHA_LYNX || ALPHA_RAWHIDE || ALPHA_DP264 || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_GENERIC || ALPHA_SHARK || ALPHA_MARVEL diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 68dfdba71d74..0f2899b4159d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -64,6 +64,9 @@ config GENERIC_CALIBRATE_DELAY config GENERIC_BUST_SPINLOCK bool +config ARCH_MAY_HAVE_PC_FDC + bool + config GENERIC_ISA_DMA bool @@ -150,6 +153,7 @@ config ARCH_RPC select ARCH_ACORN select FIQ select TIMER_ACORN + select ARCH_MAY_HAVE_PC_FDC help On the Acorn Risc-PC, Linux can support the internal IDE disk and CD-ROM interface, serial and parallel port, and the floppy drive. diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig index 324d9edeec38..bdd257921cfb 100644 --- a/arch/arm/mach-footbridge/Kconfig +++ b/arch/arm/mach-footbridge/Kconfig @@ -87,6 +87,7 @@ config FOOTBRIDGE_ADDIN # EBSA285 board in either host or addin mode config ARCH_EBSA285 + select ARCH_MAY_HAVE_PC_FDC bool endif diff --git a/arch/arm26/Kconfig b/arch/arm26/Kconfig index 1f0373267306..1f00b3d03a07 100644 --- a/arch/arm26/Kconfig +++ b/arch/arm26/Kconfig @@ -55,6 +55,10 @@ config GENERIC_BUST_SPINLOCK config GENERIC_ISA_DMA bool +config ARCH_MAY_HAVE_PC_FDC + bool + default y + source "init/Kconfig" diff --git a/arch/i386/Kconfig b/arch/i386/Kconfig index 4b7de3e1e57b..5d51b38bd70d 100644 --- a/arch/i386/Kconfig +++ b/arch/i386/Kconfig @@ -37,6 +37,10 @@ config GENERIC_IOMAP bool default y +config ARCH_MAY_HAVE_PC_FDC + bool + default y + source "init/Kconfig" menu "Processor type and features" diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 178c4a3fbb72..ba960bbc8e6d 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -25,6 +25,11 @@ config GENERIC_CALIBRATE_DELAY bool default y +config ARCH_MAY_HAVE_PC_FDC + bool + depends on Q40 || (BROKEN && SUN3X) + default y + mainmenu "Linux/68k Kernel Configuration" source "init/Kconfig" diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d79fba0aa8bf..8d76eb1ff291 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -4,6 +4,11 @@ config MIPS # Horrible source of confusion. Die, die, die ... select EMBEDDED +# shouldn't it be per-subarchitecture? +config ARCH_MAY_HAVE_PC_FDC + bool + default y + mainmenu "Linux/MIPS Kernel Configuration" source "init/Kconfig" diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index 1c2d87435233..0b07922a2ac6 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -49,6 +49,10 @@ config ISA_DMA_API bool default y +config ARCH_MAY_HAVE_PC_FDC + bool + default y + source "init/Kconfig" diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig index 36dee0ff5ca0..6ab7e5ea5fcf 100644 --- a/arch/ppc/Kconfig +++ b/arch/ppc/Kconfig @@ -47,6 +47,10 @@ config SCHED_NO_NO_OMIT_FRAME_POINTER bool default y +config ARCH_MAY_HAVE_PC_FDC + bool + default y + source "init/Kconfig" menu "Processor" diff --git a/arch/ppc64/Kconfig b/arch/ppc64/Kconfig index 13b262f10216..deca68ad644a 100644 --- a/arch/ppc64/Kconfig +++ b/arch/ppc64/Kconfig @@ -44,6 +44,10 @@ config SCHED_NO_NO_OMIT_FRAME_POINTER bool default y +config ARCH_MAY_HAVE_PC_FDC + bool + default y + # We optimistically allocate largepages from the VM, so make the limit # large enough (16MB). This badly named config option is actually # max order + 1 diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index adc8109f8b77..3e804c736e64 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -37,6 +37,10 @@ config GENERIC_CALIBRATE_DELAY bool default y +config ARCH_MAY_HAVE_PC_FDC + bool + default y + source "init/Kconfig" menu "System type" diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index aca028aa29bf..aba05394d30a 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -211,6 +211,10 @@ config GENERIC_CALIBRATE_DELAY bool default y +config ARCH_MAY_HAVE_PC_FDC + bool + default y + config SUN_PM bool default y diff --git a/arch/sparc64/Kconfig b/arch/sparc64/Kconfig index 73ec6aec5ed5..1e9d8638a28a 100644 --- a/arch/sparc64/Kconfig +++ b/arch/sparc64/Kconfig @@ -26,6 +26,10 @@ config TIME_INTERPOLATION bool default y +config ARCH_MAY_HAVE_PC_FDC + bool + default y + choice prompt "Kernel page size" default SPARC64_PAGE_SIZE_8KB diff --git a/arch/x86_64/Kconfig b/arch/x86_64/Kconfig index 251ce7cf1a38..8f868b67ef0f 100644 --- a/arch/x86_64/Kconfig +++ b/arch/x86_64/Kconfig @@ -65,6 +65,10 @@ config GENERIC_IOMAP bool default y +config ARCH_MAY_HAVE_PC_FDC + bool + default y + source "init/Kconfig" diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 6b736364cc5b..51b0af1cebee 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -6,7 +6,7 @@ menu "Block devices" config BLK_DEV_FD tristate "Normal floppy disk support" - depends on (!ARCH_S390 && !M68K && !IA64 && !UML && !ARM) || Q40 || (SUN3X && BROKEN) || ARCH_RPC || ARCH_EBSA285 + depends on ARCH_MAY_HAVE_PC_FDC ---help--- If you want to use the floppy disk drive(s) of your PC under Linux, say Y. Information about this driver, especially important for IBM -- cgit v1.2.3