From ed6a0b6e9fd78e167d0488331d1695c6c84192be Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Sun, 19 Mar 2023 11:31:48 -0500 Subject: MIPS: octeon: Use of_address_to_resource() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace of_get_address() and of_translate_address() calls with single call to of_address_to_resource(). Signed-off-by: Rob Herring Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/octeon-irq.c | 35 +++++++++++++++-------------------- 1 file changed, 15 insertions(+), 20 deletions(-) (limited to 'arch/mips/cavium-octeon') diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index fd8043f6ff8a..064e2409377a 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -2290,7 +2290,7 @@ static irqreturn_t octeon_irq_cib_handler(int my_irq, void *data) static int __init octeon_irq_init_cib(struct device_node *ciu_node, struct device_node *parent) { - const __be32 *addr; + struct resource res; u32 val; struct octeon_irq_cib_host_data *host_data; int parent_irq; @@ -2309,21 +2309,19 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node, return -ENOMEM; raw_spin_lock_init(&host_data->lock); - addr = of_get_address(ciu_node, 0, NULL, NULL); - if (!addr) { + r = of_address_to_resource(ciu_node, 0, &res); + if (r) { pr_err("ERROR: Couldn't acquire reg(0) %pOFn\n", ciu_node); - return -EINVAL; + return r; } - host_data->raw_reg = (u64)phys_to_virt( - of_translate_address(ciu_node, addr)); + host_data->raw_reg = (u64)phys_to_virt(res.start); - addr = of_get_address(ciu_node, 1, NULL, NULL); - if (!addr) { + r = of_address_to_resource(ciu_node, 1, &res); + if (r) { pr_err("ERROR: Couldn't acquire reg(1) %pOFn\n", ciu_node); - return -EINVAL; + return r; } - host_data->en_reg = (u64)phys_to_virt( - of_translate_address(ciu_node, addr)); + host_data->en_reg = (u64)phys_to_virt(res.start); r = of_property_read_u32(ciu_node, "cavium,max-bits", &val); if (r) { @@ -2874,11 +2872,11 @@ static struct irq_chip octeon_irq_chip_ciu3_mbox = { static int __init octeon_irq_init_ciu3(struct device_node *ciu_node, struct device_node *parent) { - int i; + int i, ret; int node; struct irq_domain *domain; struct octeon_ciu3_info *ciu3_info; - const __be32 *zero_addr; + struct resource res; u64 base_addr; union cvmx_ciu3_const consts; @@ -2888,14 +2886,11 @@ static int __init octeon_irq_init_ciu3(struct device_node *ciu_node, if (!ciu3_info) return -ENOMEM; - zero_addr = of_get_address(ciu_node, 0, NULL, NULL); - if (WARN_ON(!zero_addr)) - return -EINVAL; - - base_addr = of_translate_address(ciu_node, zero_addr); - base_addr = (u64)phys_to_virt(base_addr); + ret = of_address_to_resource(ciu_node, 0, &res); + if (WARN_ON(ret)) + return ret; - ciu3_info->ciu3_addr = base_addr; + ciu3_info->ciu3_addr = base_addr = phys_to_virt(res.start); ciu3_info->node = node; consts.u64 = cvmx_read_csr(base_addr + CIU3_CONST); -- cgit v1.2.3 From 101f26c72825c5dba1dfe826e4202a9a04b435c6 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 27 Mar 2023 10:35:22 +0200 Subject: MIPS: octeon: Fix compile error Commit ed6a0b6e9fd7 ("MIPS: octeon: Use of_address_to_resource()") lost a cast, which causes a compile error. Fixes: ed6a0b6e9fd7 ("MIPS: octeon: Use of_address_to_resource()") Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/octeon-irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/cavium-octeon') diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 064e2409377a..8425a6b38aa2 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -2890,7 +2890,7 @@ static int __init octeon_irq_init_ciu3(struct device_node *ciu_node, if (WARN_ON(ret)) return ret; - ciu3_info->ciu3_addr = base_addr = phys_to_virt(res.start); + ciu3_info->ciu3_addr = base_addr = (u64)phys_to_virt(res.start); ciu3_info->node = node; consts.u64 = cvmx_read_csr(base_addr + CIU3_CONST); -- cgit v1.2.3 From 78073b8f1ffe4085309808815746403209bfd6bc Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 4 Apr 2023 10:33:49 +0100 Subject: MIPS: Octeon: Disable CVMSEG by default on other platforms QEMU can't emulate CVMSEG on generic platform for now. Just disable it by default. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/mips/cavium-octeon') diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index c1899f109e19..450e979ef5d9 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -14,7 +14,8 @@ config CAVIUM_CN63XXP1 config CAVIUM_OCTEON_CVMSEG_SIZE int "Number of L1 cache lines reserved for CVMSEG memory" range 0 54 - default 1 + default 0 if !CAVIUM_OCTEON_SOC + default 1 if CAVIUM_OCTEON_SOC help CVMSEG LM is a segment that accesses portions of the dcache as a local memory; the larger CVMSEG is, the smaller the cache is. -- cgit v1.2.3