From 9a3634d023012cf54e541f825ed11ff481c6a110 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Jul 2022 18:02:51 +0100 Subject: arm64/sysreg: Convert CTR_EL0 to automatic generation Convert CTR_EL0 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20220704170302.2609529-18-broonie@kernel.org Signed-off-by: Will Deacon --- arch/arm64/tools/sysreg | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm64/tools/sysreg') diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ff5e552f7420..a9f4c157c4be 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -273,6 +273,27 @@ Field 3:1 Level Field 0 InD EndSysreg +Sysreg CTR_EL0 3 3 0 0 1 +Res0 63:38 +Field 37:32 TminLine +Res1 31 +Res0 30 +Field 29 DIC +Field 28 IDC +Field 27:24 CWG +Field 23:20 ERG +Field 19:16 DminLine +Enum 15:14 L1Ip + 0b00 VPIPT + # This is named as AIVIVT in the ARM but documented as reserved + 0b01 RESERVED + 0b10 VIPT + 0b11 PIPT +EndEnum +Res0 13:4 +Field 3:0 IminLine +EndSysreg + Sysreg SVCR 3 3 4 2 2 Res0 63:2 Field 1 ZA -- cgit v1.2.3 From 5589083d802b1f1434f9481f671eee5d985f5772 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Jul 2022 18:02:52 +0100 Subject: arm64/sysreg: Convert DCZID_EL0 to automatic generation Convert DCZID_EL0 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20220704170302.2609529-19-broonie@kernel.org Signed-off-by: Will Deacon --- arch/arm64/include/asm/sysreg.h | 5 ----- arch/arm64/tools/sysreg | 6 ++++++ 2 files changed, 6 insertions(+), 5 deletions(-) (limited to 'arch/arm64/tools/sysreg') diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 234f9a3844de..1a6a04b96dfa 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -461,8 +461,6 @@ #define SMIDR_EL1_SMPS_SHIFT 15 #define SMIDR_EL1_AFFINITY_SHIFT 0 -#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) - #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) @@ -1081,9 +1079,6 @@ #define MVFR2_FPMISC_SHIFT 4 #define MVFR2_SIMDMISC_SHIFT 0 -#define DCZID_EL0_DZP_SHIFT 4 -#define DCZID_EL0_BS_SHIFT 0 - #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a9f4c157c4be..c286b62958ea 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -294,6 +294,12 @@ Res0 13:4 Field 3:0 IminLine EndSysreg +Sysreg DCZID_EL0 3 3 0 0 7 +Res0 63:5 +Field 4 DZP +Field 3:0 BS +EndSysreg + Sysreg SVCR 3 3 4 2 2 Res0 63:2 Field 1 ZA -- cgit v1.2.3 From d1b60bed639bd5ea6c4a80d43816e05c16c0ec6c Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Jul 2022 18:02:53 +0100 Subject: arm64/sysreg: Convert GMID to automatic generation Automatically generate the register definitions for GMID as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20220704170302.2609529-20-broonie@kernel.org Signed-off-by: Will Deacon --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm64/tools/sysreg') diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 1a6a04b96dfa..1b92bea9299a 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -454,7 +454,6 @@ #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) -#define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4) #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) #define SMIDR_EL1_IMPLEMENTER_SHIFT 24 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c286b62958ea..ea3520a347b1 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -257,6 +257,11 @@ Field 5:3 Ctype2 Field 2:0 Ctype1 EndSysreg +Sysreg GMID_EL1 3 1 0 0 4 +Res0 63:4 +Field 3:0 BS +EndSysreg + Sysreg SMIDR_EL1 3 1 0 0 6 Res0 63:32 Field 31:24 IMPLEMENTER -- cgit v1.2.3 From f7b5115cc39cfbe49a1d0b57605c918237e1b8c2 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Jul 2022 18:02:54 +0100 Subject: arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generation Automatically generate defines for ID_AA64ISAR1_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20220704170302.2609529-21-broonie@kernel.org Signed-off-by: Will Deacon --- arch/arm64/include/asm/sysreg.h | 34 ----------------- arch/arm64/tools/sysreg | 83 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+), 34 deletions(-) (limited to 'arch/arm64/tools/sysreg') diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 1b92bea9299a..7f87690e74b3 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -201,7 +201,6 @@ #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) -#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) #define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) @@ -700,39 +699,6 @@ /* Position the attr at the correct index */ #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) -/* id_aa64isar1 */ -#define ID_AA64ISAR1_EL1_I8MM_SHIFT 52 -#define ID_AA64ISAR1_EL1_DGH_SHIFT 48 -#define ID_AA64ISAR1_EL1_BF16_SHIFT 44 -#define ID_AA64ISAR1_EL1_SPECRES_SHIFT 40 -#define ID_AA64ISAR1_EL1_SB_SHIFT 36 -#define ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32 -#define ID_AA64ISAR1_EL1_GPI_SHIFT 28 -#define ID_AA64ISAR1_EL1_GPA_SHIFT 24 -#define ID_AA64ISAR1_EL1_LRCPC_SHIFT 20 -#define ID_AA64ISAR1_EL1_FCMA_SHIFT 16 -#define ID_AA64ISAR1_EL1_JSCVT_SHIFT 12 -#define ID_AA64ISAR1_EL1_API_SHIFT 8 -#define ID_AA64ISAR1_EL1_APA_SHIFT 5 -#define ID_AA64ISAR1_EL1_DPB_SHIFT 0 - -#define ID_AA64ISAR1_EL1_APA_NI 0x0 -#define ID_AA64ISAR1_EL1_APA_PAuth 0x1 -#define ID_AA64ISAR1_EL1_APA_ARCH_EPAC 0x2 -#define ID_AA64ISAR1_EL1_APA_Pauth2 0x3 -#define ID_AA64ISAR1_EL1_APA_FPAC 0x4 -#define ID_AA64ISAR1_EL1_APA_FPACCOMBINE 0x5 -#define ID_AA64ISAR1_EL1_API_NI 0x0 -#define ID_AA64ISAR1_EL1_API_PAuth 0x1 -#define ID_AA64ISAR1_EL1_API_EPAC 0x2 -#define ID_AA64ISAR1_EL1_API_PAuth2 0x3 -#define ID_AA64ISAR1_EL1_API_FPAC 0x4 -#define ID_AA64ISAR1_EL1_API_FPACCOMBINE 0x5 -#define ID_AA64ISAR1_EL1_GPA_NI 0x0 -#define ID_AA64ISAR1_EL1_GPA_IMP 0x1 -#define ID_AA64ISAR1_EL1_GPI_NI 0x0 -#define ID_AA64ISAR1_EL1_GPI_IMP 0x1 - /* id_aa64isar2 */ #define ID_AA64ISAR2_EL1_BC_SHIFT 28 #define ID_AA64ISAR2_EL1_APA3_SHIFT 12 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ea3520a347b1..164221177079 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -114,6 +114,89 @@ EndEnum Res0 3:0 EndSysreg +Sysreg ID_AA64ISAR1_EL1 3 0 0 6 1 +Enum 63:60 LS64 + 0b0000 NI + 0b0001 LS64 + 0b0010 LS64_V + 0b0011 LS64_ACCDATA +EndEnum +Enum 59:56 XS + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 55:52 I8MM + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 51:48 DGH + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 47:44 BF16 + 0b0000 NI + 0b0001 IMP + 0b0010 EBF16 +EndEnum +Enum 43:40 SPECRES + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 39:36 SB + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 35:32 FRINTTS + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 31:28 GPI + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 27:24 GPA + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 23:20 LRCPC + 0b0000 NI + 0b0001 IMP + 0b0010 LRCPC2 +EndEnum +Enum 19:16 FCMA + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 15:12 JSCVT + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 11:8 API + 0b0000 NI + 0b0001 PAuth + 0b0010 EPAC + 0b0011 PAuth2 + 0b0100 FPAC + 0b0101 FPACCOMBINE +EndEnum +Enum 7:4 APA + 0b0000 NI + 0b0001 PAuth + 0b0010 EPAC + 0b0011 PAuth2 + 0b0100 FPAC + 0b0101 FPACCOMBINE +EndEnum +Enum 3:0 DPB + 0b0000 NI + 0b0001 IMP + 0b0010 DPB2 +EndEnum +EndSysreg + 0b0001 IMP +EndEnum +EndSysreg + Sysreg SCTLR_EL1 3 0 1 0 0 Field 63 TIDCP Field 62 SPINMASK -- cgit v1.2.3 From 8fcc8285c0e312a6d5ec6060c67eba87d2881419 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Jul 2022 18:02:55 +0100 Subject: arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation Automatically generate defines for ID_AA64ISAR2_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20220704170302.2609529-22-broonie@kernel.org Signed-off-by: Will Deacon --- arch/arm64/include/asm/sysreg.h | 27 --------------------------- arch/arm64/tools/sysreg | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 27 deletions(-) (limited to 'arch/arm64/tools/sysreg') diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 7f87690e74b3..cd6820f6e819 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -201,8 +201,6 @@ #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) -#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) - #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) @@ -699,31 +697,6 @@ /* Position the attr at the correct index */ #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) -/* id_aa64isar2 */ -#define ID_AA64ISAR2_EL1_BC_SHIFT 28 -#define ID_AA64ISAR2_EL1_APA3_SHIFT 12 -#define ID_AA64ISAR2_EL1_GPA3_SHIFT 8 -#define ID_AA64ISAR2_EL1_RPRES_SHIFT 4 -#define ID_AA64ISAR2_EL1_WFxT_SHIFT 0 - -/* - * Value 0x1 has been removed from the architecture, and is - * reserved, but has not yet been removed from the ARM ARM - * as of ARM DDI 0487G.b. - */ -#define ID_AA64ISAR2_EL1_WFxT_NI 0x0 -#define ID_AA64ISAR2_EL1_WFxT_IMP 0x2 - -#define ID_AA64ISAR2_EL1_APA3_NI 0x0 -#define ID_AA64ISAR2_EL1_APA3_PAuth 0x1 -#define ID_AA64ISAR2_EL1_APA3_EPAC 0x2 -#define ID_AA64ISAR2_EL1_APA3_PAuth2 0x3 -#define ID_AA64ISAR2_EL1_APA3_FPAC 0x4 -#define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE 0x5 - -#define ID_AA64ISAR2_EL1_GPA3_NI 0x0 -#define ID_AA64ISAR2_EL1_GPA3_IMP 0x1 - /* id_aa64pfr0 */ #define ID_AA64PFR0_CSV3_SHIFT 60 #define ID_AA64PFR0_CSV2_SHIFT 56 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 164221177079..da5e925bf624 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -193,8 +193,41 @@ Enum 3:0 DPB 0b0010 DPB2 EndEnum EndSysreg + +Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2 +Res0 63:28 +Enum 27:24 PAC_frac + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 23:20 BC + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 19:16 MOPS + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 15:12 APA3 + 0b0000 NI + 0b0001 PAuth + 0b0010 EPAC + 0b0011 PAuth2 + 0b0100 FPAC + 0b0101 FPACCOMBINE +EndEnum +Enum 11:8 GPA3 + 0b0000 NI 0b0001 IMP EndEnum +Enum 7:4 RPRES + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 3:0 WFxT + 0b0000 NI + 0b0010 IMP +EndEnum EndSysreg Sysreg SCTLR_EL1 3 0 1 0 0 -- cgit v1.2.3 From 464ca8df6248eced7bce5309c344f62b08a1d5c0 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Jul 2022 18:02:56 +0100 Subject: arm64/sysreg: Convert LORSA_EL1 to automatic generation Convert LORSA_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20220704170302.2609529-23-broonie@kernel.org Signed-off-by: Will Deacon --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 8 ++++++++ 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm64/tools/sysreg') diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index cd6820f6e819..48a48974515b 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -407,7 +407,6 @@ #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) -#define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index da5e925bf624..c1e3a9ceb049 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -515,3 +515,11 @@ EndSysreg Sysreg TTBR1_EL1 3 0 2 0 1 Fields TTBRx_EL1 EndSysreg + +Sysreg LORSA_EL1 3 0 10 4 0 +Res0 63:52 +Field 51:16 SA +Res0 15:1 +Field 0 Valid +EndSysreg + -- cgit v1.2.3 From 0d879f7a32a8e8ac8990ec6c771da0f12d40bb2b Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Jul 2022 18:02:57 +0100 Subject: arm64/sysreg: Convert LOREA_EL1 to automatic generation Convert LOREA_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20220704170302.2609529-24-broonie@kernel.org Signed-off-by: Will Deacon --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 6 ++++++ 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm64/tools/sysreg') diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 48a48974515b..56989d982c81 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -407,7 +407,6 @@ #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) -#define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c1e3a9ceb049..4c23c65e53d1 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -523,3 +523,9 @@ Res0 15:1 Field 0 Valid EndSysreg +Sysreg LOREA_EL1 3 0 10 4 1 +Res0 63:52 +Field 51:48 EA_51_48 +Field 47:16 EA_47_16 +Res0 15:0 +EndSysreg -- cgit v1.2.3 From cdf428f79b3c1a9a86c581e7141a979249cbd966 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Jul 2022 18:02:58 +0100 Subject: arm64/sysreg: Convert LORN_EL1 to automatic generation Convert LORN_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20220704170302.2609529-25-broonie@kernel.org Signed-off-by: Will Deacon --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm64/tools/sysreg') diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 56989d982c81..78e61eb25eff 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -407,7 +407,6 @@ #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) -#define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 4c23c65e53d1..ec84a76fe66e 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -529,3 +529,8 @@ Field 51:48 EA_51_48 Field 47:16 EA_47_16 Res0 15:0 EndSysreg + +Sysreg LORN_EL1 3 0 10 4 2 +Res0 63:8 +Field 7:0 Num +EndSysreg -- cgit v1.2.3 From 41cc24e0c883bb610da5841e6df6672712346c48 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Jul 2022 18:02:59 +0100 Subject: arm64/sysreg: Convert LORC_EL1 to automatic generation Convert LORC_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20220704170302.2609529-26-broonie@kernel.org Signed-off-by: Will Deacon --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 7 +++++++ 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'arch/arm64/tools/sysreg') diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 78e61eb25eff..261b42b88e9f 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -407,7 +407,6 @@ #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) -#define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ec84a76fe66e..95fcad79b917 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -534,3 +534,10 @@ Sysreg LORN_EL1 3 0 10 4 2 Res0 63:8 Field 7:0 Num EndSysreg + +Sysreg LORC_EL1 3 0 10 4 3 +Res0 63:10 +Field 9:2 DS +Res0 1 +Field 0 EN +EndSysreg -- cgit v1.2.3 From 12c897b4ffecce971e6654e952a0f6453976b3bc Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Jul 2022 18:03:00 +0100 Subject: arm64/sysreg: Convert LORID_EL1 to automatic generation Convert LORID_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20220704170302.2609529-27-broonie@kernel.org Signed-off-by: Will Deacon --- arch/arm64/include/asm/sysreg.h | 2 -- arch/arm64/tools/sysreg | 7 +++++++ 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'arch/arm64/tools/sysreg') diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 261b42b88e9f..ee7ecba7f498 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -407,8 +407,6 @@ #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) -#define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) - #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 95fcad79b917..13b8f85682af 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -541,3 +541,10 @@ Field 9:2 DS Res0 1 Field 0 EN EndSysreg + +Sysreg LORID_EL1 3 0 10 4 7 +Res0 63:24 +Field 23:16 LD +Res0 15:8 +Field 7:0 LR +EndSysreg -- cgit v1.2.3 From 2bc589bd645fd085bb7f621a6e2a723a40fd8948 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Jul 2022 18:03:01 +0100 Subject: arm64/sysreg: Convert ID_AA64SMFR0_EL1 to automatic generation Convert ID_AA64SMFR0_EL1 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20220704170302.2609529-28-broonie@kernel.org Signed-off-by: Will Deacon --- arch/arm64/include/asm/sysreg.h | 18 ------------------ arch/arm64/tools/sysreg | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 18 deletions(-) (limited to 'arch/arm64/tools/sysreg') diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index ee7ecba7f498..2e2b5811e081 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -193,7 +193,6 @@ #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) -#define SYS_ID_AA64SMFR0_EL1 sys_reg(3, 0, 0, 4, 5) #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) @@ -760,23 +759,6 @@ #define ID_AA64ZFR0_EL1_AES_PMULL128 0x2 #define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1 -/* id_aa64smfr0 */ -#define ID_AA64SMFR0_EL1_FA64_SHIFT 63 -#define ID_AA64SMFR0_EL1_I16I64_SHIFT 52 -#define ID_AA64SMFR0_EL1_F64F64_SHIFT 48 -#define ID_AA64SMFR0_EL1_I8I32_SHIFT 36 -#define ID_AA64SMFR0_EL1_F16F32_SHIFT 35 -#define ID_AA64SMFR0_EL1_B16F32_SHIFT 34 -#define ID_AA64SMFR0_EL1_F32F32_SHIFT 32 - -#define ID_AA64SMFR0_EL1_FA64_IMP 0x1 -#define ID_AA64SMFR0_EL1_I16I64_IMP 0xf -#define ID_AA64SMFR0_EL1_F64F64_IMP 0x1 -#define ID_AA64SMFR0_EL1_I8I32_IMP 0xf -#define ID_AA64SMFR0_EL1_F16F32_IMP 0x1 -#define ID_AA64SMFR0_EL1_B16F32_IMP 0x1 -#define ID_AA64SMFR0_EL1_F32F32_IMP 0x1 - /* id_aa64mmfr0 */ #define ID_AA64MMFR0_ECV_SHIFT 60 #define ID_AA64MMFR0_FGT_SHIFT 56 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 13b8f85682af..b5c4251c6796 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -46,6 +46,43 @@ # feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration # item ACCDATA) though it may be more taseful to do something else. +Sysreg ID_AA64SMFR0_EL1 3 0 0 4 5 +Enum 63 FA64 + 0b0 NI + 0b1 IMP +EndEnum +Res0 62:60 +Field 59:56 SMEver +Enum 55:52 I16I64 + 0b0000 NI + 0b1111 IMP +EndEnum +Res0 51:49 +Enum 48 F64F64 + 0b0 NI + 0b1 IMP +EndEnum +Res0 47:40 +Enum 39:36 I8I32 + 0b0000 NI + 0b1111 IMP +EndEnum +Enum 35 F16F32 + 0b0 NI + 0b1 IMP +EndEnum +Enum 34 B16F32 + 0b0 NI + 0b1 IMP +EndEnum +Res0 33 +Enum 32 F32F32 + 0b0 NI + 0b1 IMP +EndEnum +Res0 31:0 +EndSysreg + Sysreg ID_AA64ISAR0_EL1 3 0 0 6 0 Enum 63:60 RNDR 0b0000 NI -- cgit v1.2.3 From 3bbeca99309fd795f8697648e59fec8b70209f6e Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Jul 2022 18:03:02 +0100 Subject: arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generation Convert ID_AA64ZFR0_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20220704170302.2609529-29-broonie@kernel.org Signed-off-by: Will Deacon --- arch/arm64/include/asm/sysreg.h | 23 --------------------- arch/arm64/tools/sysreg | 46 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+), 23 deletions(-) (limited to 'arch/arm64/tools/sysreg') diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 2e2b5811e081..d7f115368197 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -192,7 +192,6 @@ #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) -#define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) @@ -737,28 +736,6 @@ #define ID_AA64PFR1_MTE 0x2 #define ID_AA64PFR1_MTE_ASYMM 0x3 -/* id_aa64zfr0 */ -#define ID_AA64ZFR0_EL1_F64MM_SHIFT 56 -#define ID_AA64ZFR0_EL1_F32MM_SHIFT 52 -#define ID_AA64ZFR0_EL1_I8MM_SHIFT 44 -#define ID_AA64ZFR0_EL1_SM4_SHIFT 40 -#define ID_AA64ZFR0_EL1_SHA3_SHIFT 32 -#define ID_AA64ZFR0_EL1_BF16_SHIFT 20 -#define ID_AA64ZFR0_EL1_BitPerm_SHIFT 16 -#define ID_AA64ZFR0_EL1_AES_SHIFT 4 -#define ID_AA64ZFR0_EL1_SVEver_SHIFT 0 - -#define ID_AA64ZFR0_EL1_F64MM_IMP 0x1 -#define ID_AA64ZFR0_EL1_F32MM_IMP 0x1 -#define ID_AA64ZFR0_EL1_I8MM_IMP 0x1 -#define ID_AA64ZFR0_EL1_BF16_IMP 0x1 -#define ID_AA64ZFR0_EL1_SM4_IMP 0x1 -#define ID_AA64ZFR0_EL1_SHA3_IMP 0x1 -#define ID_AA64ZFR0_EL1_BitPerm_IMP 0x1 -#define ID_AA64ZFR0_EL1_AES_IMP 0x1 -#define ID_AA64ZFR0_EL1_AES_PMULL128 0x2 -#define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1 - /* id_aa64mmfr0 */ #define ID_AA64MMFR0_ECV_SHIFT 60 #define ID_AA64MMFR0_FGT_SHIFT 56 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b5c4251c6796..9ae483ec1e56 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -46,6 +46,52 @@ # feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration # item ACCDATA) though it may be more taseful to do something else. +Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4 +Res0 63:60 +Enum 59:56 F64MM + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 55:52 F32MM + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 51:48 +Enum 47:44 I8MM + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 43:40 SM4 + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 39:36 +Enum 35:32 SHA3 + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 31:24 +Enum 23:20 BF16 + 0b0000 NI + 0b0001 IMP + 0b0010 EBF16 +EndEnum +Enum 19:16 BitPerm + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 15:8 +Enum 7:4 AES + 0b0000 NI + 0b0001 IMP + 0b0010 PMULL128 +EndEnum +Enum 3:0 SVEver + 0b0000 IMP + 0b0001 SVE2 +EndEnum +EndSysreg + Sysreg ID_AA64SMFR0_EL1 3 0 0 4 5 Enum 63 FA64 0b0 NI -- cgit v1.2.3