From 972c542746904b5f418284946728a61b783275ef Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 8 Dec 2009 18:46:28 -0700 Subject: ARM: OMAP4: PM: OMAP4 clock tree and clkdev registration This patch defines all the clock nodes in OMAP4430 platform. All the clock node structs and the clkdev table is autogenerated using a python script (gen_clock_tree.py) developed by Paul Walmsley, Benoit Cousson and Rajendra Nayak. Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley Cc: Benoit Cousson --- arch/arm/mach-omap2/clock44xx.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 arch/arm/mach-omap2/clock44xx.h (limited to 'arch/arm/mach-omap2/clock44xx.h') diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h new file mode 100644 index 000000000000..c1bc4b6eb6b3 --- /dev/null +++ b/arch/arm/mach-omap2/clock44xx.h @@ -0,0 +1,23 @@ +/* + * OMAP4 clock function prototypes and macros + * + * Copyright (C) 2009 Texas Instruments, Inc. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H + +unsigned long omap3_dpll_recalc(struct clk *clk); +unsigned long omap3_clkoutx2_recalc(struct clk *clk); +int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); + +/* DPLL modes */ +#define DPLL_LOW_POWER_STOP 0x1 +#define DPLL_LOW_POWER_BYPASS 0x5 +#define DPLL_LOCKED 0x7 +#define OMAP4430_MAX_DPLL_MULT 2048 +#define OMAP4430_MAX_DPLL_DIV 128 + +extern const struct clkops clkops_noncore_dpll_ops; + +#endif -- cgit v1.2.3