From 63d2dfdbf4b12a6993adf5005fd308d611d453d6 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Thu, 5 Sep 2013 13:17:49 +0530 Subject: ARC: cacheflush refactor #2: I and D caches lines to have same size Having them be different seems an obscure configuration. Signed-off-by: Vineet Gupta --- arch/arc/include/asm/cache.h | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'arch/arc/include') diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index e4abdaac6f9f..2fd3162ec4df 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -17,13 +17,7 @@ #endif #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) - -/* For a rare case where customers have differently config I/D */ -#define ARC_ICACHE_LINE_LEN L1_CACHE_BYTES -#define ARC_DCACHE_LINE_LEN L1_CACHE_BYTES - -#define ICACHE_LINE_MASK (~(ARC_ICACHE_LINE_LEN - 1)) -#define DCACHE_LINE_MASK (~(ARC_DCACHE_LINE_LEN - 1)) +#define CACHE_LINE_MASK (~(L1_CACHE_BYTES - 1)) /* * ARC700 doesn't cache any access in top 256M. -- cgit v1.2.3