From b94f9008f2ad551f4d6a9537b10238847cb81e5d Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 24 Oct 2019 13:14:12 -0700 Subject: dt-bindings: Document brcm, irq-can-wake for brcm, bcm7038-l1-intc.txt The BCM7038 L1 interrupt controller can be used as a wake-up interrupt controller on MIPS and ARM-based systems, document the brcm,irq-can-wake which has been "standardized" across Broadcom interrupt controllers. Signed-off-by: Florian Fainelli Signed-off-by: Marc Zyngier Acked-by: Rob Herring Link: https://lore.kernel.org/r/20191024201415.23454-3-f.fainelli@gmail.com --- .../bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt index 2117d4ac1ae5..4eb043270f5b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt @@ -31,6 +31,11 @@ Required properties: - interrupts: specifies the interrupt line(s) in the interrupt-parent controller node; valid values depend on the type of parent interrupt controller +Optional properties: + +- brcm,irq-can-wake: If present, this means the L1 controller can be used as a + wakeup source for system suspend/resume. + If multiple reg ranges and interrupt-parent entries are present on an SMP system, the driver will allow IRQ SMP affinity to be set up through the /proc/irq/ interface. In the simplest possible configuration, only one -- cgit v1.2.3 From e14b5e5ff0841270e6262e3e5fd69ad764a80aee Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 24 Oct 2019 13:14:14 -0700 Subject: dt-bindings: Document brcm, int-fwd-mask property for bcm7038-l1-intc Indicate that the brcm,int-fwd-mask property is optional and can be set on platforms which require to leave specific interrupts unmanaged by Linux and need to retain the firmware configuration. Signed-off-by: Florian Fainelli Signed-off-by: Marc Zyngier Acked-by: Rob Herring Link: https://lore.kernel.org/r/20191024201415.23454-5-f.fainelli@gmail.com --- .../bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt index 4eb043270f5b..5ddef1dc0c1a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt @@ -36,6 +36,12 @@ Optional properties: - brcm,irq-can-wake: If present, this means the L1 controller can be used as a wakeup source for system suspend/resume. +Optional properties: + +- brcm,int-fwd-mask: if present, a bit mask to indicate which interrupts + have already been configured by the firmware and should be left unmanaged. + This should have one 32-bit word per status/set/clear/mask group. + If multiple reg ranges and interrupt-parent entries are present on an SMP system, the driver will allow IRQ SMP affinity to be set up through the /proc/irq/ interface. In the simplest possible configuration, only one -- cgit v1.2.3 From 87cd38dfd9e67ffa7c3d3d1a54a2482ed23f1307 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Thu, 7 Nov 2019 13:21:14 +0100 Subject: dt/bindings: Add bindings for Layerscape external irqs This adds Device Tree binding documentation for the external interrupt lines with configurable polarity present on some Layerscape SOCs. Signed-off-by: Rasmus Villemoes Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20191107122115.6244-2-linux@rasmusvillemoes.dk --- .../interrupt-controller/fsl,ls-extirq.txt | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt new file mode 100644 index 000000000000..f0ad7801e8cf --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt @@ -0,0 +1,49 @@ +* Freescale Layerscape external IRQs + +Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting +the polarity of certain external interrupt lines. + +The device node must be a child of the node representing the +Supplemental Configuration Unit (SCFG). + +Required properties: +- compatible: should be "fsl,-extirq", e.g. "fsl,ls1021a-extirq". +- #interrupt-cells: Must be 2. The first element is the index of the + external interrupt line. The second element is the trigger type. +- #address-cells: Must be 0. +- interrupt-controller: Identifies the node as an interrupt controller +- reg: Specifies the Interrupt Polarity Control Register (INTPCR) in + the SCFG. +- interrupt-map: Specifies the mapping from external interrupts to GIC + interrupts. +- interrupt-map-mask: Must be <0xffffffff 0>. + +Example: + scfg: scfg@1570000 { + compatible = "fsl,ls1021a-scfg", "syscon"; + reg = <0x0 0x1570000 0x0 0x10000>; + big-endian; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1570000 0x10000>; + + extirq: interrupt-controller@1ac { + compatible = "fsl,ls1021a-extirq"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1ac 4>; + interrupt-map = + <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0xffffffff 0x0>; + }; + }; + + + interrupts-extended = <&gic GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <&extirq 1 IRQ_TYPE_LEVEL_LOW>; -- cgit v1.2.3 From bf93b04cd85d74c34335e76882cf8bf206caab6e Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 8 Nov 2019 14:58:18 +0530 Subject: dt-bindings: qcom,pdc: Add compatible for sc7180 Add the compatible string for sc7180 SoC from Qualcomm. Signed-off-by: Rajendra Nayak Signed-off-by: Marc Zyngier Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20191108092824.9773-8-rnayak@codeaurora.org --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt index 8e0797cb1487..1df293953327 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt @@ -17,7 +17,8 @@ Properties: - compatible: Usage: required Value type: - Definition: Should contain "qcom,-pdc" + Definition: Should contain "qcom,-pdc" and "qcom,pdc" + - "qcom,sc7180-pdc": For SC7180 - "qcom,sdm845-pdc": For SDM845 - reg: -- cgit v1.2.3 From 09d31567f85b6cd0eddf28d90f7b83be09ee282b Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Fri, 15 Nov 2019 15:11:48 -0700 Subject: of/irq: Document properties for wakeup interrupt parent Some interrupt controllers in a SoC, are always powered on and have a select interrupts routed to them, so that they can wakeup the SoC from suspend. Add wakeup-parent DT property to refer to these interrupt controllers. Signed-off-by: Lina Iyer Signed-off-by: Marc Zyngier Reviewed-by: Rob Herring Reviewed-by: Linus Walleij Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/1573855915-9841-6-git-send-email-ilina@codeaurora.org --- .../devicetree/bindings/interrupt-controller/interrupts.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt index 4a3ee253f7f0..4ebfa0008781 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt @@ -108,3 +108,15 @@ commonly used: sensitivity = <7>; }; }; + +3) Interrupt wakeup parent +-------------------------- + +Some interrupt controllers in a SoC, are always powered on and have a select +interrupts routed to them, so that they can wakeup the SoC from suspend. These +interrupt controllers do not fall into the category of a parent interrupt +controller and can be specified by the "wakeup-parent" property and contain a +single phandle referring to the wakeup capable interrupt controller. + + Example: + wakeup-parent = <&pdc_intc>; -- cgit v1.2.3