From 1caf002efa223f930ba508159535cf82ad4b2811 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Tue, 20 Dec 2022 09:12:44 +0800 Subject: dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC This cache controller is also used on the StarFive JH7110 SoC. Signed-off-by: Emil Renner Berthing Signed-off-by: Hal Feng Acked-by: Rob Herring Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml index bf3f07421f7e..31d20efaa6d3 100644 --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -38,6 +38,10 @@ properties: - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache - const: cache + - items: + - const: starfive,jh7110-ccache + - const: sifive,ccache0 + - const: cache - items: - const: microchip,mpfs-ccache - const: sifive,fu540-c000-ccache @@ -85,6 +89,7 @@ allOf: contains: enum: - sifive,fu740-c000-ccache + - starfive,jh7110-ccache - microchip,mpfs-ccache then: @@ -105,7 +110,9 @@ allOf: properties: compatible: contains: - const: sifive,fu740-c000-ccache + enum: + - sifive,fu740-c000-ccache + - starfive,jh7110-ccache then: properties: -- cgit v1.2.3 From 922ef52cea18567bd6a7e083c6acd776b5676bb6 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 17 Nov 2022 14:29:55 +0100 Subject: dt-bindings: soc: qcom: Add bindings for Qualcomm Ramp Controller Document the Qualcomm Ramp Controller, found on various legacy Qualcomm SoCs. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221117132956.169432-2-angelogioacchino.delregno@collabora.com --- .../soc/qcom/qcom,msm8976-ramp-controller.yaml | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,msm8976-ramp-controller.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,msm8976-ramp-controller.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,msm8976-ramp-controller.yaml new file mode 100644 index 000000000000..aae9cf7b8caf --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,msm8976-ramp-controller.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,msm8976-ramp-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Ramp Controller + +maintainers: + - AngeloGioacchino Del Regno + +description: + The Ramp Controller is used to program the sequence ID for pulse + swallowing, enable sequences and link Sequence IDs (SIDs) for the + CPU cores on some Qualcomm SoCs. + +properties: + compatible: + enum: + - qcom,msm8976-ramp-controller + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + cpu-power-controller@b014000 { + compatible = "qcom,msm8976-ramp-controller"; + reg = <0x0b014000 0x68>; + }; -- cgit v1.2.3 From 6b42133d2189d9b3770153e84111ede1e1948e0f Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 17 Nov 2022 18:04:59 +0100 Subject: dt-bindings: soc: qcom: convert non-smd RPM bindings to dt-schema Convert the non-SMD RPM node bindings to dt-schema, the old txt bindings are now removed since all bindings were converted. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring Acked-by: Lee Jones Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221005-mdm9615-pinctrl-yaml-v5-2-910019fb8b9b@linaro.org --- Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 283 --------------------- .../devicetree/bindings/soc/qcom/qcom,rpm.yaml | 101 ++++++++ 2 files changed, 101 insertions(+), 283 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mfd/qcom-rpm.txt create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt deleted file mode 100644 index b823b8625243..000000000000 --- a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt +++ /dev/null @@ -1,283 +0,0 @@ -Qualcomm Resource Power Manager (RPM) - -This driver is used to interface with the Resource Power Manager (RPM) found in -various Qualcomm platforms. The RPM allows each component in the system to vote -for state of the system resources, such as clocks, regulators and bus -frequencies. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,rpm-apq8064" - "qcom,rpm-msm8660" - "qcom,rpm-msm8960" - "qcom,rpm-ipq8064" - "qcom,rpm-mdm9615" - -- reg: - Usage: required - Value type: - Definition: base address and size of the RPM's message ram - -- interrupts: - Usage: required - Value type: - Definition: three entries specifying the RPM's: - 1. acknowledgement interrupt - 2. error interrupt - 3. wakeup interrupt - -- interrupt-names: - Usage: required - Value type: - Definition: must be the three strings "ack", "err" and "wakeup", in order - -- qcom,ipc: - Usage: required - Value type: - - Definition: three entries specifying the outgoing ipc bit used for - signaling the RPM: - - phandle to a syscon node representing the apcs registers - - u32 representing offset to the register within the syscon - - u32 representing the ipc bit within the register - - -= SUBNODES - -The RPM exposes resources to its subnodes. The below bindings specify the set -of valid subnodes that can operate on these resources. - -== Regulators - -Regulator nodes are identified by their compatible: - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,rpm-pm8058-regulators" - "qcom,rpm-pm8901-regulators" - "qcom,rpm-pm8921-regulators" - "qcom,rpm-pm8018-regulators" - "qcom,rpm-smb208-regulators" - -- vdd_l0_l1_lvs-supply: -- vdd_l2_l11_l12-supply: -- vdd_l3_l4_l5-supply: -- vdd_l6_l7-supply: -- vdd_l8-supply: -- vdd_l9-supply: -- vdd_l10-supply: -- vdd_l13_l16-supply: -- vdd_l14_l15-supply: -- vdd_l17_l18-supply: -- vdd_l19_l20-supply: -- vdd_l21-supply: -- vdd_l22-supply: -- vdd_l23_l24_l25-supply: -- vdd_ncp-supply: -- vdd_s0-supply: -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: - Usage: optional (pm8058 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- lvs0_in-supply: -- lvs1_in-supply: -- lvs2_in-supply: -- lvs3_in-supply: -- mvs_in-supply: -- vdd_l0-supply: -- vdd_l1-supply: -- vdd_l2-supply: -- vdd_l3-supply: -- vdd_l4-supply: -- vdd_l5-supply: -- vdd_l6-supply: -- vdd_s0-supply: -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: - Usage: optional (pm8901 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- vdd_l1_l2_l12_l18-supply: -- vdd_l3_l15_l17-supply: -- vdd_l4_l14-supply: -- vdd_l5_l8_l16-supply: -- vdd_l6_l7-supply: -- vdd_l9_l11-supply: -- vdd_l10_l22-supply: -- vdd_l21_l23_l29-supply: -- vdd_l24-supply: -- vdd_l25-supply: -- vdd_l26-supply: -- vdd_l27-supply: -- vdd_l28-supply: -- vdd_ncp-supply: -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s4-supply: -- vdd_s5-supply: -- vdd_s6-supply: -- vdd_s7-supply: -- vdd_s8-supply: -- vin_5vs-supply: -- vin_lvs1_3_6-supply: -- vin_lvs2-supply: -- vin_lvs4_5_7-supply: - Usage: optional (pm8921 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- vin_lvs1-supply: -- vdd_l7-supply: -- vdd_l8-supply: -- vdd_l9_l10_l11_l12-supply: - Usage: optional (pm8018 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -The regulator node houses sub-nodes for each regulator within the device. Each -sub-node is identified using the node's name, with valid values listed for each -of the pmics below. - -pm8058: - l0, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, - l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, s0, s1, s2, s3, s4, - lvs0, lvs1, ncp - -pm8901: - l0, l1, l2, l3, l4, l5, l6, s0, s1, s2, s3, s4, lvs0, lvs1, lvs2, lvs3, - mvs - -pm8921: - s1, s2, s3, s4, s7, s8, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, - l12, l14, l15, l16, l17, l18, l21, l22, l23, l24, l25, l26, l27, l28, - l29, lvs1, lvs2, lvs3, lvs4, lvs5, lvs6, lvs7, usb-switch, hdmi-switch, - ncp - -pm8018: - s1, s2, s3, s4, s5, , l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, - l12, l14, lvs1 - -smb208: - s1a, s1b, s2a, s2b - -The content of each sub-node is defined by the standard binding for regulators - -see regulator.txt - with additional custom properties described below: - -=== Switch-mode Power Supply regulator custom properties - -- bias-pull-down: - Usage: optional - Value type: - Definition: enable pull down of the regulator when inactive - -- qcom,switch-mode-frequency: - Usage: required - Value type: - Definition: Frequency (Hz) of the switch-mode power supply; - must be one of: - 19200000, 9600000, 6400000, 4800000, 3840000, 3200000, - 2740000, 2400000, 2130000, 1920000, 1750000, 1600000, - 1480000, 1370000, 1280000, 1200000 - -- qcom,force-mode: - Usage: optional (default if no other qcom,force-mode is specified) - Value type: - Definition: indicates that the regulator should be forced to a - particular mode, valid values are: - QCOM_RPM_FORCE_MODE_NONE - do not force any mode - QCOM_RPM_FORCE_MODE_LPM - force into low power mode - QCOM_RPM_FORCE_MODE_HPM - force into high power mode - QCOM_RPM_FORCE_MODE_AUTO - allow regulator to automatically - select its own mode based on - realtime current draw, only for: - pm8921 smps and ftsmps - -- qcom,power-mode-hysteretic: - Usage: optional - Value type: - Definition: select that the power supply should operate in hysteretic - mode, instead of the default pwm mode - -=== Low-dropout regulator custom properties - -- bias-pull-down: - Usage: optional - Value type: - Definition: enable pull down of the regulator when inactive - -- qcom,force-mode: - Usage: optional - Value type: - Definition: indicates that the regulator should not be forced to any - particular mode, valid values are: - QCOM_RPM_FORCE_MODE_NONE - do not force any mode - QCOM_RPM_FORCE_MODE_LPM - force into low power mode - QCOM_RPM_FORCE_MODE_HPM - force into high power mode - QCOM_RPM_FORCE_MODE_BYPASS - set regulator to use bypass - mode, i.e. to act as a switch - and not regulate, only for: - pm8921 pldo, nldo and nldo1200 - -=== Negative Charge Pump custom properties - -- qcom,switch-mode-frequency: - Usage: required - Value type: - Definition: Frequency (Hz) of the switch mode power supply; - must be one of: - 19200000, 9600000, 6400000, 4800000, 3840000, 3200000, - 2740000, 2400000, 2130000, 1920000, 1750000, 1600000, - 1480000, 1370000, 1280000, 1200000 - -= EXAMPLE - - #include - - rpm@108000 { - compatible = "qcom,rpm-msm8960"; - reg = <0x108000 0x1000>; - qcom,ipc = <&apcs 0x8 2>; - - interrupts = <0 19 0>, <0 21 0>, <0 22 0>; - interrupt-names = "ack", "err", "wakeup"; - - regulators { - compatible = "qcom,rpm-pm8921-regulators"; - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - - s1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - bias-pull-down; - - qcom,switch-mode-frequency = <3200000>; - }; - - pm8921_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - - qcom,force-mode = ; - }; - }; - }; - diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml new file mode 100644 index 000000000000..b00be9e01206 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,rpm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Resource Power Manager (RPM) + +description: + This driver is used to interface with the Resource Power Manager (RPM) found + in various Qualcomm platforms. The RPM allows each component in the system + to vote for state of the system resources, such as clocks, regulators and bus + frequencies. + +maintainers: + - Bjorn Andersson + +properties: + compatible: + enum: + - qcom,rpm-apq8064 + - qcom,rpm-msm8660 + - qcom,rpm-msm8960 + - qcom,rpm-ipq8064 + - qcom,rpm-mdm9615 + + reg: + maxItems: 1 + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: ack + - const: err + - const: wakeup + + qcom,ipc: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to a syscon node representing the APCS registers + - description: u32 representing offset to the register within the syscon + - description: u32 representing the ipc bit within the register + description: + Three entries specifying the outgoing ipc bit used for signaling the RPM. + +patternProperties: + "^regulators(-[01])?$": + type: object + $ref: /schemas/regulator/qcom,rpm-regulator.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-names + - qcom,ipc + +additionalProperties: false + +examples: + - | + #include + #include + #include + + rpm@108000 { + compatible = "qcom,rpm-msm8960"; + reg = <0x108000 0x1000>; + qcom,ipc = <&apcs 0x8 2>; + + interrupts = , , ; + interrupt-names = "ack", "err", "wakeup"; + + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + + s1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + + bias-pull-down; + + qcom,switch-mode-frequency = <3200000>; + }; + + pm8921_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + + qcom,force-mode = ; + }; + }; + }; -- cgit v1.2.3 From 417091dc60ba0a991c0e6aa77c1eeb2cfcf0a3d4 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Tue, 27 Dec 2022 20:52:45 +0530 Subject: dt-bindings: soc: qcom,dcc: Add the dtschema Add the device tree bindings for Data Capture and Compare(DCC). Signed-off-by: Souradeep Chowdhury Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/eb758cbdc7bd0973b3ca154b11fb8db54cde805f.1672148732.git.quic_schowdhu@quicinc.com --- .../devicetree/bindings/soc/qcom/qcom,dcc.yaml | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,dcc.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,dcc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,dcc.yaml new file mode 100644 index 000000000000..ce7e20dd22c9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,dcc.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,dcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Data Capture and Compare + +maintainers: + - Souradeep Chowdhury + +description: | + DCC (Data Capture and Compare) is a DMA engine which is used to save + configuration data or system memory contents during catastrophic failure + or SW trigger. DCC is used to capture and store data for debugging purpose + +properties: + compatible: + items: + - enum: + - qcom,sm8150-dcc + - qcom,sc7280-dcc + - qcom,sc7180-dcc + - qcom,sdm845-dcc + - const: qcom,dcc + + reg: + items: + - description: DCC base + - description: DCC RAM base + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + dma@10a2000{ + compatible = "qcom,sm8150-dcc", "qcom,dcc"; + reg = <0x010a2000 0x1000>, + <0x010ad000 0x2000>; + }; -- cgit v1.2.3 From 4cbe60cf5ad622f7f45ccc4fa369c9f7a71903b9 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Tue, 27 Dec 2022 20:52:46 +0530 Subject: soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC) The DCC is a DMA Engine designed to capture and store data during system crash or software triggers. The DCC operates based on user inputs via the debugfs interface. The user gives addresses as inputs and these addresses are stored in the dcc sram. In case of a system crash or a manual software trigger by the user through the debugfs interface, the dcc captures and stores the values at these addresses. This patch contains the driver which has all the methods pertaining to the debugfs interface, auxiliary functions to support all the four fundamental operations of dcc namely read, write, read/modify/write and loop. The probe method here instantiates all the resources necessary for dcc to operate mainly the dedicated dcc sram where it stores the values. The DCC driver can be used for debugging purposes without going for a reboot since it can perform software triggers as well based on user inputs. Also add the documentation for debugfs entries which explains the functionalities of each debugfs file that has been created for dcc. The following is the justification of using debugfs interface over the other alternatives like sysfs/ioctls i) As can be seen from the debugfs attribute descriptions, some of the debugfs attribute files here contains multiple arguments which needs to be accepted from the user. This goes against the design style of sysfs. ii) The user input patterns have been made simple and convenient in this case with the use of debugfs interface as user doesn't need to shuffle between different files to execute one instruction as was the case on using other alternatives. Signed-off-by: Souradeep Chowdhury Reviewed-by: Alex Elder [bjorn: Fixed up a few indents and line wraps] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/644b4f66a358492a8a6738454035c3b120092fe7.1672148732.git.quic_schowdhu@quicinc.com --- Documentation/ABI/testing/debugfs-driver-dcc | 98 ++ drivers/soc/qcom/Kconfig | 8 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/dcc.c | 1299 ++++++++++++++++++++++++++ 4 files changed, 1406 insertions(+) create mode 100644 Documentation/ABI/testing/debugfs-driver-dcc create mode 100644 drivers/soc/qcom/dcc.c (limited to 'Documentation') diff --git a/Documentation/ABI/testing/debugfs-driver-dcc b/Documentation/ABI/testing/debugfs-driver-dcc new file mode 100644 index 000000000000..a46809502059 --- /dev/null +++ b/Documentation/ABI/testing/debugfs-driver-dcc @@ -0,0 +1,98 @@ +What: /sys/kernel/debug/dcc/.../ready +Date: December 2022 +Contact: Souradeep Chowdhury +Description: + This file is used to check the status of the dcc + hardware if it's ready to take the inputs. A 'Y' + here indicates dcc is in a ready condition. + Example: + cat /sys/kernel/debug/dcc/.../ready + +What: /sys/kernel/debug/dcc/.../trigger +Date: December 2022 +Contact: Souradeep Chowdhury +Description: + This is the debugfs interface for manual software + triggers. The user can simply enter a 1 against + the debugfs file and enable a manual trigger. + Example: + echo 1 > /sys/kernel/debug/dcc/.../trigger + +What: /sys/kernel/debug/dcc/.../config_reset +Date: December 2022 +Contact: Souradeep Chowdhury +Description: + This file is used to reset the configuration of + a dcc driver to the default configuration. This + means that all the previous addresses stored in + the driver gets removed and user needs to enter + the address values from the start. + Example: + echo 1 > /sys/kernel/debug/dcc/../config_reset + +What: /sys/kernel/debug/dcc/.../[list-number]/config +Date: December 2022 +Contact: Souradeep Chowdhury +Description: + This stores the addresses of the registers which + should be read in case of a hardware crash or + manual software triggers. The addresses entered here + are considered under all the 4 types of dcc + instructions Read type, Write type, Read Modify Write + type and Loop type. The lists need to be configured + sequentially and not in a overlapping manner. As an + example user can jump to list x only after list y is + configured and enabled. The format for entering all + types of instructions are explained in examples as + follows. + Example: + i)Read Type Instruction + echo R <1> <2> <3> >/sys/kernel/debug/dcc/../[list-number]/config + 1->Address to be considered for reading the value. + 2->The word count of the addresses, read n words + starting from address <1>. Each word is of 32 bits. + If not entered 1 is considered. + 3->Can be 'apb' or 'ahb' which indicates if it is apb or ahb + bus respectively. If not entered ahb is considered. + ii)Write Type Instruction + echo W <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config + 1->Address to be considered for writing the value. + 2->The value that needs to be written at the location. + 3->Can be a 'apb' or 'ahb' which indicates if it is apb or ahb + but respectively. + iii)Read Modify Write type instruction + echo RW <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config + 1->The address which needs to be considered for read then write. + 2->The value that needs to be written on the address. + 3->The mask of the value to be written. + iv)Loop Type Instruction + echo L <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config + 1->The loop count, the number of times the value of the addresses will be + captured. + 2->The address count, total number of addresses to be entered in this + instruction. + 3->The series of addresses to be entered separated by a space like + ... and so on. + +What: /sys/kernel/debug/dcc/.../[list-number]/enable +Date: December 2022 +Contact: Souradeep Chowdhury +Description: + This debugfs interface is used for enabling the + the dcc hardware. Enable file is kept under the + directory list number for which the user wants + to enable it. For example if the user wants to + enable list 1, then he should go for + echo 1 > /sys/kernel/debug/dcc/.../1/enable. + On enabling the dcc, all the addresses entered + by the user for the corresponding list is written + into dcc sram which is read by the dcc hardware + on manual or crash induced triggers. Lists should + be enabled sequentially.For example after configuring + addresses for list 1 and enabling it, a user can + proceed to enable list 2 or vice versa. + Example: + echo 0 > /sys/kernel/debug/dcc/.../[list-number]/enable + (disable dcc for the corresponding list number) + echo 1 > /sys/kernel/debug/dcc/.../[list-number]/enable + (enable dcc for the corresponding list number) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index df46108e58ce..21c4ce2315ba 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -70,6 +70,14 @@ config QCOM_LLCC SDM845. This provides interfaces to clients that use the LLCC. Say yes here to enable LLCC slice driver. +config QCOM_DCC + tristate "Qualcomm Technologies, Inc. Data Capture and Compare(DCC) engine driver" + depends on ARCH_QCOM || COMPILE_TEST + help + This option enables driver for Data Capture and Compare engine. DCC + driver provides interface to configure DCC block and read back + captured data from DCC's internal SRAM. + config QCOM_KRYO_L2_ACCESSORS bool depends on ARCH_QCOM && ARM64 || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 6e02333c4080..3b92c6c8e0ec 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_QCOM_AOSS_QMP) += qcom_aoss.o obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o obj-$(CONFIG_QCOM_CPR) += cpr.o +obj-$(CONFIG_QCOM_DCC) += dcc.o obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o obj-$(CONFIG_QCOM_OCMEM) += ocmem.o diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c new file mode 100644 index 000000000000..d4101f79cb5d --- /dev/null +++ b/drivers/soc/qcom/dcc.c @@ -0,0 +1,1299 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define STATUS_READY_TIMEOUT 5000 /* microseconds */ + +#define DCC_SRAM_NODE "dcc_sram" + +/* DCC registers */ +#define DCC_HW_INFO 0x04 +#define DCC_LL_NUM_INFO 0x10 +#define DCC_STATUS(vers) ((vers) == 1 ? 0x0c : 0x1c) +#define DCC_LL_LOCK 0x00 +#define DCC_LL_CFG 0x04 +#define DCC_LL_BASE 0x08 +#define DCC_FD_BASE 0x0c +#define DCC_LL_TIMEOUT 0x10 +#define DCC_LL_INT_ENABLE 0x18 +#define DCC_LL_INT_STATUS 0x1c +#define DCC_LL_SW_TRIGGER 0x2c +#define DCC_LL_BUS_ACCESS_STATUS 0x30 + +/* Default value used if a bit 6 in the HW_INFO register is set. */ +#define DCC_FIX_LOOP_OFFSET 16 + +/* Mask to find version info from HW_Info register */ +#define DCC_VER_INFO_MASK BIT(9) + +#define MAX_DCC_OFFSET GENMASK(9, 2) +#define MAX_DCC_LEN GENMASK(6, 0) +#define MAX_LOOP_CNT GENMASK(7, 0) +#define MAX_LOOP_ADDR 10 + +#define DCC_ADDR_DESCRIPTOR 0x00 +#define DCC_ADDR_LIMIT 27 +#define DCC_WORD_SIZE sizeof(u32) +#define DCC_ADDR_RANGE_MASK GENMASK(31, 4) +#define DCC_LOOP_DESCRIPTOR BIT(30) +#define DCC_RD_MOD_WR_DESCRIPTOR BIT(31) +#define DCC_LINK_DESCRIPTOR GENMASK(31, 30) +#define DCC_STATUS_MASK GENMASK(1, 0) +#define DCC_LOCK_MASK BIT(0) +#define DCC_LOOP_OFFSET_MASK BIT(6) +#define DCC_TRIGGER_MASK BIT(9) + +#define DCC_WRITE_MASK BIT(15) +#define DCC_WRITE_OFF_MASK GENMASK(7, 0) +#define DCC_WRITE_LEN_MASK GENMASK(14, 8) + +#define DCC_READ_IND 0x00 +#define DCC_WRITE_IND (BIT(28)) + +#define DCC_AHB_IND 0x00 +#define DCC_APB_IND BIT(29) + +#define DCC_MAX_LINK_LIST 8 + +#define DCC_VER_MASK2 GENMASK(5, 0) + +#define DCC_SRAM_WORD_LENGTH 4 + +#define DCC_RD_MOD_WR_ADDR 0xc105e + +enum dcc_descriptor_type { + DCC_READ_TYPE, + DCC_LOOP_TYPE, + DCC_READ_WRITE_TYPE, + DCC_WRITE_TYPE +}; + +struct dcc_config_entry { + u32 base; + u32 offset; + u32 len; + u32 loop_cnt; + u32 write_val; + u32 mask; + bool apb_bus; + enum dcc_descriptor_type desc_type; + struct list_head list; +}; + +/** + * struct dcc_drvdata - configuration information related to a dcc device + * @base: Base Address of the dcc device + * @dev: The device attached to the driver data + * @mutex: Lock to protect access and manipulation of dcc_drvdata + * @ram_base: Base address for the SRAM dedicated for the dcc device + * @ram_size: Total size of the SRAM dedicated for the dcc device + * @ram_offset: Offset to the SRAM dedicated for dcc device + * @mem_map_ver: Memory map version of DCC hardware + * @ram_cfg: Used for address limit calculation for dcc + * @ram_start: Starting address of DCC SRAM + * @sram_dev: Miscellaneous device equivalent of dcc SRAM + * @cfg_head: Points to the head of the linked list of addresses + * @dbg_dir: The dcc debugfs directory under which all the debugfs files are placed + * @nr_link_list: Total number of linkedlists supported by the DCC configuration + * @loop_shift: Loop offset bits range for the addresses + * @enable_bitmap: Bitmap to capture the enabled status of each linked list of addresses + */ +struct dcc_drvdata { + void __iomem *base; + void __iomem *ram_base; + struct device *dev; + struct mutex mutex; + size_t ram_size; + size_t ram_offset; + int mem_map_ver; + unsigned int ram_cfg; + unsigned int ram_start; + struct miscdevice sram_dev; + struct list_head *cfg_head; + struct dentry *dbg_dir; + size_t nr_link_list; + u8 loop_shift; + unsigned long *enable_bitmap; +}; + +struct dcc_cfg_attr { + u32 addr; + u32 prev_addr; + u32 prev_off; + u32 link; + u32 sram_offset; +}; + +struct dcc_cfg_loop_attr { + u32 loop_cnt; + u32 loop_len; + u32 loop_off; + bool loop_start; +}; + +static inline u32 dcc_list_offset(int version) +{ + return version == 1 ? 0x1c : version == 2 ? 0x2c : 0x34; +} + +static inline void dcc_list_writel(struct dcc_drvdata *drvdata, + u32 ll, u32 val, u32 off) +{ + u32 offset = dcc_list_offset(drvdata->mem_map_ver) + off; + + writel(val, drvdata->base + ll * 0x80 + offset); +} + +static inline u32 dcc_list_readl(struct dcc_drvdata *drvdata, u32 ll, u32 off) +{ + u32 offset = dcc_list_offset(drvdata->mem_map_ver) + off; + + return readl(drvdata->base + ll * 0x80 + offset); +} + +static void dcc_sram_write_auto(struct dcc_drvdata *drvdata, + u32 val, u32 *off) +{ + /* If the overflow condition is met increment the offset + * and return to indicate that overflow has occurred + */ + if (unlikely(*off > drvdata->ram_size - 4)) { + *off += 4; + return; + } + + writel(val, drvdata->ram_base + *off); + + *off += 4; +} + +static int dcc_sw_trigger(struct dcc_drvdata *drvdata) +{ + void __iomem *addr; + int ret = 0; + int i; + u32 status; + u32 ll_cfg; + u32 tmp_ll_cfg; + u32 val; + + mutex_lock(&drvdata->mutex); + + for (i = 0; i < drvdata->nr_link_list; i++) { + if (!test_bit(i, drvdata->enable_bitmap)) + continue; + ll_cfg = dcc_list_readl(drvdata, i, DCC_LL_CFG); + tmp_ll_cfg = ll_cfg & ~DCC_TRIGGER_MASK; + dcc_list_writel(drvdata, tmp_ll_cfg, i, DCC_LL_CFG); + dcc_list_writel(drvdata, 1, i, DCC_LL_SW_TRIGGER); + dcc_list_writel(drvdata, ll_cfg, i, DCC_LL_CFG); + } + + addr = drvdata->base + DCC_STATUS(drvdata->mem_map_ver); + if (readl_poll_timeout(addr, val, !FIELD_GET(DCC_STATUS_MASK, val), + 1, STATUS_READY_TIMEOUT)) { + dev_err(drvdata->dev, "DCC is busy after receiving sw trigger\n"); + ret = -EBUSY; + goto out_unlock; + } + + for (i = 0; i < drvdata->nr_link_list; i++) { + if (!test_bit(i, drvdata->enable_bitmap)) + continue; + + status = dcc_list_readl(drvdata, i, DCC_LL_BUS_ACCESS_STATUS); + if (!status) + continue; + + dev_err(drvdata->dev, "Read access error for list %d err: 0x%x\n", + i, status); + ll_cfg = dcc_list_readl(drvdata, i, DCC_LL_CFG); + tmp_ll_cfg = ll_cfg & ~DCC_TRIGGER_MASK; + dcc_list_writel(drvdata, tmp_ll_cfg, i, DCC_LL_CFG); + dcc_list_writel(drvdata, DCC_STATUS_MASK, i, DCC_LL_BUS_ACCESS_STATUS); + dcc_list_writel(drvdata, ll_cfg, i, DCC_LL_CFG); + ret = -ENODATA; + break; + } + +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static void dcc_ll_cfg_reset_link(struct dcc_cfg_attr *cfg) +{ + cfg->addr = 0x00; + cfg->link = 0; + cfg->prev_off = 0; + cfg->prev_addr = cfg->addr; +} + +static void dcc_emit_read_write(struct dcc_drvdata *drvdata, + struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg) +{ + if (cfg->link) { + /* + * write new offset = 1 to continue + * processing the list + */ + + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + /* Reset link and prev_off */ + dcc_ll_cfg_reset_link(cfg); + } + + cfg->addr = DCC_RD_MOD_WR_DESCRIPTOR; + dcc_sram_write_auto(drvdata, cfg->addr, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, entry->mask, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, entry->write_val, &cfg->sram_offset); + + cfg->addr = 0; +} + +static void dcc_emit_loop(struct dcc_drvdata *drvdata, struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg, + struct dcc_cfg_loop_attr *cfg_loop, + u32 *total_len) +{ + int loop; + + /* Check if we need to write link of prev entry */ + if (cfg->link) + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + if (cfg_loop->loop_start) { + loop = (cfg->sram_offset - cfg_loop->loop_off) / 4; + loop |= (cfg_loop->loop_cnt << drvdata->loop_shift) & + GENMASK(DCC_ADDR_LIMIT, drvdata->loop_shift); + loop |= DCC_LOOP_DESCRIPTOR; + *total_len += (*total_len - cfg_loop->loop_len) * cfg_loop->loop_cnt; + + dcc_sram_write_auto(drvdata, loop, &cfg->sram_offset); + + cfg_loop->loop_start = false; + cfg_loop->loop_len = 0; + cfg_loop->loop_off = 0; + } else { + cfg_loop->loop_start = true; + cfg_loop->loop_cnt = entry->loop_cnt - 1; + cfg_loop->loop_len = *total_len; + cfg_loop->loop_off = cfg->sram_offset; + } + + /* Reset link and prev_off */ + dcc_ll_cfg_reset_link(cfg); +} + +static void dcc_emit_write(struct dcc_drvdata *drvdata, + struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg) +{ + u32 off; + + if (cfg->link) { + /* + * write new offset = 1 to continue + * processing the list + */ + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + /* Reset link and prev_off */ + cfg->addr = 0x00; + cfg->prev_off = 0; + cfg->prev_addr = cfg->addr; + } + + off = entry->offset / 4; + /* write new offset-length pair to correct position */ + cfg->link |= ((off & DCC_WRITE_OFF_MASK) | DCC_WRITE_MASK | + FIELD_PREP(DCC_WRITE_LEN_MASK, entry->len)); + cfg->link |= DCC_LINK_DESCRIPTOR; + + /* Address type */ + cfg->addr = (entry->base >> 4) & GENMASK(DCC_ADDR_LIMIT, 0); + if (entry->apb_bus) + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_APB_IND; + else + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_AHB_IND; + dcc_sram_write_auto(drvdata, cfg->addr, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, entry->write_val, &cfg->sram_offset); + + cfg->addr = 0x00; + cfg->link = 0; +} + +static int dcc_emit_read(struct dcc_drvdata *drvdata, + struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg, + u32 *pos, u32 *total_len) +{ + u32 off; + u32 temp_off; + + cfg->addr = (entry->base >> 4) & GENMASK(27, 0); + + if (entry->apb_bus) + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_APB_IND; + else + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_AHB_IND; + + off = entry->offset / 4; + + *total_len += entry->len * 4; + + if (!cfg->prev_addr || cfg->prev_addr != cfg->addr || cfg->prev_off > off) { + /* Check if we need to write prev link entry */ + if (cfg->link) + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + dev_dbg(drvdata->dev, "DCC: sram address 0x%x\n", cfg->sram_offset); + + /* Write address */ + dcc_sram_write_auto(drvdata, cfg->addr, &cfg->sram_offset); + + /* Reset link and prev_off */ + cfg->link = 0; + cfg->prev_off = 0; + } + + if ((off - cfg->prev_off) > 0xff || entry->len > MAX_DCC_LEN) { + dev_err(drvdata->dev, "DCC: Programming error Base: 0x%x, offset 0x%x\n", + entry->base, entry->offset); + return -EINVAL; + } + + if (cfg->link) { + /* + * link already has one offset-length so new + * offset-length needs to be placed at + * bits [29:15] + */ + *pos = 15; + + /* Clear bits [31:16] */ + cfg->link &= GENMASK(14, 0); + } else { + /* + * link is empty, so new offset-length needs + * to be placed at bits [15:0] + */ + *pos = 0; + cfg->link = 1 << 15; + } + + /* write new offset-length pair to correct position */ + temp_off = (off - cfg->prev_off) & GENMASK(7, 0); + cfg->link |= temp_off | ((entry->len << 8) & GENMASK(14, 8)) << *pos; + + cfg->link |= DCC_LINK_DESCRIPTOR; + + if (*pos) { + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + cfg->link = 0; + } + + cfg->prev_off = off + entry->len - 1; + cfg->prev_addr = cfg->addr; + return 0; +} + +static int dcc_emit_config(struct dcc_drvdata *drvdata, unsigned int curr_list) +{ + int ret; + u32 total_len, pos; + struct dcc_config_entry *entry; + struct dcc_cfg_attr cfg; + struct dcc_cfg_loop_attr cfg_loop; + + memset(&cfg, 0, sizeof(cfg)); + memset(&cfg_loop, 0, sizeof(cfg_loop)); + cfg.sram_offset = drvdata->ram_cfg * 4; + total_len = 0; + + list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) { + switch (entry->desc_type) { + case DCC_READ_WRITE_TYPE: + dcc_emit_read_write(drvdata, entry, &cfg); + break; + + case DCC_LOOP_TYPE: + dcc_emit_loop(drvdata, entry, &cfg, &cfg_loop, &total_len); + break; + + case DCC_WRITE_TYPE: + dcc_emit_write(drvdata, entry, &cfg); + break; + + case DCC_READ_TYPE: + ret = dcc_emit_read(drvdata, entry, &cfg, &pos, &total_len); + if (ret) + goto err; + break; + } + } + + if (cfg.link) + dcc_sram_write_auto(drvdata, cfg.link, &cfg.sram_offset); + + if (cfg_loop.loop_start) { + dev_err(drvdata->dev, "DCC: Programming error: Loop unterminated\n"); + ret = -EINVAL; + goto err; + } + + /* Handling special case of list ending with a rd_mod_wr */ + if (cfg.addr == DCC_RD_MOD_WR_DESCRIPTOR) { + cfg.addr = (DCC_RD_MOD_WR_ADDR) & GENMASK(27, 0); + cfg.addr |= DCC_ADDR_DESCRIPTOR; + dcc_sram_write_auto(drvdata, cfg.addr, &cfg.sram_offset); + } + + /* Setting zero to indicate end of the list */ + cfg.link = DCC_LINK_DESCRIPTOR; + dcc_sram_write_auto(drvdata, cfg.link, &cfg.sram_offset); + + /* Check if sram offset exceeds the ram size */ + if (cfg.sram_offset > drvdata->ram_size) + goto overstep; + + /* Update ram_cfg and check if the data will overstep */ + drvdata->ram_cfg = (cfg.sram_offset + total_len) / 4; + + if (cfg.sram_offset + total_len > drvdata->ram_size) { + cfg.sram_offset += total_len; + goto overstep; + } + + drvdata->ram_start = cfg.sram_offset / 4; + return 0; +overstep: + ret = -EINVAL; + memset_io(drvdata->ram_base, 0, drvdata->ram_size); + +err: + return ret; +} + +static bool dcc_valid_list(struct dcc_drvdata *drvdata, unsigned int curr_list) +{ + u32 lock_reg; + + if (list_empty(&drvdata->cfg_head[curr_list])) + return false; + + if (test_bit(curr_list, drvdata->enable_bitmap)) { + dev_err(drvdata->dev, "List %d is already enabled\n", curr_list); + return false; + } + + lock_reg = dcc_list_readl(drvdata, curr_list, DCC_LL_LOCK); + if (lock_reg & DCC_LOCK_MASK) { + dev_err(drvdata->dev, "List %d is already locked\n", curr_list); + return false; + } + + return true; +} + +static bool is_dcc_enabled(struct dcc_drvdata *drvdata) +{ + int list; + + for (list = 0; list < drvdata->nr_link_list; list++) + if (test_bit(list, drvdata->enable_bitmap)) + return true; + + return false; +} + +static int dcc_enable(struct dcc_drvdata *drvdata, unsigned int curr_list) +{ + int ret; + u32 ram_cfg_base; + + mutex_lock(&drvdata->mutex); + + if (!dcc_valid_list(drvdata, curr_list)) { + ret = -EINVAL; + goto out_unlock; + } + + /* Fill dcc sram with the poison value. + * This helps in understanding bus + * hang from registers returning a zero + */ + if (!is_dcc_enabled(drvdata)) + memset_io(drvdata->ram_base, 0xde, drvdata->ram_size); + + /* 1. Take ownership of the list */ + dcc_list_writel(drvdata, DCC_LOCK_MASK, curr_list, DCC_LL_LOCK); + + /* 2. Program linked-list in the SRAM */ + ram_cfg_base = drvdata->ram_cfg; + ret = dcc_emit_config(drvdata, curr_list); + if (ret) { + dcc_list_writel(drvdata, 0, curr_list, DCC_LL_LOCK); + goto out_unlock; + } + + /* 3. Program DCC_RAM_CFG reg */ + dcc_list_writel(drvdata, ram_cfg_base + + drvdata->ram_offset / 4, curr_list, DCC_LL_BASE); + dcc_list_writel(drvdata, drvdata->ram_start + + drvdata->ram_offset / 4, curr_list, DCC_FD_BASE); + dcc_list_writel(drvdata, 0xFFF, curr_list, DCC_LL_TIMEOUT); + + /* 4. Clears interrupt status register */ + dcc_list_writel(drvdata, 0, curr_list, DCC_LL_INT_ENABLE); + dcc_list_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)), + curr_list, DCC_LL_INT_STATUS); + + set_bit(curr_list, drvdata->enable_bitmap); + + /* 5. Configure trigger */ + dcc_list_writel(drvdata, DCC_TRIGGER_MASK, + curr_list, DCC_LL_CFG); + +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static void dcc_disable(struct dcc_drvdata *drvdata, int curr_list) +{ + mutex_lock(&drvdata->mutex); + + if (!test_bit(curr_list, drvdata->enable_bitmap)) + goto out_unlock; + dcc_list_writel(drvdata, 0, curr_list, DCC_LL_CFG); + dcc_list_writel(drvdata, 0, curr_list, DCC_LL_BASE); + dcc_list_writel(drvdata, 0, curr_list, DCC_FD_BASE); + dcc_list_writel(drvdata, 0, curr_list, DCC_LL_LOCK); + clear_bit(curr_list, drvdata->enable_bitmap); +out_unlock: + mutex_unlock(&drvdata->mutex); +} + +static u32 dcc_filp_curr_list(const struct file *filp) +{ + struct dentry *dentry = file_dentry(filp); + int curr_list, ret; + + ret = kstrtoint(dentry->d_parent->d_name.name, 0, &curr_list); + if (ret) + return ret; + + return curr_list; +} + +static ssize_t enable_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *ppos) +{ + char *buf; + struct dcc_drvdata *drvdata = filp->private_data; + + mutex_lock(&drvdata->mutex); + + if (is_dcc_enabled(drvdata)) + buf = "Y\n"; + else + buf = "N\n"; + + mutex_unlock(&drvdata->mutex); + + return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf)); +} + +static ssize_t enable_write(struct file *filp, const char __user *userbuf, + size_t count, loff_t *ppos) +{ + int ret = 0, curr_list; + bool val; + struct dcc_drvdata *drvdata = filp->private_data; + + curr_list = dcc_filp_curr_list(filp); + if (curr_list < 0) + return curr_list; + + ret = kstrtobool_from_user(userbuf, count, &val); + if (ret < 0) + return ret; + + if (val) { + ret = dcc_enable(drvdata, curr_list); + if (ret) + return ret; + } else { + dcc_disable(drvdata, curr_list); + } + + return count; +} + +static const struct file_operations enable_fops = { + .read = enable_read, + .write = enable_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static ssize_t trigger_write(struct file *filp, + const char __user *user_buf, size_t count, + loff_t *ppos) +{ + int ret; + unsigned int val; + struct dcc_drvdata *drvdata = filp->private_data; + + ret = kstrtouint_from_user(user_buf, count, 0, &val); + if (ret < 0) + return ret; + + if (val != 1) + return -EINVAL; + + ret = dcc_sw_trigger(drvdata); + if (ret < 0) + return ret; + + return count; +} + +static const struct file_operations trigger_fops = { + .write = trigger_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int addr, + unsigned int len, bool apb_bus, int curr_list) +{ + int ret = 0; + struct dcc_config_entry *entry, *pentry; + unsigned int base, offset; + + mutex_lock(&drvdata->mutex); + + if (!len || len > drvdata->ram_size / DCC_WORD_SIZE) { + dev_err(drvdata->dev, "DCC: Invalid length\n"); + ret = -EINVAL; + goto out_unlock; + } + + base = addr & DCC_ADDR_RANGE_MASK; + + if (!list_empty(&drvdata->cfg_head[curr_list])) { + pentry = list_last_entry(&drvdata->cfg_head[curr_list], + struct dcc_config_entry, list); + + if (pentry->desc_type == DCC_READ_TYPE && + addr >= (pentry->base + pentry->offset) && + addr <= (pentry->base + pentry->offset + MAX_DCC_OFFSET)) { + /* Re-use base address from last entry */ + base = pentry->base; + + if ((pentry->len * 4 + pentry->base + pentry->offset) + == addr) { + len += pentry->len; + + if (len > MAX_DCC_LEN) + pentry->len = MAX_DCC_LEN; + else + pentry->len = len; + + addr = pentry->base + pentry->offset + + pentry->len * 4; + len -= pentry->len; + } + } + } + + offset = addr - base; + + while (len) { + entry = kzalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) { + ret = -ENOMEM; + goto out_unlock; + } + + entry->base = base; + entry->offset = offset; + entry->len = min_t(u32, len, MAX_DCC_LEN); + entry->desc_type = DCC_READ_TYPE; + entry->apb_bus = apb_bus; + INIT_LIST_HEAD(&entry->list); + list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); + + len -= entry->len; + offset += MAX_DCC_LEN * 4; + } + +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static ssize_t dcc_config_add_read(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + bool bus; + int len, nval; + unsigned int base; + char apb_bus[4]; + + nval = sscanf(buf, "%x %i %3s", &base, &len, apb_bus); + if (nval <= 0 || nval > 3) + return -EINVAL; + + if (nval == 1) { + len = 1; + bus = false; + } else if (nval == 2) { + bus = false; + } else if (!strcmp("apb", apb_bus)) { + bus = true; + } else if (!strcmp("ahb", apb_bus)) { + bus = false; + } else { + return -EINVAL; + } + + return dcc_config_add(drvdata, base, len, bus, curr_list); +} + +static void dcc_config_reset(struct dcc_drvdata *drvdata) +{ + struct dcc_config_entry *entry, *temp; + int curr_list; + + mutex_lock(&drvdata->mutex); + + for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) { + list_for_each_entry_safe(entry, temp, + &drvdata->cfg_head[curr_list], list) { + list_del(&entry->list); + kfree(entry); + } + } + drvdata->ram_start = 0; + drvdata->ram_cfg = 0; + mutex_unlock(&drvdata->mutex); +} + +static ssize_t config_reset_write(struct file *filp, + const char __user *user_buf, size_t count, + loff_t *ppos) +{ + unsigned int val, ret; + struct dcc_drvdata *drvdata = filp->private_data; + + ret = kstrtouint_from_user(user_buf, count, 0, &val); + if (ret < 0) + return ret; + + if (val) + dcc_config_reset(drvdata); + + return count; +} + +static const struct file_operations config_reset_fops = { + .write = config_reset_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static ssize_t ready_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *ppos) +{ + int ret = 0; + char *buf; + struct dcc_drvdata *drvdata = filp->private_data; + + mutex_lock(&drvdata->mutex); + + if (!is_dcc_enabled(drvdata)) { + ret = -EINVAL; + goto out_unlock; + } + + if (!FIELD_GET(BIT(1), readl(drvdata->base + DCC_STATUS(drvdata->mem_map_ver)))) + buf = "Y\n"; + else + buf = "N\n"; +out_unlock: + mutex_unlock(&drvdata->mutex); + + if (ret < 0) + return -EINVAL; + else + return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf) + 1); +} + +static const struct file_operations ready_fops = { + .read = ready_read, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt, int curr_list) +{ + struct dcc_config_entry *entry; + + entry = kzalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENOMEM; + + entry->loop_cnt = min_t(u32, loop_cnt, MAX_LOOP_CNT); + entry->desc_type = DCC_LOOP_TYPE; + INIT_LIST_HEAD(&entry->list); + list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); + + return 0; +} + +static ssize_t dcc_config_add_loop(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + int ret, i = 0; + char *token, *input; + char delim[2] = " "; + unsigned int val[MAX_LOOP_ADDR]; + + input = buf; + + while ((token = strsep(&input, delim)) && i < MAX_LOOP_ADDR) { + ret = kstrtoint(token, 0, &val[i++]); + if (ret) + return ret; + } + + if (token) { + dev_err(drvdata->dev, "Max limit %u of loop address exceeded", + MAX_LOOP_ADDR); + return -EINVAL; + } + + if (val[1] < 1 || val[1] > 8) + return -EINVAL; + + ret = dcc_add_loop(drvdata, val[0], curr_list); + if (ret) + return ret; + + for (i = 0; i < val[1]; i++) + dcc_config_add(drvdata, val[i + 2], 1, false, curr_list); + + return dcc_add_loop(drvdata, 1, curr_list); +} + +static int dcc_rd_mod_wr_add(struct dcc_drvdata *drvdata, unsigned int mask, + unsigned int val, int curr_list) +{ + int ret = 0; + struct dcc_config_entry *entry; + + mutex_lock(&drvdata->mutex); + + if (list_empty(&drvdata->cfg_head[curr_list])) { + dev_err(drvdata->dev, "DCC: No read address programmed\n"); + ret = -EPERM; + goto out_unlock; + } + + entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); + if (!entry) { + ret = -ENOMEM; + goto out_unlock; + } + + entry->desc_type = DCC_READ_WRITE_TYPE; + entry->mask = mask; + entry->write_val = val; + list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static ssize_t dcc_config_add_read_write(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + int ret; + int nval; + unsigned int addr, mask, val; + + nval = sscanf(buf, "%x %x %x", &addr, &mask, &val); + + if (nval <= 1 || nval > 3) + return -EINVAL; + + ret = dcc_config_add(drvdata, addr, 1, false, curr_list); + if (ret) + return ret; + + return dcc_rd_mod_wr_add(drvdata, mask, val, curr_list); +} + +static int dcc_add_write(struct dcc_drvdata *drvdata, unsigned int addr, + unsigned int write_val, int apb_bus, int curr_list) +{ + struct dcc_config_entry *entry; + + entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENOMEM; + + entry->desc_type = DCC_WRITE_TYPE; + entry->base = addr & GENMASK(31, 4); + entry->offset = addr - entry->base; + entry->write_val = write_val; + entry->len = 1; + entry->apb_bus = apb_bus; + list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); + + return 0; +} + +static ssize_t dcc_config_add_write(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + bool bus; + int nval; + unsigned int addr, write_val; + char apb_bus[4]; + + nval = sscanf(buf, "%x %x %3s", &addr, &write_val, apb_bus); + + if (nval <= 1 || nval > 3) + return -EINVAL; + + if (nval == 2) + bus = true; + + if (nval == 3) { + if (!strcmp("apb", apb_bus)) + bus = true; + else if (!strcmp("ahb", apb_bus)) + bus = false; + else + return -EINVAL; + } + + return dcc_add_write(drvdata, addr, write_val, bus, curr_list); +} + +static int config_show(struct seq_file *m, void *data) +{ + struct dcc_drvdata *drvdata = m->private; + struct dcc_config_entry *entry; + int index = 0, curr_list; + + curr_list = dcc_filp_curr_list(m->file); + if (curr_list < 0) + return curr_list; + + mutex_lock(&drvdata->mutex); + + list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) { + index++; + switch (entry->desc_type) { + case DCC_READ_WRITE_TYPE: + seq_printf(m, "RW mask: 0x%x, val: 0x%x\n index: 0x%x\n", + entry->mask, entry->write_val, index); + break; + case DCC_LOOP_TYPE: + seq_printf(m, "L index: 0x%x Loop: %d\n", index, entry->loop_cnt); + break; + case DCC_WRITE_TYPE: + seq_printf(m, "W Base:0x%x, Offset: 0x%x, val: 0x%x, APB: %d\n, Index: 0x%x\n", + entry->base, entry->offset, entry->write_val, entry->apb_bus, + index); + break; + case DCC_READ_TYPE: + seq_printf(m, "R Base:0x%x, Offset: 0x%x, len: 0x%x, APB: %d\n, Index: 0x%x\n", + entry->base, entry->offset, entry->len, entry->apb_bus, index); + } + } + mutex_unlock(&drvdata->mutex); + return 0; +} + +static int config_open(struct inode *inode, struct file *file) +{ + struct dcc_drvdata *drvdata = inode->i_private; + + return single_open(file, config_show, drvdata); +} + +static ssize_t config_write(struct file *filp, + const char __user *user_buf, size_t count, + loff_t *ppos) +{ + int ret, curr_list; + char *token, buf[50]; + char *bufp = buf; + char *delim = " "; + struct dcc_drvdata *drvdata = filp->private_data; + + if (count > sizeof(buf) || count == 0) + return -EINVAL; + + ret = copy_from_user(buf, user_buf, count); + if (ret) + return -EFAULT; + + curr_list = dcc_filp_curr_list(filp); + if (curr_list < 0) + return curr_list; + + if (buf[count - 1] == '\n') + buf[count - 1] = '\0'; + else + return -EINVAL; + + token = strsep(&bufp, delim); + + if (!strcmp("R", token)) { + ret = dcc_config_add_read(drvdata, bufp, curr_list); + } else if (!strcmp("W", token)) { + ret = dcc_config_add_write(drvdata, bufp, curr_list); + } else if (!strcmp("RW", token)) { + ret = dcc_config_add_read_write(drvdata, bufp, curr_list); + } else if (!strcmp("L", token)) { + ret = dcc_config_add_loop(drvdata, bufp, curr_list); + } else { + dev_err(drvdata->dev, "%s is not a correct input\n", token); + return -EINVAL; + } + + if (ret) + return ret; + + return count; +} + +static const struct file_operations config_fops = { + .open = config_open, + .read = seq_read, + .write = config_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static void dcc_delete_debug_dir(struct dcc_drvdata *drvdata) +{ + debugfs_remove_recursive(drvdata->dbg_dir); +}; + +static void dcc_create_debug_dir(struct dcc_drvdata *drvdata) +{ + int i; + char list_num[10]; + struct dentry *list; + struct device *dev = drvdata->dev; + + drvdata->dbg_dir = debugfs_create_dir(dev_name(dev), NULL); + if (IS_ERR(drvdata->dbg_dir)) { + pr_err("can't create debugfs dir\n"); + return; + } + + for (i = 0; i <= drvdata->nr_link_list; i++) { + sprintf(list_num, "%d", i); + list = debugfs_create_dir(list_num, drvdata->dbg_dir); + debugfs_create_file("enable", 0600, list, drvdata, &enable_fops); + debugfs_create_file("config", 0600, list, drvdata, &config_fops); + } + + debugfs_create_file("trigger", 0200, drvdata->dbg_dir, drvdata, &trigger_fops); + debugfs_create_file("ready", 0400, drvdata->dbg_dir, drvdata, &ready_fops); + debugfs_create_file("config_reset", 0200, drvdata->dbg_dir, + drvdata, &config_reset_fops); +} + +static ssize_t dcc_sram_read(struct file *file, char __user *data, + size_t len, loff_t *ppos) +{ + struct dcc_drvdata *drvdata = container_of(file->private_data, struct dcc_drvdata, sram_dev); + unsigned char *buf; + + /* EOF check */ + if (*ppos >= drvdata->ram_size) + return 0; + + if ((*ppos + len) > drvdata->ram_size) + len = (drvdata->ram_size - *ppos); + + buf = kzalloc(len, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + memcpy_fromio(buf, drvdata->ram_base + *ppos, len); + + if (copy_to_user(data, buf, len)) { + kfree(buf); + return -EFAULT; + } + + *ppos += len; + + kfree(buf); + + return len; +} + +static const struct file_operations dcc_sram_fops = { + .owner = THIS_MODULE, + .read = dcc_sram_read, + .llseek = no_llseek, +}; + +static int dcc_sram_dev_init(struct dcc_drvdata *drvdata) +{ + drvdata->sram_dev.minor = MISC_DYNAMIC_MINOR; + drvdata->sram_dev.name = DCC_SRAM_NODE; + drvdata->sram_dev.fops = &dcc_sram_fops; + + return misc_register(&drvdata->sram_dev); +} + +static void dcc_sram_dev_exit(struct dcc_drvdata *drvdata) +{ + misc_deregister(&drvdata->sram_dev); +} + +static int dcc_probe(struct platform_device *pdev) +{ + u32 val; + int ret = 0, i; + struct device *dev = &pdev->dev; + struct dcc_drvdata *drvdata; + struct resource *res; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev = &pdev->dev; + platform_set_drvdata(pdev, drvdata); + + drvdata->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(drvdata->base)) + return PTR_ERR(drvdata->base); + + drvdata->ram_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); + if (IS_ERR(drvdata->ram_base)) + return PTR_ERR(drvdata->ram_base); + + drvdata->ram_size = resource_size(res); + + drvdata->ram_offset = (size_t)of_device_get_match_data(&pdev->dev); + + val = readl(drvdata->base + DCC_HW_INFO); + + if (FIELD_GET(DCC_VER_INFO_MASK, val)) { + drvdata->mem_map_ver = 3; + drvdata->nr_link_list = readl(drvdata->base + DCC_LL_NUM_INFO); + if (!drvdata->nr_link_list) + return -EINVAL; + } else if ((val & DCC_VER_MASK2) == DCC_VER_MASK2) { + drvdata->mem_map_ver = 2; + drvdata->nr_link_list = readl(drvdata->base + DCC_LL_NUM_INFO); + if (!drvdata->nr_link_list) + return -EINVAL; + } else { + drvdata->mem_map_ver = 1; + drvdata->nr_link_list = DCC_MAX_LINK_LIST; + } + + /* Either set the fixed loop offset or calculate + * it from the total number of words in dcc_sram. + * Max consecutive addresses dcc can loop is + * equivalent to the words in dcc_sram. + */ + if (val & DCC_LOOP_OFFSET_MASK) + drvdata->loop_shift = DCC_FIX_LOOP_OFFSET; + else + drvdata->loop_shift = get_bitmask_order((drvdata->ram_offset + + drvdata->ram_size) / DCC_SRAM_WORD_LENGTH - 1); + + mutex_init(&drvdata->mutex); + + drvdata->enable_bitmap = devm_kcalloc(dev, BITS_TO_LONGS(drvdata->nr_link_list), + sizeof(*drvdata->enable_bitmap), GFP_KERNEL); + if (!drvdata->enable_bitmap) + return -ENOMEM; + + drvdata->cfg_head = devm_kcalloc(dev, drvdata->nr_link_list, + sizeof(*drvdata->cfg_head), GFP_KERNEL); + if (!drvdata->cfg_head) + return -ENOMEM; + + for (i = 0; i < drvdata->nr_link_list; i++) + INIT_LIST_HEAD(&drvdata->cfg_head[i]); + + ret = dcc_sram_dev_init(drvdata); + if (ret) { + dev_err(drvdata->dev, "DCC: sram node not registered.\n"); + return ret; + } + + dcc_create_debug_dir(drvdata); + + return 0; +} + +static int dcc_remove(struct platform_device *pdev) +{ + struct dcc_drvdata *drvdata = platform_get_drvdata(pdev); + + dcc_delete_debug_dir(drvdata); + dcc_sram_dev_exit(drvdata); + dcc_config_reset(drvdata); + + return 0; +} + +static const struct of_device_id dcc_match_table[] = { + { .compatible = "qcom,sc7180-dcc", .data = (void *)0x6000 }, + { .compatible = "qcom,sc7280-dcc", .data = (void *)0x12000 }, + { .compatible = "qcom,sdm845-dcc", .data = (void *)0x6000 }, + { .compatible = "qcom,sm8150-dcc", .data = (void *)0x5000 }, + { } +}; +MODULE_DEVICE_TABLE(of, dcc_match_table); + +static struct platform_driver dcc_driver = { + .probe = dcc_probe, + .remove = dcc_remove, + .driver = { + .name = "qcom-dcc", + .of_match_table = dcc_match_table, + }, +}; +module_platform_driver(dcc_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Qualcomm Technologies Inc. DCC driver"); -- cgit v1.2.3 From dc2f5a499de420001813562ddbc9d51ece295978 Mon Sep 17 00:00:00 2001 From: Bagas Sanjaya Date: Fri, 30 Dec 2022 20:50:30 +0700 Subject: soc: qcom: dcc: Fix examples list on /sys/kernel/debug/dcc/.../[list-number]/config documentation kernel test robot reported htmldocs warnings: Documentation/ABI/testing/debugfs-driver-dcc:34: WARNING: Unexpected indentation. Documentation/ABI/testing/debugfs-driver-dcc:34: WARNING: Block quote ends without a blank line; unexpected unindent. Fix these by fixing numbered list syntax on description of /sys/kernel/debug/dcc/.../[list-number]/config, including adding blank line separators as appropriate. Link: https://lore.kernel.org/linux-doc/202212300426.eMLsZsvA-lkp@intel.com/ Fixes: 4cbe60cf5ad622 ("soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC)") Reported-by: kernel test robot Signed-off-by: Bagas Sanjaya Acked-by: Souradeep Chowdhury Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221230135030.17002-2-bagasdotme@gmail.com --- Documentation/ABI/testing/debugfs-driver-dcc | 63 ++++++++++++++++++---------- 1 file changed, 41 insertions(+), 22 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/debugfs-driver-dcc b/Documentation/ABI/testing/debugfs-driver-dcc index a46809502059..a00f4502885b 100644 --- a/Documentation/ABI/testing/debugfs-driver-dcc +++ b/Documentation/ABI/testing/debugfs-driver-dcc @@ -44,35 +44,54 @@ Description: example user can jump to list x only after list y is configured and enabled. The format for entering all types of instructions are explained in examples as - follows. - Example: - i)Read Type Instruction + follows: + + i) Read Type Instruction + echo R <1> <2> <3> >/sys/kernel/debug/dcc/../[list-number]/config + 1->Address to be considered for reading the value. + 2->The word count of the addresses, read n words starting from address <1>. Each word is of 32 bits. If not entered 1 is considered. + 3->Can be 'apb' or 'ahb' which indicates if it is apb or ahb bus respectively. If not entered ahb is considered. - ii)Write Type Instruction - echo W <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config - 1->Address to be considered for writing the value. - 2->The value that needs to be written at the location. - 3->Can be a 'apb' or 'ahb' which indicates if it is apb or ahb - but respectively. - iii)Read Modify Write type instruction - echo RW <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config - 1->The address which needs to be considered for read then write. - 2->The value that needs to be written on the address. - 3->The mask of the value to be written. - iv)Loop Type Instruction - echo L <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config - 1->The loop count, the number of times the value of the addresses will be - captured. - 2->The address count, total number of addresses to be entered in this - instruction. - 3->The series of addresses to be entered separated by a space like - ... and so on. + + ii) Write Type Instruction + + echo W <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config + + 1->Address to be considered for writing the value. + + 2->The value that needs to be written at the location. + + 3->Can be a 'apb' or 'ahb' which indicates if it is apb or ahb + but respectively. + + iii) Read Modify Write type instruction + + echo RW <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config + + 1->The address which needs to be considered for read then write. + + 2->The value that needs to be written on the address. + + 3->The mask of the value to be written. + + iv) Loop Type Instruction + + echo L <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config + + 1->The loop count, the number of times the value of the addresses will be + captured. + + 2->The address count, total number of addresses to be entered in this + instruction. + + 3->The series of addresses to be entered separated by a space like + ... and so on. What: /sys/kernel/debug/dcc/.../[list-number]/enable Date: December 2022 -- cgit v1.2.3 From 13763fb955a0043bd9b6fb1e237f4fd8fe8b3c75 Mon Sep 17 00:00:00 2001 From: Bagas Sanjaya Date: Fri, 30 Dec 2022 20:50:31 +0700 Subject: soc: qcom: dcc: rewrite description of dcc sysfs files The description of dcc sysfs files is somewhat confusing and not effective. Rewrite it to be clear. While at it, also use literal code block for config sysfs examples and remove redundant examples that are obvious. Signed-off-by: Bagas Sanjaya Acked-by: Souradeep Chowdhury Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221230135030.17002-3-bagasdotme@gmail.com --- Documentation/ABI/testing/debugfs-driver-dcc | 142 ++++++++++++++------------- 1 file changed, 76 insertions(+), 66 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/debugfs-driver-dcc b/Documentation/ABI/testing/debugfs-driver-dcc index a00f4502885b..27ed5919d21b 100644 --- a/Documentation/ABI/testing/debugfs-driver-dcc +++ b/Documentation/ABI/testing/debugfs-driver-dcc @@ -3,115 +3,125 @@ Date: December 2022 Contact: Souradeep Chowdhury Description: This file is used to check the status of the dcc - hardware if it's ready to take the inputs. A 'Y' - here indicates dcc is in a ready condition. - Example: - cat /sys/kernel/debug/dcc/.../ready + hardware if it's ready to receive user configurations. + A 'Y' here indicates dcc is ready. What: /sys/kernel/debug/dcc/.../trigger Date: December 2022 Contact: Souradeep Chowdhury Description: This is the debugfs interface for manual software - triggers. The user can simply enter a 1 against - the debugfs file and enable a manual trigger. - Example: - echo 1 > /sys/kernel/debug/dcc/.../trigger + triggers. The trigger can be invoked by writing '1' + to the file. What: /sys/kernel/debug/dcc/.../config_reset Date: December 2022 Contact: Souradeep Chowdhury Description: This file is used to reset the configuration of - a dcc driver to the default configuration. This - means that all the previous addresses stored in - the driver gets removed and user needs to enter - the address values from the start. - Example: - echo 1 > /sys/kernel/debug/dcc/../config_reset + a dcc driver to the default configuration. When '1' + is written to the file, all the previous addresses + stored in the driver gets removed and users need to + reconfigure addresses again. What: /sys/kernel/debug/dcc/.../[list-number]/config Date: December 2022 Contact: Souradeep Chowdhury Description: This stores the addresses of the registers which - should be read in case of a hardware crash or - manual software triggers. The addresses entered here - are considered under all the 4 types of dcc - instructions Read type, Write type, Read Modify Write - type and Loop type. The lists need to be configured - sequentially and not in a overlapping manner. As an - example user can jump to list x only after list y is - configured and enabled. The format for entering all - types of instructions are explained in examples as - follows: + can be read in case of a hardware crash or manual + software triggers. The input addresses type + can be one of following dcc instructions: read, + write, read-write, and loop type. The lists need to + be configured sequentially and not in a overlapping + manner; e.g. users can jump to list x only after + list y is configured and enabled. The input format for + each type is as follows: - i) Read Type Instruction + i) Read instruction - echo R <1> <2> <3> >/sys/kernel/debug/dcc/../[list-number]/config + :: - 1->Address to be considered for reading the value. + echo R >/sys/kernel/debug/dcc/../[list-number]/config - 2->The word count of the addresses, read n words - starting from address <1>. Each word is of 32 bits. - If not entered 1 is considered. + where: - 3->Can be 'apb' or 'ahb' which indicates if it is apb or ahb - bus respectively. If not entered ahb is considered. + + The address to be read. - ii) Write Type Instruction + + The addresses word count, starting from address <1>. + Each word is 32 bits (4 bytes). If omitted, defaulted + to 1. - echo W <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config + + The bus type, which can be either 'apb' or 'ahb'. + The default is 'ahb' if leaved out. - 1->Address to be considered for writing the value. + ii) Write instruction - 2->The value that needs to be written at the location. + :: - 3->Can be a 'apb' or 'ahb' which indicates if it is apb or ahb - but respectively. + echo W > /sys/kernel/debug/dcc/../[list-number]/config - iii) Read Modify Write type instruction + where: - echo RW <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config + + The address to be written. - 1->The address which needs to be considered for read then write. + + The value to be written at . - 2->The value that needs to be written on the address. + + The bus type, which can be either 'apb' or 'ahb'. - 3->The mask of the value to be written. + iii) Read-write instruction - iv) Loop Type Instruction + :: - echo L <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config + echo RW > /sys/kernel/debug/dcc/../[list-number]/config - 1->The loop count, the number of times the value of the addresses will be - captured. + where: - 2->The address count, total number of addresses to be entered in this - instruction. + + The address to be read and written. - 3->The series of addresses to be entered separated by a space like - ... and so on. + + The value to be written at . + + + The value mask. + + iv) Loop instruction + + :: + + echo L
... > /sys/kernel/debug/dcc/../[list-number]/config + + where: + + + Number of iterations + +
+ total number of addresses to be written + +
+ Space-separated list of addresses. What: /sys/kernel/debug/dcc/.../[list-number]/enable Date: December 2022 Contact: Souradeep Chowdhury Description: This debugfs interface is used for enabling the - the dcc hardware. Enable file is kept under the - directory list number for which the user wants - to enable it. For example if the user wants to - enable list 1, then he should go for - echo 1 > /sys/kernel/debug/dcc/.../1/enable. - On enabling the dcc, all the addresses entered + the dcc hardware. A file named "enable" is in the + directory list number where users can enable/disable + the specific list by writing boolean (1 or 0) to the + file. + + On enabling the dcc, all the addresses specified by the user for the corresponding list is written into dcc sram which is read by the dcc hardware - on manual or crash induced triggers. Lists should - be enabled sequentially.For example after configuring - addresses for list 1 and enabling it, a user can - proceed to enable list 2 or vice versa. - Example: - echo 0 > /sys/kernel/debug/dcc/.../[list-number]/enable - (disable dcc for the corresponding list number) - echo 1 > /sys/kernel/debug/dcc/.../[list-number]/enable - (enable dcc for the corresponding list number) + on manual or crash induced triggers. Lists must + be configured and enabled sequentially, e.g. list + 2 can only be enabled when list 1 have so. -- cgit v1.2.3 From 2433c716707a22635a4c3905b1966f022f7adb8e Mon Sep 17 00:00:00 2001 From: Nathan Lu Date: Tue, 6 Dec 2022 10:00:42 +0800 Subject: dt-bindings: mediatek: modify VDOSYS0 mmsys device tree Documentations for MT8188 modify VDOSYS0 mmsys device tree Documentations for MT8188. Signed-off-by: Nathan Lu Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221206020046.11333-3-nathan.lu@mediatek.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 0711f1834fbd..84de12709323 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -31,6 +31,7 @@ properties: - mediatek,mt8173-mmsys - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys + - mediatek,mt8188-vdosys0 - mediatek,mt8192-mmsys - mediatek,mt8365-mmsys - const: syscon -- cgit v1.2.3 From 5d98c6351d4690288c55c2fcb23a470e0675b4e5 Mon Sep 17 00:00:00 2001 From: Nathan Lu Date: Tue, 6 Dec 2022 10:00:43 +0800 Subject: dt-bindings: mediatek: modify VDOSYS0 mutex device tree Documentations for MT8188 modify VDOSYS0 mutex device tree Documentations for MT8188. Signed-off-by: Nathan Lu Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221206020046.11333-4-nathan.lu@mediatek.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index 9241e5fc7cff..15c133cac315 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -32,6 +32,7 @@ properties: - mediatek,mt8183-disp-mutex - mediatek,mt8186-disp-mutex - mediatek,mt8186-mdp3-mutex + - mediatek,mt8188-disp-mutex - mediatek,mt8192-disp-mutex - mediatek,mt8195-disp-mutex -- cgit v1.2.3 From 658a8ef679435959f550a45f7312afaebb9e20a8 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 9 Jan 2023 13:53:25 +0100 Subject: dt-bindings: firmware: convert meson_sm.txt to dt-schema Convert the Amlogic Secure Monitor bindings to dt-schema. Take in account usage the used variant with amlogic,meson-gx-sm. Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221117-b4-amlogic-bindings-convert-v2-1-36ad050bb625@linaro.org Signed-off-by: Neil Armstrong --- .../bindings/firmware/amlogic,meson-gxbb-sm.yaml | 39 ++++++++++++++++++++++ .../bindings/firmware/meson/meson_sm.txt | 15 --------- 2 files changed, 39 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/firmware/amlogic,meson-gxbb-sm.yaml delete mode 100644 Documentation/devicetree/bindings/firmware/meson/meson_sm.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/firmware/amlogic,meson-gxbb-sm.yaml b/Documentation/devicetree/bindings/firmware/amlogic,meson-gxbb-sm.yaml new file mode 100644 index 000000000000..8f50e698760e --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/amlogic,meson-gxbb-sm.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/amlogic,meson-gxbb-sm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Secure Monitor (SM) + +description: + In the Amlogic SoCs the Secure Monitor code is used to provide access to the + NVMEM, enable JTAG, set USB boot, etc... + +maintainers: + - Neil Armstrong + +properties: + compatible: + oneOf: + - const: amlogic,meson-gxbb-sm + - items: + - const: amlogic,meson-gx-sm + - const: amlogic,meson-gxbb-sm + + power-controller: + type: object + $ref: /schemas/power/amlogic,meson-sec-pwrc.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + firmware { + secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + }; + }; diff --git a/Documentation/devicetree/bindings/firmware/meson/meson_sm.txt b/Documentation/devicetree/bindings/firmware/meson/meson_sm.txt deleted file mode 100644 index c248cd44f727..000000000000 --- a/Documentation/devicetree/bindings/firmware/meson/meson_sm.txt +++ /dev/null @@ -1,15 +0,0 @@ -* Amlogic Secure Monitor - -In the Amlogic SoCs the Secure Monitor code is used to provide access to the -NVMEM, enable JTAG, set USB boot, etc... - -Required properties for the secure monitor node: -- compatible: Should be "amlogic,meson-gxbb-sm" - -Example: - - firmware { - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - }; - }; -- cgit v1.2.3 From bc5998b92b9ee8818cc0f7fe02604751389a154e Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 9 Jan 2023 13:53:30 +0100 Subject: dt-bindings: power: amlogic,meson-gx-pwrc: mark bindings as deprecated The amlogic,meson-gx-pwrc-vpu compatible isn't used anymore since [1] was merged in v5.8-rc1 and amlogic,meson-g12a-pwrc-vpu either since [2] was merged in v5.3-rc1. [1] commit 5273d6cacc06 ("arm64: dts: meson-gx: Switch to the meson-ee-pwrc bindings") [2] commit f4f1c8d9ace7 ("arm64: dts: meson-g12: add Everything-Else power domain controller") Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221117-b4-amlogic-bindings-convert-v2-6-36ad050bb625@linaro.org Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt index 99b5b10cda31..ba5865ae6bfe 100644 --- a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt +++ b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt @@ -1,5 +1,5 @@ -Amlogic Meson Power Controller -============================== +Amlogic Meson Power Controller (deprecated) +=========================================== The Amlogic Meson SoCs embeds an internal Power domain controller. -- cgit v1.2.3 From b4f0370d3ce276397f5c48af99d0b77548825eb1 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 9 Jan 2023 18:45:06 +0100 Subject: dt-bindings: power: qcom,rpmpd: document sa8775p Add a compatible for sa8775p platforms and relevant defines to the include file. Signed-off-by: Bartosz Golaszewski Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230109174511.1740856-14-brgl@bgdev.pl --- .../devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 633d49884019..1778d9851510 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -30,6 +30,7 @@ properties: - qcom,qcs404-rpmpd - qcom,qdu1000-rpmhpd - qcom,sa8540p-rpmhpd + - qcom,sa8775p-rpmhpd - qcom,sdm660-rpmpd - qcom,sc7180-rpmhpd - qcom,sc7280-rpmhpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 1e19e258a74d..3117bf7d5ebf 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -4,6 +4,25 @@ #ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H #define _DT_BINDINGS_POWER_QCOM_RPMPD_H +/* SA8775P Power Domain Indexes */ +#define SA8775P_CX 0 +#define SA8775P_CX_AO 1 +#define SA8775P_DDR 2 +#define SA8775P_EBI 3 +#define SA8775P_GFX 4 +#define SA8775P_LCX 5 +#define SA8775P_LMX 6 +#define SA8775P_MMCX 7 +#define SA8775P_MMCX_AO 8 +#define SA8775P_MSS 9 +#define SA8775P_MX 10 +#define SA8775P_MX_AO 11 +#define SA8775P_MXC 12 +#define SA8775P_MXC_AO 13 +#define SA8775P_NSP0 14 +#define SA8775P_NSP1 15 +#define SA8775P_XO 16 + /* SDM670 Power Domain Indexes */ #define SDM670_MX 0 #define SDM670_MX_AO 1 -- cgit v1.2.3 From 8f3945a9adce3934943b365bcd5ae2932737f028 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 22 Nov 2022 10:23:44 +0100 Subject: dt-bindings: firmware: qcom,scm: document MSM8226 clocks Document the clocks (core, bus and iface) used on MSM8226 SCM. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221122092345.44369-1-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 25688571ee7c..fc986f2f5d30 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -111,6 +111,7 @@ allOf: enum: - qcom,scm-apq8084 - qcom,scm-mdm9607 + - qcom,scm-msm8226 - qcom,scm-msm8916 - qcom,scm-msm8953 - qcom,scm-msm8974 -- cgit v1.2.3 From c5b8840c895a5b0291ef84e3f13d92c3414033e7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 22 Nov 2022 10:23:45 +0100 Subject: dt-bindings: firmware: qcom,scm: narrow clocks and interconnects SCM has clock inputs and interconnects only on some of the SoCs, so disallow them inb other cases, which makes the binding stricter. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221122092345.44369-2-krzysztof.kozlowski@linaro.org --- .../devicetree/bindings/firmware/qcom,scm.yaml | 44 ++++++++++++++++++---- 1 file changed, 37 insertions(+), 7 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index fc986f2f5d30..8e6e9ebb343d 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -82,6 +82,32 @@ properties: description: TCSR hardware block allOf: + # Clocks + - if: + properties: + compatible: + contains: + enum: + - qcom,scm-apq8064 + - qcom,scm-apq8084 + - qcom,scm-mdm9607 + - qcom,scm-msm8226 + - qcom,scm-msm8660 + - qcom,scm-msm8916 + - qcom,scm-msm8953 + - qcom,scm-msm8960 + - qcom,scm-msm8974 + - qcom,scm-msm8976 + - qcom,scm-sm6375 + then: + required: + - clocks + - clock-names + else: + properties: + clock-names: false + clocks: false + - if: properties: compatible: @@ -100,10 +126,6 @@ allOf: clocks: maxItems: 1 - required: - - clocks - - clock-names - - if: properties: compatible: @@ -128,9 +150,17 @@ allOf: minItems: 3 maxItems: 3 - required: - - clocks - - clock-names + # Interconnects + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,scm-sm8450 + then: + properties: + interconnects: false required: - compatible -- cgit v1.2.3 From 5b8db5b4f756bcb3a3f9b6577f32fc0d3867496f Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Fri, 16 Dec 2022 15:13:12 -0800 Subject: dt-bindings: firmware: scm: Add QDU1000/QRU1000 compatible Add compatible for scm driver for QDU1000 and QRU1000 platforms. These drivers only require the compatible field, so update the bindings accordingly for these platforms. Signed-off-by: Melody Olvera Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221216231312.22574-1-quic_molvera@quicinc.com --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 8e6e9ebb343d..9312a0953ea8 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -38,6 +38,7 @@ properties: - qcom,scm-msm8994 - qcom,scm-msm8996 - qcom,scm-msm8998 + - qcom,scm-qdu1000 - qcom,scm-sc7180 - qcom,scm-sc7280 - qcom,scm-sc8280xp -- cgit v1.2.3 From da0d37e42f93f7bd6351e7ef67a52ea9a272c761 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 9 Jan 2023 14:05:21 +0100 Subject: dt-bindings: reserved-memory: rmtfs: Make qcom,vmid an array Some SoCs mandate that the RMTFS is also assigned to the NAV VM, while others really don't want that. Since it has to be conditional, turn qcom,vmid into an u32 array so that we can handle the NAV case, as well as other similar ones if they pop up in the future. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230109130523.298971-1-konrad.dybcio@linaro.org --- .../devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml b/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml index 2998f1c8f0db..08eb10c25821 100644 --- a/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml +++ b/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml @@ -27,9 +27,11 @@ properties: identifier of the client to use this region for buffers qcom,vmid: - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32-array description: > - vmid of the remote processor, to set up memory protection + Array of vmids of the remote processors, to set up memory protection + minItems: 1 + maxItems: 2 required: - qcom,client-id -- cgit v1.2.3 From c525e181fda7f18b694dffb0f22686a4cb407cee Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Tue, 17 Jan 2023 02:48:40 +0000 Subject: dt-bindings: soc: qcom: smd-rpm: Exclude MSM8936 from glink-channels MSM8936/MSM8939 should like MSM8916 not require glink-channels. Reviewed-by: Krzysztof Kozlowski Acked-by: Krzysztof Kozlowski Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230117024846.1367794-3-bryan.odonoghue@linaro.org --- Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index 11c0f4dd797c..16fd67c0bd1f 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -80,6 +80,7 @@ if: enum: - qcom,rpm-apq8084 - qcom,rpm-msm8916 + - qcom,rpm-msm8936 - qcom,rpm-msm8974 - qcom,rpm-msm8976 - qcom,rpm-msm8953 -- cgit v1.2.3 From dfe5ac7023624617d402ca1c295552fbd271e20c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 13 Jan 2023 16:22:32 +0100 Subject: Revert "dt-bindings: power: rpmpd: Add SM4250 support" SM4250 and SM6115 use a shared device tree and the RPMPDs are identical. There's no need for a separate entry, so remove it. This reverts commit 45ac44ed10e58cf9b510e6552317ed7d2602346f. Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230113152232.2624545-2-konrad.dybcio@linaro.org --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 - include/dt-bindings/power/qcom-rpmpd.h | 10 ---------- 2 files changed, 11 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 1778d9851510..afad3135ed67 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -40,7 +40,6 @@ properties: - qcom,sdm845-rpmhpd - qcom,sdx55-rpmhpd - qcom,sdx65-rpmhpd - - qcom,sm4250-rpmpd - qcom,sm6115-rpmpd - qcom,sm6125-rpmpd - qcom,sm6350-rpmhpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 3117bf7d5ebf..6df4ee400ef8 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -325,16 +325,6 @@ #define SDM660_SSCMX 8 #define SDM660_SSCMX_VFL 9 -/* SM4250 Power Domains */ -#define SM4250_VDDCX 0 -#define SM4250_VDDCX_AO 1 -#define SM4250_VDDCX_VFL 2 -#define SM4250_VDDMX 3 -#define SM4250_VDDMX_AO 4 -#define SM4250_VDDMX_VFL 5 -#define SM4250_VDD_LPI_CX 6 -#define SM4250_VDD_LPI_MX 7 - /* SM6115 Power Domains */ #define SM6115_VDDCX 0 #define SM6115_VDDCX_AO 1 -- cgit v1.2.3 From afb37e2577938bb854f20d428d8f29a01ea8bc93 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Fri, 13 Jan 2023 21:41:13 +0530 Subject: dt-bindings: firmware: qcom,scm: Add optional interrupt Add an interrupt specification to the bindings to support the wait-queue feature on SM8450 SoCs. Signed-off-by: Guru Das Srinagesh Signed-off-by: Sibi Sankar Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230113161114.22607-2-quic_sibis@quicinc.com --- .../devicetree/bindings/firmware/qcom,scm.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 9312a0953ea8..4193492ba73e 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -74,6 +74,12 @@ properties: '#reset-cells': const: 1 + interrupts: + description: + The wait-queue interrupt that firmware raises as part of handshake + protocol to handle sleeping SCM calls. + maxItems: 1 + qcom,dload-mode: $ref: /schemas/types.yaml#/definitions/phandle-array items: @@ -163,6 +169,18 @@ allOf: properties: interconnects: false + # Interrupts + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,scm-sm8450 + then: + properties: + interrupts: false + required: - compatible -- cgit v1.2.3 From 1725dde87f1eb560497a3be85d3973a7deea7fa4 Mon Sep 17 00:00:00 2001 From: "Garmin.Chang" Date: Fri, 23 Dec 2022 16:05:52 +0800 Subject: dt-bindings: power: Add MT8188 power domains Add power domains dt-bindings for MT8188. Signed-off-by: Garmin.Chang Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221223080553.9397-2-Garmin.Chang@mediatek.com Signed-off-by: Matthias Brugger --- .../bindings/power/mediatek,power-controller.yaml | 2 + include/dt-bindings/power/mediatek,mt8188-power.h | 44 ++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 include/dt-bindings/power/mediatek,mt8188-power.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 605ec7ab5f63..c9acef80f452 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -28,6 +28,7 @@ properties: - mediatek,mt8173-power-controller - mediatek,mt8183-power-controller - mediatek,mt8186-power-controller + - mediatek,mt8188-power-controller - mediatek,mt8192-power-controller - mediatek,mt8195-power-controller @@ -84,6 +85,7 @@ $defs: "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain. "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. + "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain. "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain. maxItems: 1 diff --git a/include/dt-bindings/power/mediatek,mt8188-power.h b/include/dt-bindings/power/mediatek,mt8188-power.h new file mode 100644 index 000000000000..57e75cf3aa2c --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt8188-power.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang + */ + +#ifndef _DT_BINDINGS_POWER_MT8188_POWER_H +#define _DT_BINDINGS_POWER_MT8188_POWER_H + +#define MT8188_POWER_DOMAIN_MFG0 0 +#define MT8188_POWER_DOMAIN_MFG1 1 +#define MT8188_POWER_DOMAIN_MFG2 2 +#define MT8188_POWER_DOMAIN_MFG3 3 +#define MT8188_POWER_DOMAIN_MFG4 4 +#define MT8188_POWER_DOMAIN_PEXTP_MAC_P0 5 +#define MT8188_POWER_DOMAIN_PEXTP_PHY_TOP 6 +#define MT8188_POWER_DOMAIN_CSIRX_TOP 7 +#define MT8188_POWER_DOMAIN_ETHER 8 +#define MT8188_POWER_DOMAIN_HDMI_TX 9 +#define MT8188_POWER_DOMAIN_ADSP_AO 10 +#define MT8188_POWER_DOMAIN_ADSP_INFRA 11 +#define MT8188_POWER_DOMAIN_ADSP 12 +#define MT8188_POWER_DOMAIN_AUDIO 13 +#define MT8188_POWER_DOMAIN_AUDIO_ASRC 14 +#define MT8188_POWER_DOMAIN_VPPSYS0 15 +#define MT8188_POWER_DOMAIN_VDOSYS0 16 +#define MT8188_POWER_DOMAIN_VDOSYS1 17 +#define MT8188_POWER_DOMAIN_DP_TX 18 +#define MT8188_POWER_DOMAIN_EDP_TX 19 +#define MT8188_POWER_DOMAIN_VPPSYS1 20 +#define MT8188_POWER_DOMAIN_WPE 21 +#define MT8188_POWER_DOMAIN_VDEC0 22 +#define MT8188_POWER_DOMAIN_VDEC1 23 +#define MT8188_POWER_DOMAIN_VENC 24 +#define MT8188_POWER_DOMAIN_IMG_VCORE 25 +#define MT8188_POWER_DOMAIN_IMG_MAIN 26 +#define MT8188_POWER_DOMAIN_DIP 27 +#define MT8188_POWER_DOMAIN_IPE 28 +#define MT8188_POWER_DOMAIN_CAM_VCORE 29 +#define MT8188_POWER_DOMAIN_CAM_MAIN 30 +#define MT8188_POWER_DOMAIN_CAM_SUBA 31 +#define MT8188_POWER_DOMAIN_CAM_SUBB 32 + +#endif /* _DT_BINDINGS_POWER_MT8188_POWER_H */ -- cgit v1.2.3 From f32397bfbddef1c0bd1687a8f5581017b315bd00 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Mon, 2 Jan 2023 17:06:02 +0100 Subject: dt-bindings: input: mtk-pmic-keys: add binding for MT6357 PMIC Add binding documentation for the PMIC keys on MT6357. Signed-off-by: Fabien Parent Acked-by: Rob Herring Acked-by: Dmitry Torokhov Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20221005-mt6357-support-v8-1-560caaafee53@baylibre.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml index 2f72ec418415..037c3ae9f1c3 100644 --- a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml @@ -26,6 +26,7 @@ properties: enum: - mediatek,mt6323-keys - mediatek,mt6331-keys + - mediatek,mt6357-keys - mediatek,mt6358-keys - mediatek,mt6397-keys -- cgit v1.2.3 From fc5a643fdd0b7406e73e7f18e14308eeaa89d2b7 Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Mon, 2 Jan 2023 17:06:03 +0100 Subject: dt-bindings: soc: mediatek: convert pwrap documentation - Convert soc/mediatek/pwrap.txt to soc/mediatek/mediatek,pwrap.yaml - Add syscon compatible const for mt8186 and mt8195 to match the DTS needs, which is missing from pwrap.txt. Reviewed-by: Rob Herring Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20221005-mt6357-support-v8-2-560caaafee53@baylibre.com Signed-off-by: Matthias Brugger --- .../devicetree/bindings/leds/leds-mt6323.txt | 2 +- Documentation/devicetree/bindings/mfd/mt6397.txt | 2 +- .../bindings/soc/mediatek/mediatek,pwrap.yaml | 147 +++++++++++++++++++++ .../devicetree/bindings/soc/mediatek/pwrap.txt | 75 ----------- 4 files changed, 149 insertions(+), 77 deletions(-) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml delete mode 100644 Documentation/devicetree/bindings/soc/mediatek/pwrap.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/leds/leds-mt6323.txt b/Documentation/devicetree/bindings/leds/leds-mt6323.txt index 45bf9f7d85f3..73353692efa1 100644 --- a/Documentation/devicetree/bindings/leds/leds-mt6323.txt +++ b/Documentation/devicetree/bindings/leds/leds-mt6323.txt @@ -9,7 +9,7 @@ MT6323 PMIC hardware. For MT6323 MFD bindings see: Documentation/devicetree/bindings/mfd/mt6397.txt For MediaTek PMIC wrapper bindings see: -Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml Required properties: - compatible : Must be "mediatek,mt6323-led" diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt index 518986c44880..294693a8906c 100644 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt @@ -13,7 +13,7 @@ MT6397/MT6323 is a multifunction device with the following sub modules: It is interfaced to host controller using SPI interface by a proprietary hardware called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap. See the following for pwarp node definitions: -../soc/mediatek/pwrap.txt +../soc/mediatek/mediatek,pwrap.yaml This document describes the binding for MFD device and its sub module. diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml new file mode 100644 index 000000000000..3fefd634bc69 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,pwrap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek PMIC Wrapper + +maintainers: + - Flora Fu + - Alexandre Mergnat + +description: + On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface + is not directly visible to the CPU, but only through the PMIC wrapper + inside the SoC. The communication between the SoC and the PMIC can + optionally be encrypted. Also a non standard Dual IO SPI mode can be + used to increase speed. + + IP Pairing + + On MT8135 the pins of some SoC internal peripherals can be on the PMIC. + The signals of these pins are routed over the SPI bus using the pwrap + bridge. In the binding description below the properties needed for bridging + are marked with "IP Pairing". These are optional on SoCs which do not support + IP Pairing + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-pwrap + - mediatek,mt6765-pwrap + - mediatek,mt6779-pwrap + - mediatek,mt6797-pwrap + - mediatek,mt6873-pwrap + - mediatek,mt7622-pwrap + - mediatek,mt8135-pwrap + - mediatek,mt8173-pwrap + - mediatek,mt8183-pwrap + - mediatek,mt8186-pwrap + - mediatek,mt8188-pwrap + - mediatek,mt8195-pwrap + - mediatek,mt8365-pwrap + - mediatek,mt8516-pwrap + - items: + - enum: + - mediatek,mt8186-pwrap + - mediatek,mt8195-pwrap + - const: syscon + + reg: + minItems: 1 + items: + - description: PMIC wrapper registers + - description: IP pairing registers + + reg-names: + minItems: 1 + items: + - const: pwrap + - const: pwrap-bridge + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + items: + - description: SPI bus clock + - description: Main module clock + - description: System module clock + - description: Timer module clock + + clock-names: + minItems: 2 + items: + - const: spi + - const: wrap + - const: sys + - const: tmr + + resets: + minItems: 1 + items: + - description: PMIC wrapper reset + - description: IP pairing reset + + reset-names: + minItems: 1 + items: + - const: pwrap + - const: pwrap-bridge + + pmic: + type: object + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + +dependentRequired: + resets: [reset-names] + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8365-pwrap + then: + properties: + clocks: + minItems: 4 + + clock-names: + minItems: 4 + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pwrap@1000f000 { + compatible = "mediatek,mt8135-pwrap"; + reg = <0 0x1000f000 0 0x1000>, + <0 0x11017000 0 0x1000>; + reg-names = "pwrap", "pwrap-bridge"; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "spi", "wrap"; + resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, + <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; + reset-names = "pwrap", "pwrap-bridge"; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt deleted file mode 100644 index 12e4b4260b40..000000000000 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ /dev/null @@ -1,75 +0,0 @@ -MediaTek PMIC Wrapper Driver - -This document describes the binding for the MediaTek PMIC wrapper. - -On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface -is not directly visible to the CPU, but only through the PMIC wrapper -inside the SoC. The communication between the SoC and the PMIC can -optionally be encrypted. Also a non standard Dual IO SPI mode can be -used to increase speed. - -IP Pairing - -on MT8135 the pins of some SoC internal peripherals can be on the PMIC. -The signals of these pins are routed over the SPI bus using the pwrap -bridge. In the binding description below the properties needed for bridging -are marked with "IP Pairing". These are optional on SoCs which do not support -IP Pairing - -Required properties in pwrap device node. -- compatible: - "mediatek,mt2701-pwrap" for MT2701/7623 SoCs - "mediatek,mt6765-pwrap" for MT6765 SoCs - "mediatek,mt6779-pwrap" for MT6779 SoCs - "mediatek,mt6797-pwrap" for MT6797 SoCs - "mediatek,mt6873-pwrap" for MT6873/8192 SoCs - "mediatek,mt7622-pwrap" for MT7622 SoCs - "mediatek,mt8135-pwrap" for MT8135 SoCs - "mediatek,mt8173-pwrap" for MT8173 SoCs - "mediatek,mt8183-pwrap" for MT8183 SoCs - "mediatek,mt8186-pwrap" for MT8186 SoCs - "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap" for MT8188 SoCs - "mediatek,mt8195-pwrap" for MT8195 SoCs - "mediatek,mt8365-pwrap" for MT8365 SoCs - "mediatek,mt8516-pwrap" for MT8516 SoCs -- interrupts: IRQ for pwrap in SOC -- reg-names: "pwrap" is required; "pwrap-bridge" is optional. - "pwrap": Main registers base - "pwrap-bridge": bridge base (IP Pairing) -- reg: Must contain an entry for each entry in reg-names. -- clock-names: Must include the following entries: - "spi": SPI bus clock - "wrap": Main module clock - "sys": Optional system module clock - "tmr": Optional timer module clock -- clocks: Must contain an entry for each entry in clock-names. - -Optional properities: -- reset-names: Some SoCs include the following entries: - "pwrap" - "pwrap-bridge" (IP Pairing) -- resets: Must contain an entry for each entry in reset-names. -- pmic: Using either MediaTek PMIC MFD as the child device of pwrap - See the following for child node definitions: - Documentation/devicetree/bindings/mfd/mt6397.txt - or the regulator-only device as the child device of pwrap, such as MT6380. - See the following definitions for such kinds of devices. - Documentation/devicetree/bindings/regulator/mt6380-regulator.txt - -Example: - pwrap: pwrap@1000f000 { - compatible = "mediatek,mt8135-pwrap"; - reg = <0 0x1000f000 0 0x1000>, - <0 0x11017000 0 0x1000>; - reg-names = "pwrap", "pwrap-bridge"; - interrupts = ; - resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, - <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; - reset-names = "pwrap", "pwrap-bridge"; - clocks = <&clk26m>, <&clk26m>; - clock-names = "spi", "wrap"; - - pmic { - compatible = "mediatek,mt6397"; - }; - }; -- cgit v1.2.3 From 22282276ea7907a4faa230c21faa021b94ff2164 Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Mon, 2 Jan 2023 17:06:04 +0100 Subject: dt-bindings: mfd: mediatek: Add bindings for MT6357 PMIC Currently, almost all MT63XX PMIC are documented mfd/mt6397.txt. Unfortunately, the PMICs haven't always similar HW sub-features. To have a better human readable schema, I chose to make one PMIC schema to match the exact HW capabilities instead of convert mt6397.txt to mediatek,mt63xx.yaml and put a bunch of properties behind "if contain ... then ..." - add interrupt property - change property refs to match with new yaml documentation Reviewed-by: Krzysztof Kozlowski Acked-by: Lee Jones Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20221005-mt6357-support-v8-3-560caaafee53@baylibre.com Signed-off-by: Matthias Brugger --- .../devicetree/bindings/mfd/mediatek,mt6357.yaml | 111 +++++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml new file mode 100644 index 000000000000..837a77013d57 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6357 PMIC + +maintainers: + - Flora Fu + - Alexandre Mergnat + +description: | + MT6357 is a power management system chip containing 5 buck + converters and 29 LDOs. Supported features are audio codec, + USB battery charging, fuel gauge, RTC + + This is a multifunction device with the following sub modules: + - Regulator + - RTC + - Keys + + It is interfaced to host controller using SPI interface by a proprietary hardware + called PMIC wrapper or pwrap. This MFD is a child device of pwrap. + See the following for pwrap node definitions: + Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml + +properties: + compatible: + const: mediatek,mt6357 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + regulators: + type: object + $ref: /schemas/regulator/mediatek,mt6357-regulator.yaml + description: + List of MT6357 BUCKs and LDOs regulators. + + rtc: + type: object + $ref: /schemas/rtc/rtc.yaml# + description: + MT6357 Real Time Clock. + properties: + compatible: + const: mediatek,mt6357-rtc + start-year: true + required: + - compatible + + keys: + type: object + $ref: /schemas/input/mediatek,pmic-keys.yaml + description: + MT6357 power and home keys. + +required: + - compatible + - regulators + +additionalProperties: false + +examples: + - | + #include + + pwrap { + pmic { + compatible = "mediatek,mt6357"; + + interrupt-parent = <&pio>; + interrupts = <145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + mt6357_vproc_reg: buck-vproc { + regulator-name = "vproc"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <220>; + regulator-always-on; + }; + + // ... + + mt6357_vusb33_reg: ldo-vusb33 { + regulator-name = "vusb33"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <264>; + }; + }; + + rtc { + compatible = "mediatek,mt6357-rtc"; + }; + + keys { + compatible = "mediatek,mt6357-keys"; + }; + }; + }; -- cgit v1.2.3 From 0f62ed0092ec468f48847897738dfafa8b941991 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Wed, 18 Jan 2023 12:14:20 +0000 Subject: firmware: arm_scmi: Add debugfs ABI documentation for common entries Add description of the debugfs SCMI common ABI. Signed-off-by: Cristian Marussi Tested-by: Florian Fainelli Tested-by: Vincent Guittot Link: https://lore.kernel.org/r/20230118121426.492864-12-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- Documentation/ABI/testing/debugfs-scmi | 70 ++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/ABI/testing/debugfs-scmi (limited to 'Documentation') diff --git a/Documentation/ABI/testing/debugfs-scmi b/Documentation/ABI/testing/debugfs-scmi new file mode 100644 index 000000000000..ee7179ab2edf --- /dev/null +++ b/Documentation/ABI/testing/debugfs-scmi @@ -0,0 +1,70 @@ +What: /sys/kernel/debug/scmi//instance_name +Date: March 2023 +KernelVersion: 6.3 +Contact: cristian.marussi@arm.com +Description: The name of the underlying SCMI instance described by + all the debugfs accessors rooted at /sys/kernel/debug/scmi/, + expressed as the full name of the top DT SCMI node under which + this SCMI instance is rooted. +Users: Debugging, any userspace test suite + +What: /sys/kernel/debug/scmi//atomic_threshold_us +Date: March 2023 +KernelVersion: 6.3 +Contact: cristian.marussi@arm.com +Description: An optional time value, expressed in microseconds, representing, + on this SCMI instance , the threshold above which any SCMI + command, advertised to have an higher-than-threshold execution + latency, should not be considered for atomic mode of operation, + even if requested. +Users: Debugging, any userspace test suite + +What: /sys/kernel/debug/scmi//transport/type +Date: March 2023 +KernelVersion: 6.3 +Contact: cristian.marussi@arm.com +Description: A string representing the type of transport configured for this + SCMI instance . +Users: Debugging, any userspace test suite + +What: /sys/kernel/debug/scmi//transport/is_atomic +Date: March 2023 +KernelVersion: 6.3 +Contact: cristian.marussi@arm.com +Description: A boolean stating if the transport configured on the underlying + SCMI instance is capable of atomic mode of operation. +Users: Debugging, any userspace test suite + +What: /sys/kernel/debug/scmi//transport/max_rx_timeout_ms +Date: March 2023 +KernelVersion: 6.3 +Contact: cristian.marussi@arm.com +Description: Timeout in milliseconds allowed for SCMI synchronous replies + for the currently configured SCMI transport for instance . +Users: Debugging, any userspace test suite + +What: /sys/kernel/debug/scmi//transport/max_msg_size +Date: March 2023 +KernelVersion: 6.3 +Contact: cristian.marussi@arm.com +Description: Max message size of allowed SCMI messages for the currently + configured SCMI transport for instance . +Users: Debugging, any userspace test suite + +What: /sys/kernel/debug/scmi//transport/tx_max_msg +Date: March 2023 +KernelVersion: 6.3 +Contact: cristian.marussi@arm.com +Description: Max number of concurrently allowed in-flight SCMI messages for + the currently configured SCMI transport for instance on the + TX channels. +Users: Debugging, any userspace test suite + +What: /sys/kernel/debug/scmi//transport/rx_max_msg +Date: March 2023 +KernelVersion: 6.3 +Contact: cristian.marussi@arm.com +Description: Max number of concurrently allowed in-flight SCMI messages for + the currently configured SCMI transport for instance on the + RX channels. +Users: Debugging, any userspace test suite -- cgit v1.2.3 From 74225707b3349d52e6b99a2e15185b5db8126637 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Wed, 18 Jan 2023 12:14:22 +0000 Subject: firmware: arm_scmi: Add debugfs ABI documentation for raw mode Add description of the debugfs SCMI raw mode ABI. Signed-off-by: Cristian Marussi Tested-by: Florian Fainelli Tested-by: Vincent Guittot Link: https://lore.kernel.org/r/20230118121426.492864-14-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- Documentation/ABI/testing/debugfs-scmi-raw | 66 ++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/ABI/testing/debugfs-scmi-raw (limited to 'Documentation') diff --git a/Documentation/ABI/testing/debugfs-scmi-raw b/Documentation/ABI/testing/debugfs-scmi-raw new file mode 100644 index 000000000000..45817d465b1f --- /dev/null +++ b/Documentation/ABI/testing/debugfs-scmi-raw @@ -0,0 +1,66 @@ +What: /sys/kernel/debug/scmi//raw/message +Date: March 2023 +KernelVersion: 6.3 +Contact: cristian.marussi@arm.com +Description: SCMI Raw synchronous message injection/snooping facility; write + a complete SCMI synchronous command message (header included) + in little-endian binary format to have it sent to the configured + backend SCMI server for instance . + Any subsequently received response can be read from this same + entry if it arrived within the configured timeout. + Each write to the entry causes one command request to be built + and sent while the replies are read back one message at time + (receiving an EOF at each message boundary). +Users: Debugging, any userspace test suite + +What: /sys/kernel/debug/scmi//raw/message_async +Date: March 2023 +KernelVersion: 6.3 +Contact: cristian.marussi@arm.com +Description: SCMI Raw asynchronous message injection/snooping facility; write + a complete SCMI asynchronous command message (header included) + in little-endian binary format to have it sent to the configured + backend SCMI server for instance . + Any subsequently received response can be read from this same + entry if it arrived within the configured timeout. + Any additional delayed response received afterwards can be read + from this same entry too if it arrived within the configured + timeout. + Each write to the entry causes one command request to be built + and sent while the replies are read back one message at time + (receiving an EOF at each message boundary). +Users: Debugging, any userspace test suite + +What: /sys/kernel/debug/scmi//raw/errors +Date: March 2023 +KernelVersion: 6.3 +Contact: cristian.marussi@arm.com +Description: SCMI Raw message errors facility; any kind of timed-out or + generally unexpectedly received SCMI message, for instance , + can be read from this entry. + Each read gives back one message at time (receiving an EOF at + each message boundary). +Users: Debugging, any userspace test suite + +What: /sys/kernel/debug/scmi//raw/notification +Date: March 2023 +KernelVersion: 6.3 +Contact: cristian.marussi@arm.com +Description: SCMI Raw notification snooping facility; any notification + emitted by the backend SCMI server, for instance , can be + read from this entry. + Each read gives back one message at time (receiving an EOF at + each message boundary). +Users: Debugging, any userspace test suite + +What: /sys/kernel/debug/scmi//raw/reset +Date: March 2023 +KernelVersion: 6.3 +Contact: cristian.marussi@arm.com +Description: SCMI Raw stack reset facility; writing a value to this entry + causes the internal queues of any kind of received message, + still pending to be read out for instance , to be immediately + flushed. + Can be used to reset and clean the SCMI Raw stack between to + different test-run. +Users: Debugging, any userspace test suite -- cgit v1.2.3 From 7860701d1e6e6e048960567d4767d93d693d6faa Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Wed, 18 Jan 2023 12:14:26 +0000 Subject: firmware: arm_scmi: Add per-channel raw injection support On a system configured with multiple transport channels, expose a few additional debugfs per-channel entries to allow a user to explicitly select which transport channel to use for the SCMI message injection. Signed-off-by: Cristian Marussi Tested-by: Florian Fainelli Tested-by: Vincent Guittot Link: https://lore.kernel.org/r/20230118121426.492864-18-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- Documentation/ABI/testing/debugfs-scmi-raw | 43 ++++++++ drivers/firmware/arm_scmi/common.h | 2 + drivers/firmware/arm_scmi/driver.c | 38 ++++++-- drivers/firmware/arm_scmi/protocols.h | 3 + drivers/firmware/arm_scmi/raw_mode.c | 152 +++++++++++++++++++++++++---- drivers/firmware/arm_scmi/raw_mode.h | 3 +- 6 files changed, 217 insertions(+), 24 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/debugfs-scmi-raw b/Documentation/ABI/testing/debugfs-scmi-raw index 45817d465b1f..5468ec08c084 100644 --- a/Documentation/ABI/testing/debugfs-scmi-raw +++ b/Documentation/ABI/testing/debugfs-scmi-raw @@ -64,3 +64,46 @@ Description: SCMI Raw stack reset facility; writing a value to this entry Can be used to reset and clean the SCMI Raw stack between to different test-run. Users: Debugging, any userspace test suite + +What: /sys/kernel/debug/scmi//raw/channels//message +Date: March 2023 +KernelVersion: 6.3 +Contact: cristian.marussi@arm.com +Description: SCMI Raw synchronous message injection/snooping facility; write + a complete SCMI synchronous command message (header included) + in little-endian binary format to have it sent to the configured + backend SCMI server for instance through the transport + channel. + Any subsequently received response can be read from this same + entry if it arrived on channel within the configured + timeout. + Each write to the entry causes one command request to be built + and sent while the replies are read back one message at time + (receiving an EOF at each message boundary). + Note that these per-channel entries rooted at <..>/channels + exist only if the transport is configured to have more than + one channel. +Users: Debugging, any userspace test suite + +What: /sys/kernel/debug/scmi//raw/channels//message_async +Date: March 2023 +KernelVersion: 6.3 +Contact: cristian.marussi@arm.com +Description: SCMI Raw asynchronous message injection/snooping facility; write + a complete SCMI asynchronous command message (header included) + in little-endian binary format to have it sent to the configured + backend SCMI server for instance through the transport + channel. + Any subsequently received response can be read from this same + entry if it arrived on channel within the configured + timeout. + Any additional delayed response received afterwards can be read + from this same entry too if it arrived within the configured + timeout. + Each write to the entry causes one command request to be built + and sent while the replies are read back one message at time + (receiving an EOF at each message boundary). + Note that these per-channel entries rooted at <..>/channels + exist only if the transport is configured to have more than + one channel. +Users: Debugging, any userspace test suite diff --git a/drivers/firmware/arm_scmi/common.h b/drivers/firmware/arm_scmi/common.h index bf3883f169e3..c46dc5215af7 100644 --- a/drivers/firmware/arm_scmi/common.h +++ b/drivers/firmware/arm_scmi/common.h @@ -27,6 +27,8 @@ #include "protocols.h" #include "notify.h" +#define SCMI_MAX_CHANNELS 256 + #define SCMI_MAX_RESPONSE_TIMEOUT (2 * MSEC_PER_SEC) enum scmi_error_codes { diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index 282d7737cb8f..d21c7eafd641 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -660,6 +660,7 @@ void scmi_xfer_raw_put(const struct scmi_handle *handle, struct scmi_xfer *xfer) struct scmi_info *info = handle_to_scmi_info(handle); xfer->flags &= ~SCMI_XFER_FLAG_IS_RAW; + xfer->flags &= ~SCMI_XFER_FLAG_CHAN_SET; return __scmi_xfer_put(&info->tx_minfo, xfer); } @@ -896,7 +897,8 @@ static void scmi_handle_notification(struct scmi_chan_info *cinfo, if (IS_ENABLED(CONFIG_ARM_SCMI_RAW_MODE_SUPPORT)) { xfer->hdr.seq = MSG_XTRACT_TOKEN(msg_hdr); - scmi_raw_message_report(info->raw, xfer, SCMI_RAW_NOTIF_QUEUE); + scmi_raw_message_report(info->raw, xfer, SCMI_RAW_NOTIF_QUEUE, + cinfo->id); } __scmi_xfer_put(minfo, xfer); @@ -955,7 +957,9 @@ static void scmi_handle_response(struct scmi_chan_info *cinfo, * poll loop. */ if (!xfer->hdr.poll_completion) - scmi_raw_message_report(info->raw, xfer, SCMI_RAW_REPLY_QUEUE); + scmi_raw_message_report(info->raw, xfer, + SCMI_RAW_REPLY_QUEUE, + cinfo->id); } scmi_xfer_command_release(info, xfer); @@ -1078,7 +1082,8 @@ static int scmi_wait_for_reply(struct device *dev, const struct scmi_desc *desc, handle_to_scmi_info(cinfo->handle); scmi_raw_message_report(info->raw, xfer, - SCMI_RAW_REPLY_QUEUE); + SCMI_RAW_REPLY_QUEUE, + cinfo->id); } } } else { @@ -2608,14 +2613,35 @@ static struct scmi_debug_info *scmi_debugfs_common_setup(struct scmi_info *info) static int scmi_debugfs_raw_mode_setup(struct scmi_info *info) { - int ret = 0; + int id, num_chans = 0, ret = 0; + struct scmi_chan_info *cinfo; + u8 channels[SCMI_MAX_CHANNELS] = {}; + DECLARE_BITMAP(protos, SCMI_MAX_CHANNELS) = {}; if (!info->dbg) return -EINVAL; + /* Enumerate all channels to collect their ids */ + idr_for_each_entry(&info->tx_idr, cinfo, id) { + /* + * Cannot happen, but be defensive. + * Zero as num_chans is ok, warn and carry on. + */ + if (num_chans >= SCMI_MAX_CHANNELS || !cinfo) { + dev_warn(info->dev, + "SCMI RAW - Error enumerating channels\n"); + break; + } + + if (!test_bit(cinfo->id, protos)) { + channels[num_chans++] = cinfo->id; + set_bit(cinfo->id, protos); + } + } + info->raw = scmi_raw_mode_init(&info->handle, info->dbg->top_dentry, - info->id, info->desc, - info->tx_minfo.max_msg); + info->id, channels, num_chans, + info->desc, info->tx_minfo.max_msg); if (IS_ERR(info->raw)) { dev_err(info->dev, "Failed to initialize SCMI RAW Mode !\n"); ret = PTR_ERR(info->raw); diff --git a/drivers/firmware/arm_scmi/protocols.h b/drivers/firmware/arm_scmi/protocols.h index b5941beb8b03..78e1a01eb656 100644 --- a/drivers/firmware/arm_scmi/protocols.h +++ b/drivers/firmware/arm_scmi/protocols.h @@ -138,6 +138,9 @@ struct scmi_xfer { int state; #define SCMI_XFER_FLAG_IS_RAW BIT(0) #define SCMI_XFER_IS_RAW(x) ((x)->flags & SCMI_XFER_FLAG_IS_RAW) +#define SCMI_XFER_FLAG_CHAN_SET BIT(1) +#define SCMI_XFER_IS_CHAN_SET(x) \ + ((x)->flags & SCMI_XFER_FLAG_CHAN_SET) int flags; /* A lock to protect state and busy fields */ spinlock_t lock; diff --git a/drivers/firmware/arm_scmi/raw_mode.c b/drivers/firmware/arm_scmi/raw_mode.c index 037ef9c14fae..d40df099fd51 100644 --- a/drivers/firmware/arm_scmi/raw_mode.c +++ b/drivers/firmware/arm_scmi/raw_mode.c @@ -37,10 +37,17 @@ * which in turn is rooted under the corresponding underlying SCMI instance. * * /sys/kernel/debug/scmi/ - * |-- 0 + * `-- 0 * |-- atomic_threshold_us * |-- instance_name * |-- raw + * | |-- channels + * | | |-- 0x10 + * | | | |-- message + * | | | `-- message_async + * | | `-- 0x13 + * | | |-- message + * | | `-- message_async * | |-- errors * | |-- message * | |-- message_async @@ -65,6 +72,15 @@ * to be read; this is useful at test-suite start/stop to get * rid of any unread messages from the previous run. * + * with the per-channel entries rooted at /channels being present only on a + * system where multiple transport channels have been configured. + * + * Such per-channel entries can be used to explicitly choose a specific channel + * for SCMI bare message injection, in contrast with the general entries above + * where, instead, the selection of the proper channel to use is automatically + * performed based the protocol embedded in the injected message and on how the + * transport is configured on the system. + * * Note that other common general entries are available under transport/ to let * the user applications properly make up their expectations in terms of * timeouts and message characteristics. @@ -95,7 +111,6 @@ #include #include #include -#include #include #include #include @@ -104,6 +119,7 @@ #include #include #include +#include #include "common.h" @@ -140,6 +156,7 @@ struct scmi_raw_queue { * @desc: Pointer to the transport descriptor to use * @tx_max_msg: Maximum number of concurrent TX in-flight messages * @q: An array of Raw queue descriptors + * @chans_q: An XArray mapping optional additional per-channel queues * @free_waiters: Head of freelist for unused waiters * @free_mtx: A mutex to protect the waiters freelist * @active_waiters: Head of list for currently active and used waiters @@ -159,6 +176,7 @@ struct scmi_raw_mode_info { const struct scmi_desc *desc; int tx_max_msg; struct scmi_raw_queue *q[SCMI_RAW_MAX_QUEUE]; + struct xarray chans_q; struct list_head free_waiters; /* Protect free_waiters list */ struct mutex free_mtx; @@ -208,6 +226,8 @@ struct scmi_raw_buffer { * struct scmi_dbg_raw_data - Structure holding data needed by the debugfs * layer * + * @chan_id: The preferred channel to use: if zero the channel is automatically + * selected based on protocol. * @raw: A reference to the Raw instance. * @tx: A message buffer used to collect TX message on write. * @tx_size: The effective size of the TX message. @@ -216,6 +236,7 @@ struct scmi_raw_buffer { * @rx_size: The effective size of the RX message. */ struct scmi_dbg_raw_data { + u8 chan_id; struct scmi_raw_mode_info *raw; struct scmi_msg tx; size_t tx_size; @@ -224,6 +245,16 @@ struct scmi_dbg_raw_data { size_t rx_size; }; +static struct scmi_raw_queue * +scmi_raw_queue_select(struct scmi_raw_mode_info *raw, unsigned int idx, + unsigned int chan_id) +{ + if (!chan_id) + return raw->q[idx]; + + return xa_load(&raw->chans_q, chan_id); +} + static struct scmi_raw_buffer *scmi_raw_buffer_get(struct scmi_raw_queue *q) { unsigned long flags; @@ -563,6 +594,8 @@ static int scmi_xfer_raw_get_init(struct scmi_raw_mode_info *raw, void *buf, * * @raw: A reference to the Raw instance. * @xfer: The xfer to send + * @chan_id: The channel ID to use, if zero the channels is automatically + * selected based on the protocol used. * @async: A flag stating if an asynchronous command is required. * * This function send a previously built raw xfer using an appropriate channel @@ -576,14 +609,20 @@ static int scmi_xfer_raw_get_init(struct scmi_raw_mode_info *raw, void *buf, * Return: 0 on Success */ static int scmi_do_xfer_raw_start(struct scmi_raw_mode_info *raw, - struct scmi_xfer *xfer, bool async) + struct scmi_xfer *xfer, u8 chan_id, + bool async) { int ret; struct scmi_chan_info *cinfo; struct scmi_xfer_raw_waiter *rw; struct device *dev = raw->handle->dev; - cinfo = scmi_xfer_raw_channel_get(raw->handle, xfer->hdr.protocol_id); + if (!chan_id) + chan_id = xfer->hdr.protocol_id; + else + xfer->flags |= SCMI_XFER_FLAG_CHAN_SET; + + cinfo = scmi_xfer_raw_channel_get(raw->handle, chan_id); if (IS_ERR(cinfo)) return PTR_ERR(cinfo); @@ -630,12 +669,13 @@ static int scmi_do_xfer_raw_start(struct scmi_raw_mode_info *raw, * @buf: A buffer containing the whole SCMI message to send (including the * header) in little-endian binary format. * @len: Length of the message in @buf. + * @chan_id: The channel ID to use. * @async: A flag stating if an asynchronous command is required. * * Return: 0 on Success */ static int scmi_raw_message_send(struct scmi_raw_mode_info *raw, - void *buf, size_t len, bool async) + void *buf, size_t len, u8 chan_id, bool async) { int ret; struct scmi_xfer *xfer; @@ -644,7 +684,7 @@ static int scmi_raw_message_send(struct scmi_raw_mode_info *raw, if (ret) return ret; - ret = scmi_do_xfer_raw_start(raw, xfer, async); + ret = scmi_do_xfer_raw_start(raw, xfer, chan_id, async); if (ret) scmi_xfer_raw_put(raw->handle, xfer); @@ -687,18 +727,23 @@ scmi_raw_message_dequeue(struct scmi_raw_queue *q, bool o_nonblock) * @len: Length of @buf. * @size: The effective size of the message copied into @buf * @idx: The index of the queue to pick the next queued message from. + * @chan_id: The channel ID to use. * @o_nonblock: A flag to request a non-blocking message dequeue. * * Return: 0 on Success */ static int scmi_raw_message_receive(struct scmi_raw_mode_info *raw, void *buf, size_t len, size_t *size, - unsigned int idx, + unsigned int idx, unsigned int chan_id, bool o_nonblock) { int ret = 0; struct scmi_raw_buffer *rb; - struct scmi_raw_queue *q = raw->q[idx]; + struct scmi_raw_queue *q; + + q = scmi_raw_queue_select(raw, idx, chan_id); + if (!q) + return -ENODEV; rb = scmi_raw_message_dequeue(q, o_nonblock); if (IS_ERR(rb)) { @@ -732,7 +777,7 @@ static ssize_t scmi_dbg_raw_mode_common_read(struct file *filp, int ret; ret = scmi_raw_message_receive(rd->raw, rd->rx.buf, rd->rx.len, - &rd->rx_size, idx, + &rd->rx_size, idx, rd->chan_id, filp->f_flags & O_NONBLOCK); if (ret) { rd->rx_size = 0; @@ -782,7 +827,8 @@ static ssize_t scmi_dbg_raw_mode_common_write(struct file *filp, return cnt; } - ret = scmi_raw_message_send(rd->raw, rd->tx.buf, rd->tx_size, async); + ret = scmi_raw_message_send(rd->raw, rd->tx.buf, rd->tx_size, + rd->chan_id, async); /* Reset ppos for next message ... */ rd->tx_size = 0; @@ -797,9 +843,13 @@ static __poll_t scmi_test_dbg_raw_common_poll(struct file *filp, { unsigned long flags; struct scmi_dbg_raw_data *rd = filp->private_data; - struct scmi_raw_queue *q = rd->raw->q[idx]; + struct scmi_raw_queue *q; __poll_t mask = 0; + q = scmi_raw_queue_select(rd->raw, idx, rd->chan_id); + if (!q) + return mask; + poll_wait(filp, &q->wq, wait); spin_lock_irqsave(&q->msg_q_lock, flags); @@ -833,8 +883,10 @@ static __poll_t scmi_dbg_raw_mode_message_poll(struct file *filp, static int scmi_dbg_raw_mode_open(struct inode *inode, struct file *filp) { + u8 id; struct scmi_raw_mode_info *raw; struct scmi_dbg_raw_data *rd; + const char *id_str = filp->f_path.dentry->d_parent->d_name.name; if (!inode->i_private) return -ENODEV; @@ -859,6 +911,10 @@ static int scmi_dbg_raw_mode_open(struct inode *inode, struct file *filp) return -ENOMEM; } + /* Grab channel ID from debugfs entry naming if any */ + if (!kstrtou8(id_str, 16, &id)) + rd->chan_id = id; + rd->raw = raw; filp->private_data = rd; @@ -1028,7 +1084,8 @@ static int scmi_xfer_raw_worker_init(struct scmi_raw_mode_info *raw) return 0; } -static int scmi_raw_mode_setup(struct scmi_raw_mode_info *raw) +static int scmi_raw_mode_setup(struct scmi_raw_mode_info *raw, + u8 *channels, int num_chans) { int ret, idx; void *gid; @@ -1046,15 +1103,43 @@ static int scmi_raw_mode_setup(struct scmi_raw_mode_info *raw) } } + xa_init(&raw->chans_q); + if (num_chans > 1) { + int i; + + for (i = 0; i < num_chans; i++) { + void *xret; + struct scmi_raw_queue *q; + + q = scmi_raw_queue_init(raw); + if (IS_ERR(q)) { + ret = PTR_ERR(q); + goto err_xa; + } + + xret = xa_store(&raw->chans_q, channels[i], q, + GFP_KERNEL); + if (xa_err(xret)) { + dev_err(dev, + "Fail to allocate Raw queue 0x%02X\n", + channels[i]); + ret = xa_err(xret); + goto err_xa; + } + } + } + ret = scmi_xfer_raw_worker_init(raw); if (ret) - goto err; + goto err_xa; devres_close_group(dev, gid); raw->gid = gid; return 0; +err_xa: + xa_destroy(&raw->chans_q); err: devres_release_group(dev, gid); return ret; @@ -1067,6 +1152,8 @@ err: * @top_dentry: A reference to the top Raw debugfs dentry * @instance_id: The ID of the underlying SCMI platform instance represented by * this Raw instance + * @channels: The list of the existing channels + * @num_chans: The number of entries in @channels * @desc: Reference to the transport operations * @tx_max_msg: Max number of in-flight messages allowed by the transport * @@ -1076,6 +1163,7 @@ err: */ void *scmi_raw_mode_init(const struct scmi_handle *handle, struct dentry *top_dentry, int instance_id, + u8 *channels, int num_chans, const struct scmi_desc *desc, int tx_max_msg) { int ret; @@ -1095,7 +1183,7 @@ void *scmi_raw_mode_init(const struct scmi_handle *handle, raw->tx_max_msg = tx_max_msg; raw->id = instance_id; - ret = scmi_raw_mode_setup(raw); + ret = scmi_raw_mode_setup(raw, channels, num_chans); if (ret) { devm_kfree(dev, raw); return ERR_PTR(ret); @@ -1118,6 +1206,32 @@ void *scmi_raw_mode_init(const struct scmi_handle *handle, debugfs_create_file("errors", 0400, raw->dentry, raw, &scmi_dbg_raw_mode_errors_fops); + /* + * Expose per-channel entries if multiple channels available. + * Just ignore errors while setting up these interfaces since we + * have anyway already a working core Raw support. + */ + if (num_chans > 1) { + int i; + struct dentry *top_chans; + + top_chans = debugfs_create_dir("channels", raw->dentry); + + for (i = 0; i < num_chans; i++) { + char cdir[8]; + struct dentry *chd; + + snprintf(cdir, 8, "0x%02X", channels[i]); + chd = debugfs_create_dir(cdir, top_chans); + + debugfs_create_file("message", 0600, chd, raw, + &scmi_dbg_raw_mode_message_fops); + + debugfs_create_file("message_async", 0600, chd, raw, + &scmi_dbg_raw_mode_message_async_fops); + } + } + dev_info(dev, "SCMI RAW Mode initialized for instance %d\n", raw->id); return raw; @@ -1139,6 +1253,7 @@ void scmi_raw_mode_cleanup(void *r) cancel_work_sync(&raw->waiters_work); destroy_workqueue(raw->wait_wq); + xa_destroy(&raw->chans_q); } static int scmi_xfer_raw_collect(void *msg, size_t *msg_len, @@ -1178,6 +1293,7 @@ static int scmi_xfer_raw_collect(void *msg, size_t *msg_len, * @r: An opaque reference to the raw instance configuration * @xfer: The xfer containing the message to be reported * @idx: The index of the queue. + * @chan_id: The channel ID to use. * * If Raw mode is enabled, this is called from the SCMI core on the regular RX * path to save and enqueue the response/notification payload carried by this @@ -1187,7 +1303,8 @@ static int scmi_xfer_raw_collect(void *msg, size_t *msg_len, * user can read back the raw message payload at its own pace (if ever) without * holding an xfer for too long. */ -void scmi_raw_message_report(void *r, struct scmi_xfer *xfer, unsigned int idx) +void scmi_raw_message_report(void *r, struct scmi_xfer *xfer, + unsigned int idx, unsigned int chan_id) { int ret; unsigned long flags; @@ -1200,7 +1317,8 @@ void scmi_raw_message_report(void *r, struct scmi_xfer *xfer, unsigned int idx) return; dev = raw->handle->dev; - q = raw->q[idx]; + q = scmi_raw_queue_select(raw, idx, + SCMI_XFER_IS_CHAN_SET(xfer) ? chan_id : 0); /* * Grab the msg_q_lock upfront to avoid a possible race between @@ -1319,7 +1437,7 @@ void scmi_raw_error_report(void *r, struct scmi_chan_info *cinfo, smp_store_mb(xfer.priv, priv); scmi_xfer_raw_fill(raw, cinfo, &xfer, msg_hdr); - scmi_raw_message_report(raw, &xfer, SCMI_RAW_ERRS_QUEUE); + scmi_raw_message_report(raw, &xfer, SCMI_RAW_ERRS_QUEUE, 0); kfree(xfer.rx.buf); } diff --git a/drivers/firmware/arm_scmi/raw_mode.h b/drivers/firmware/arm_scmi/raw_mode.h index 1e3d1660b0e4..8af756a83fd1 100644 --- a/drivers/firmware/arm_scmi/raw_mode.h +++ b/drivers/firmware/arm_scmi/raw_mode.h @@ -19,11 +19,12 @@ enum { void *scmi_raw_mode_init(const struct scmi_handle *handle, struct dentry *top_dentry, int instance_id, + u8 *channels, int num_chans, const struct scmi_desc *desc, int tx_max_msg); void scmi_raw_mode_cleanup(void *raw); void scmi_raw_message_report(void *raw, struct scmi_xfer *xfer, - unsigned int idx); + unsigned int idx, unsigned int chan_id); void scmi_raw_error_report(void *raw, struct scmi_chan_info *cinfo, u32 msg_hdr, void *priv); -- cgit v1.2.3 From 32a55bbdd74e2bb76a76979bc4f37e7e7ebe620d Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Fri, 20 Jan 2023 12:23:26 +0000 Subject: firmware: arm_scmi: Clarify raw per-channel ABI documentation Explain more in detail how the per-channel identifier is chosen. Suggested-by: Vincent Guittot Signed-off-by: Cristian Marussi Link: https://lore.kernel.org/r/20230120122326.1932614-1-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- Documentation/ABI/testing/debugfs-scmi-raw | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/debugfs-scmi-raw b/Documentation/ABI/testing/debugfs-scmi-raw index 5468ec08c084..97678cc9535c 100644 --- a/Documentation/ABI/testing/debugfs-scmi-raw +++ b/Documentation/ABI/testing/debugfs-scmi-raw @@ -80,9 +80,13 @@ Description: SCMI Raw synchronous message injection/snooping facility; write Each write to the entry causes one command request to be built and sent while the replies are read back one message at time (receiving an EOF at each message boundary). + Channel identifier matches the SCMI protocol number which + has been associated with this transport channel in the DT + description, with base protocol number 0x10 being the default + channel for this instance. Note that these per-channel entries rooted at <..>/channels exist only if the transport is configured to have more than - one channel. + one default channel. Users: Debugging, any userspace test suite What: /sys/kernel/debug/scmi//raw/channels//message_async @@ -103,7 +107,11 @@ Description: SCMI Raw asynchronous message injection/snooping facility; write Each write to the entry causes one command request to be built and sent while the replies are read back one message at time (receiving an EOF at each message boundary). + Channel identifier matches the SCMI protocol number which + has been associated with this transport channel in the DT + description, with base protocol number 0x10 being the default + channel for this instance. Note that these per-channel entries rooted at <..>/channels exist only if the transport is configured to have more than - one channel. + one default channel. Users: Debugging, any userspace test suite -- cgit v1.2.3 From 1fc7606d5083f79a20eb9cfd77c0dbd9299421c1 Mon Sep 17 00:00:00 2001 From: Walker Chen Date: Thu, 19 Jan 2023 17:44:46 +0800 Subject: dt-bindings: power: Add starfive,jh7110-pmu Add bindings for the Power Management Unit on the StarFive JH7110 SoC. Signed-off-by: Walker Chen Reviewed-by: Krzysztof Kozlowski Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley Signed-off-by: Conor Dooley --- .../bindings/power/starfive,jh7110-pmu.yaml | 45 ++++++++++++++++++++++ include/dt-bindings/power/starfive,jh7110-pmu.h | 17 ++++++++ 2 files changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml create mode 100644 include/dt-bindings/power/starfive,jh7110-pmu.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml new file mode 100644 index 000000000000..98eb8b4110e7 --- /dev/null +++ b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/starfive,jh7110-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Power Management Unit + +maintainers: + - Walker Chen + +description: | + StarFive JH7110 SoC includes support for multiple power domains which can be + powered on/off by software based on different application scenes to save power. + +properties: + compatible: + enum: + - starfive,jh7110-pmu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#power-domain-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + pwrc: power-controller@17030000 { + compatible = "starfive,jh7110-pmu"; + reg = <0x17030000 0x10000>; + interrupts = <111>; + #power-domain-cells = <1>; + }; diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-bindings/power/starfive,jh7110-pmu.h new file mode 100644 index 000000000000..132bfe401fc8 --- /dev/null +++ b/include/dt-bindings/power/starfive,jh7110-pmu.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Walker Chen + */ +#ifndef __DT_BINDINGS_POWER_JH7110_POWER_H__ +#define __DT_BINDINGS_POWER_JH7110_POWER_H__ + +#define JH7110_PD_SYSTOP 0 +#define JH7110_PD_CPU 1 +#define JH7110_PD_GPUA 2 +#define JH7110_PD_VDEC 3 +#define JH7110_PD_VOUT 4 +#define JH7110_PD_ISP 5 +#define JH7110_PD_VENC 6 + +#endif -- cgit v1.2.3 From 82219cfbef1805abcc050d667e71873a10963781 Mon Sep 17 00:00:00 2001 From: "Nancy.Lin" Date: Fri, 13 Jan 2023 18:44:24 +0800 Subject: dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add vdosys1 mmsys compatible for MT8195 platform. For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to 2 different power domains, different clock drivers and different mediatek-drm drivers. Signed-off-by: Nancy.Lin Reviewed-by: Nícolas F. R. A. Prado Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230113104434.28023-2-nancy.lin@mediatek.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 84de12709323..a17c71e761d5 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -33,6 +33,7 @@ properties: - mediatek,mt8186-mmsys - mediatek,mt8188-vdosys0 - mediatek,mt8192-mmsys + - mediatek,mt8195-vdosys1 - mediatek,mt8365-mmsys - const: syscon -- cgit v1.2.3 From 84def5abbb5252681bb5aa7e3e253c37b75ed9e7 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 26 Jan 2023 00:34:17 -0600 Subject: dt-bindings: power: Add Allwinner D1 PPU The Allwinner D1 family of SoCs contain a PPU power domain controller separate from the PRCM. It can power down the video engine and DSP, and it contains special logic for hardware-assisted CPU idle. Other recent Allwinner SoCs (e.g. TV303) have a PPU with a different set of domains. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20230126063419.15971-2-samuel@sholland.org Signed-off-by: Jernej Skrabec --- .../bindings/power/allwinner,sun20i-d1-ppu.yaml | 54 ++++++++++++++++++++++ .../dt-bindings/power/allwinner,sun20i-d1-ppu.h | 10 ++++ 2 files changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml create mode 100644 include/dt-bindings/power/allwinner,sun20i-d1-ppu.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml b/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml new file mode 100644 index 000000000000..46e2647a5d72 --- /dev/null +++ b/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/allwinner,sun20i-d1-ppu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner SoCs PPU power domain controller + +maintainers: + - Samuel Holland + +description: + D1 and related SoCs contain a power domain controller for the CPUs, GPU, and + video-related hardware. + +properties: + compatible: + enum: + - allwinner,sun20i-d1-ppu + + reg: + maxItems: 1 + + clocks: + description: Bus Clock + maxItems: 1 + + resets: + maxItems: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - resets + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + ppu: power-controller@7001000 { + compatible = "allwinner,sun20i-d1-ppu"; + reg = <0x7001000 0x1000>; + clocks = <&r_ccu CLK_BUS_R_PPU>; + resets = <&r_ccu RST_BUS_R_PPU>; + #power-domain-cells = <1>; + }; diff --git a/include/dt-bindings/power/allwinner,sun20i-d1-ppu.h b/include/dt-bindings/power/allwinner,sun20i-d1-ppu.h new file mode 100644 index 000000000000..23cfb57256d6 --- /dev/null +++ b/include/dt-bindings/power/allwinner,sun20i-d1-ppu.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_POWER_SUN20I_D1_PPU_H_ +#define _DT_BINDINGS_POWER_SUN20I_D1_PPU_H_ + +#define PD_CPU 0 +#define PD_VE 1 +#define PD_DSP 2 + +#endif /* _DT_BINDINGS_POWER_SUN20I_D1_PPU_H_ */ -- cgit v1.2.3 From 1873da264caedf6b84417ff8cb0f843659f75dac Mon Sep 17 00:00:00 2001 From: Moudy Ho Date: Wed, 18 Jan 2023 11:15:07 +0800 Subject: dt-bindings: arm: mediatek: mmsys: Add support for MT8195 VPPSYS For MT8195, VPPSYS0 and VPPSYS1 are 2 display pipes with hardware differences in power domains, clocks and subsystem counts, which should be determined by compatible names. Signed-off-by: Moudy Ho Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230118031509.29834-3-moudy.ho@mediatek.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index a17c71e761d5..d1410345ef18 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -34,6 +34,8 @@ properties: - mediatek,mt8188-vdosys0 - mediatek,mt8192-mmsys - mediatek,mt8195-vdosys1 + - mediatek,mt8195-vppsys0 + - mediatek,mt8195-vppsys1 - mediatek,mt8365-mmsys - const: syscon -- cgit v1.2.3 From 2f22aafa0d3587a60248834891b988ccf014840f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 27 Jan 2023 20:40:51 +0100 Subject: dt-bindings: phy: samsung,dp-video-phy: deprecate syscon phandle The DisplayPort phy is actually part of the Power Management Unit system controller, thus it should be its child, instead of sibling node with syscon phandle. Acked-by: Vinod Koul Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20230127194057.186458-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/phy/samsung,dp-video-phy.yaml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/samsung,dp-video-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,dp-video-phy.yaml index b03b2f00cc5b..3bee3f8733f7 100644 --- a/Documentation/devicetree/bindings/phy/samsung,dp-video-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,dp-video-phy.yaml @@ -22,13 +22,13 @@ properties: samsung,pmu-syscon: $ref: /schemas/types.yaml#/definitions/phandle + deprecated: true description: - Phandle to PMU system controller interface. + Phandle to PMU system controller interface (if not a child of PMU). required: - compatible - "#phy-cells" - - samsung,pmu-syscon additionalProperties: false @@ -36,6 +36,5 @@ examples: - | phy { compatible = "samsung,exynos5420-dp-video-phy"; - samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <0>; }; -- cgit v1.2.3 From e179fc990129118c40267e923b6a35a59c47d588 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 27 Jan 2023 20:40:52 +0100 Subject: dt-bindings: phy: samsung,mipi-video-phy: deprecate syscon phandle The MIPI phy is actually part of the Power Management Unit system controller, thus it should be its child, instead of sibling node with syscon phandle. Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20230127194057.186458-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/phy/samsung,mipi-video-phy.yaml | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml index 415440aaad89..b2250e4a6b1b 100644 --- a/Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml @@ -35,15 +35,18 @@ properties: syscon: $ref: /schemas/types.yaml#/definitions/phandle + deprecated: true description: Phandle to PMU system controller interface, valid only for - samsung,s5pv210-mipi-video-phy and samsung,exynos5420-mipi-video-phy. + samsung,s5pv210-mipi-video-phy and samsung,exynos5420-mipi-video-phy (if + not a child of PMU). samsung,pmu-syscon: $ref: /schemas/types.yaml#/definitions/phandle + deprecated: true description: Phandle to PMU system controller interface, valid for - samsung,exynos5433-mipi-video-phy. + samsung,exynos5433-mipi-video-phy (if not a child of PMU). samsung,disp-sysreg: $ref: /schemas/types.yaml#/definitions/phandle @@ -81,13 +84,10 @@ allOf: samsung,disp-sysreg: false samsung,cam0-sysreg: false samsung,cam1-sysreg: false - required: - - syscon else: properties: syscon: false required: - - samsung,pmu-syscon - samsung,disp-sysreg - samsung,cam0-sysreg - samsung,cam1-sysreg @@ -99,7 +99,6 @@ examples: phy { compatible = "samsung,exynos5433-mipi-video-phy"; #phy-cells = <1>; - samsung,pmu-syscon = <&pmu_system_controller>; samsung,cam0-sysreg = <&syscon_cam0>; samsung,cam1-sysreg = <&syscon_cam1>; samsung,disp-sysreg = <&syscon_disp>; -- cgit v1.2.3 From 68d868adc121f68edde0f4c0e16923103b868945 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 31 Jan 2023 20:18:50 -0800 Subject: dt-bindings: soc: qcom: Introduce PMIC GLINK binding The PMIC GLINK service, running on a coprocessor on some modern Qualcomm platforms and implement USB Type-C handling and battery management. This binding describes the component in the OS used to communicate with the firmware and connect it's resources to those described in the Devicetree, particularly the USB Type-C controllers relationship with USB and DisplayPort components. Signed-off-by: Bjorn Andersson Tested-by: Konrad Dybcio # SM8350 PDX215 Signed-off-by: Bjorn Andersson Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230201041853.1934355-2-quic_bjorande@quicinc.com --- .../bindings/soc/qcom/qcom,pmic-glink.yaml | 95 ++++++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml new file mode 100644 index 000000000000..cf863683c21a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,pmic-glink.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PMIC GLINK firmware interface for battery management, USB + Type-C and other things. + +maintainers: + - Bjorn Andersson + +description: + The PMIC GLINK service, running on a coprocessor on some modern Qualcomm + platforms and implement USB Type-C handling and battery management. This + binding describes the component in the OS used to communicate with the + firmware and connect it's resources to those described in the Devicetree, + particularly the USB Type-C controllers relationship with USB and DisplayPort + components. + +properties: + compatible: + items: + - enum: + - qcom,sc8180x-pmic-glink + - qcom,sc8280xp-pmic-glink + - qcom,sm8350-pmic-glink + - const: qcom,pmic-glink + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + '^connector@\d$': + $ref: /schemas/connector/usb-connector.yaml# + + properties: + reg: true + + required: + - reg + + unevaluatedProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + - |+ + pmic-glink { + compatible = "qcom,sc8280xp-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&usb_role>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&ss_phy_out>; + }; + }; + + port@2 { + reg = <2>; + endpoint { + remote-endpoint = <&sbu_mux>; + }; + }; + }; + }; + }; +... + -- cgit v1.2.3 From 22b0e764c1b41ee75d7ee76287746a65727aa78a Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Thu, 12 Jan 2023 12:36:53 -0800 Subject: dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes Update the bindings to allow for generic regulator nodes instead of device-specific node names. Signed-off-by: Melody Olvera Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230112203653.23139-1-quic_molvera@quicinc.com --- Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml index b246500d3d5d..a4046ba60846 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml @@ -112,8 +112,9 @@ properties: $ref: /schemas/power/qcom,rpmpd.yaml# patternProperties: - '-regulators$': + '^regulators(-[0-9])?$': $ref: /schemas/regulator/qcom,rpmh-regulator.yaml# + unevaluatedProperties: false required: - compatible -- cgit v1.2.3 From 27d71e8063d99b4429832bc52de171ace6b1e562 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Fri, 27 Jan 2023 20:21:39 +0100 Subject: dt-bindings: firmware: qcom,scm: add qcom,scm-sa8775p compatible Add a compatible for the sa8775p platform's Secure Channel Manager firmware interface. Signed-off-by: Bartosz Golaszewski Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230127192139.299228-1-brgl@bgdev.pl --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 4193492ba73e..fd3c787e44a8 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -39,6 +39,7 @@ properties: - qcom,scm-msm8996 - qcom,scm-msm8998 - qcom,scm-qdu1000 + - qcom,scm-sa8775p - qcom,scm-sc7180 - qcom,scm-sc7280 - qcom,scm-sc8280xp -- cgit v1.2.3 From b9fd335389776b7bfd7db4dfdd57c1bfe29c54e1 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 7 Feb 2023 14:46:46 +0100 Subject: dt-bindings: firmware: document Qualcomm SM8550 SCM Document the compatible for Qualcomm SM8550 SCM. Signed-off-by: Abel Vesa Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230207-topic-sm8550-upstream-scm-bindings-v2-1-ca12bd33fa1c@linaro.org --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index fd3c787e44a8..a66e99812b1f 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -55,6 +55,7 @@ properties: - qcom,scm-sm8250 - qcom,scm-sm8350 - qcom,scm-sm8450 + - qcom,scm-sm8550 - qcom,scm-qcs404 - const: qcom,scm @@ -166,6 +167,7 @@ allOf: contains: enum: - qcom,scm-sm8450 + - qcom,scm-sm8550 then: properties: interconnects: false @@ -178,6 +180,7 @@ allOf: contains: enum: - qcom,scm-sm8450 + - qcom,scm-sm8550 then: properties: interrupts: false -- cgit v1.2.3