From b678676b7a0ab65ad5b4278505d6bcf706e53230 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 3 Mar 2026 16:33:12 +0000 Subject: dt-bindings: gpio: mpfs-gpio: permit resets Both CoreGPIO and the hardened versions of it on mpfs and pic64gx have a reset pin. For the former, usually this is wired to a common fabric reset not managed by software and for the latter two the platform firmware takes them out of reset on first-party boards (or those using modified versions of the vendor firmware), but not all boards may take this approach. Permit providing a reset in devicetree for Linux, or other devicetree-consuming software, to use. Signed-off-by: Conor Dooley Link: https://patch.msgid.link/20260303-irate-hungry-b54cda817e42@spud Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml index 184432d24ea1..eaa254a46806 100644 --- a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml @@ -33,6 +33,9 @@ properties: clocks: maxItems: 1 + resets: + maxItems: 1 + "#gpio-cells": const: 2 -- cgit v1.2.3 From c452588f3cb6b5c2bb6448fc347465aa2174cd7a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 12 Feb 2026 12:09:06 +0100 Subject: dt-bindings: gpio: gpio-delay: Use Alexander's email Group/anonymous mailboxes are not accepted for bindings maintainers, so switch from such linux @TQ mailbox to Alexander's email. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alexander Stein Link: https://patch.msgid.link/20260212110905.52842-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/gpio/gpio-delay.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-delay.yaml b/Documentation/devicetree/bindings/gpio/gpio-delay.yaml index 1cebc4058e27..b99ceff6c5f6 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-delay.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-delay.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: GPIO delay controller maintainers: - - Alexander Stein + - Alexander Stein description: | This binding describes an electrical setup where setting an GPIO output -- cgit v1.2.3 From 49944d6ab7eb951f2aefee69341c623e13434863 Mon Sep 17 00:00:00 2001 From: Rustam Adilov Date: Thu, 5 Mar 2026 21:11:05 +0500 Subject: dt-bindings: gpio: realtek-otto: add rtl9607 compatible Add the "realtek,rtl9607-gpio" compatible for GPIO nodes on the RTL9607C SoC series. Signed-off-by: Rustam Adilov Reviewed-by: Linus Walleij Reviewed-by: Sander Vanheule Link: https://patch.msgid.link/20260305161106.15999-2-adilov@disroot.org Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml index 728099c65824..b18f8f0ca0ae 100644 --- a/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml @@ -30,6 +30,7 @@ properties: - realtek,rtl8390-gpio - realtek,rtl9300-gpio - realtek,rtl9310-gpio + - realtek,rtl9607-gpio - const: realtek,otto-gpio reg: true -- cgit v1.2.3 From ececb46fc947705f22cc8c1f9182224e7ec4bb97 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 18 Mar 2026 11:04:32 +0000 Subject: dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation The microchip,mpfs-gpio binding suffered greatly due to being written with a narrow minded view of the controller, and the interrupt bits ended up incorrect. It was mistakenly assumed that the interrupt configuration was set by platform firmware, based on the FPGA configuration, and that the GPIO DT nodes were the only way to really communicate interrupt configuration to software. Instead, the mux should be a device in its own right, and the GPIO controllers should be connected to it, rather than to the PLIC. Now that a binding exists for that mux, try to fix the misconceptions in the GPIO controller binding. Firstly, it's not possible for this controller to have fewer than 14 GPIOs, and thus 14 interrupts also. There are three controllers, with 14, 24 & 32 GPIOs each. The fabric core, CoreGPIO, can of course have a customisable number of GPIOs. The example is wacky too - it follows from the incorrect understanding that the GPIO controllers are connected to the PLIC directly. They are not however, with a mux sitting in between. Update the example to use the mux as a parent, and the interrupt numbers at the mux for GPIO2 as the example - rather than the strange looking, repeated <53>. Signed-off-by: Conor Dooley Acked-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Link: https://patch.msgid.link/20260318-fondly-tradition-90b8241f0cc8@spud Signed-off-by: Bartosz Golaszewski --- .../bindings/gpio/microchip,mpfs-gpio.yaml | 24 ++++++++++++++-------- 1 file changed, 15 insertions(+), 9 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml index eaa254a46806..6a0c5341d8a4 100644 --- a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml @@ -65,6 +65,11 @@ allOf: contains: const: microchip,mpfs-gpio then: + properties: + ngpios: + enum: [14, 24, 32] + interrupts: + minItems: 14 required: - interrupts - "#interrupt-cells" @@ -85,18 +90,19 @@ examples: compatible = "microchip,mpfs-gpio"; reg = <0x20122000 0x1000>; clocks = <&clkcfg 25>; - interrupt-parent = <&plic>; + interrupt-parent = <&irqmux>; gpio-controller; #gpio-cells = <2>; + ngpios = <32>; interrupt-controller; #interrupt-cells = <1>; - interrupts = <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>; + interrupts = <64>, <65>, <66>, <67>, + <68>, <69>, <70>, <71>, + <72>, <73>, <74>, <75>, + <76>, <77>, <78>, <79>, + <80>, <81>, <82>, <83>, + <84>, <85>, <86>, <87>, + <88>, <89>, <90>, <91>, + <92>, <93>, <94>, <95>; }; ... -- cgit v1.2.3 From 05a8a80efaacc42013d78fc3fe41159b7be4333c Mon Sep 17 00:00:00 2001 From: AKASHI Takahiro Date: Mon, 23 Mar 2026 22:01:42 +0300 Subject: gpio: dt-bindings: Add GPIO on top of generic pin control Traditionally, firmware will provide a GPIO interface or a pin control interface. However, the SCMI protocol provides a generic pin control interface and the GPIO support is built on top of that using the normal pin control interfaces. Potentially, other firmware will adopt a similar generic approach in the future. Document how to configure the GPIO device. Signed-off-by: AKASHI Takahiro Signed-off-by: Dan Carpenter Reviewed-by: Linus Walleij Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/pin-control-gpio.yaml | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml b/Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml new file mode 100644 index 000000000000..a05cd339253a --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/pin-control-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pin control based generic GPIO controller + +description: + The pin control-based GPIO will facilitate a pin controller's ability + to drive electric lines high/low and other generic properties of a + pin controller to perform general-purpose one-bit binary I/O. + +maintainers: + - Dan Carpenter + +properties: + compatible: + const: scmi-pinctrl-gpio + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-line-names: true + + gpio-ranges: true + + ngpios: true + +patternProperties: + "^.+-hog(-[0-9]+)?$": + type: object + + required: + - gpio-hog + +required: + - compatible + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - ngpios + +additionalProperties: false + +examples: + - | + gpio { + compatible = "scmi-pinctrl-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <4>; + gpio-line-names = "gpio_5_17", "gpio_5_20", "gpio_5_22", "gpio_2_1"; + gpio-ranges = <&scmi_pinctrl 0 30 4>; + pinctrl-names = "default"; + pinctrl-0 = <&keys_pins>; + }; -- cgit v1.2.3 From 5bcd451286176202f4ba84b89fd98c7ea74f33a2 Mon Sep 17 00:00:00 2001 From: Shi Hao Date: Wed, 8 Apr 2026 15:03:13 +0530 Subject: dt-bindings: gpio: cavium,thunder-8890: Remove DT binding Remove the cavium,thunder-8890 GPIO binding as there are no active use cases. The binding is unused as the corresponding kernel driver binds via PCI and not the compatible. Signed-off-by: Shi Hao Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260408093313.17025-1-i.shihao.999@gmail.com [Bartosz: tweaked the commit message] Signed-off-by: Bartosz Golaszewski --- .../devicetree/bindings/gpio/gpio-thunderx.txt | 27 ---------------------- 1 file changed, 27 deletions(-) delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-thunderx.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt deleted file mode 100644 index 3f883ae29d11..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt +++ /dev/null @@ -1,27 +0,0 @@ -Cavium ThunderX/OCTEON-TX GPIO controller bindings - -Required Properties: -- reg: The controller bus address. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Must be 2. - - First cell is the GPIO pin number relative to the controller. - - Second cell is a standard generic flag bitfield as described in gpio.txt. - -Optional Properties: -- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Must be present and have value of 2 if - "interrupt-controller" is present. - - First cell is the GPIO pin number relative to the controller. - - Second cell is triggering flags as defined in interrupts.txt. - -Example: - -gpio_6_0: gpio@6,0 { - compatible = "cavium,thunder-8890-gpio"; - reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */ - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -}; -- cgit v1.2.3