From 22a9554e548424a15b744273d4509c884c9f14b1 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 19 Feb 2023 13:14:18 +0100 Subject: arm64: dts: marvell: mochabin: enlarge PCI memory window Armada 7040 uses a rather small 15MB memory window for every PCI adapter, however this is not sufficient for Qualcomm QCA6390 802.11ax cards that are shipped along with the OpenWrt WLAN model of MOCHAbin as ath11k requires at least 16MB of memory. So, similar to what MACCHIATOBin has been doing for years, lets move to using the second PCIe 2 memory window and expand it to 128MB to make it future proof. Signed-off-by: Robert Marko Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts index 7ca71f2d7afb..39ce6e25a8ef 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts @@ -455,4 +455,5 @@ phys = <&cp0_comphy5 2>; phy-names = "cp0-pcie2-x1-phy"; reset-gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>; + ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x8000000>; }; -- cgit v1.2.3 From 4b6a412ee561ce8d530b6a0dfcf05d2ae7691fd9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 21:13:13 +0100 Subject: arm64: dts: marvell: align thermal node names with bindings Bindings expect thermal node names to end with '-thermal': armada-8040-db.dtb: thermal-zones: 'ap-thermal-cpu0', ... do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 10 +++++----- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi index 4e6d29ad32eb..2c920e22cec2 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi @@ -317,7 +317,7 @@ * first one that will have a critical trip point will be chosen. */ thermal-zones { - ap_thermal_ic: ap-thermal-ic { + ap_thermal_ic: ap-ic-thermal { polling-delay-passive = <0>; /* Interrupt driven */ polling-delay = <0>; /* Interrupt driven */ @@ -334,7 +334,7 @@ cooling-maps { }; }; - ap_thermal_cpu0: ap-thermal-cpu0 { + ap_thermal_cpu0: ap-cpu0-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -367,7 +367,7 @@ }; }; - ap_thermal_cpu1: ap-thermal-cpu1 { + ap_thermal_cpu1: ap-cpu1-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -400,7 +400,7 @@ }; }; - ap_thermal_cpu2: ap-thermal-cpu2 { + ap_thermal_cpu2: ap-cpu2-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -433,7 +433,7 @@ }; }; - ap_thermal_cpu3: ap-thermal-cpu3 { + ap_thermal_cpu3: ap-cpu3-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 7d0043824f2a..0cc9ee9871e7 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -25,7 +25,7 @@ * The cooling maps are empty as there are no cooling devices. */ thermal-zones { - CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) { + CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) { polling-delay-passive = <0>; /* Interrupt driven */ polling-delay = <0>; /* Interrupt driven */ -- cgit v1.2.3 From 6d5a6740f6df4c41a96d57d542207a7d5cab0393 Mon Sep 17 00:00:00 2001 From: Enrico Mioso Date: Thu, 2 Feb 2023 10:37:06 +0100 Subject: arm64: dts: marvell: add DTS for GL.iNet GL-MV1000 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The GL-MV1000 (Brume) is a small form-factor gateway router. It is based on the Marvell Armada 88F3720 SOC (1GHz), has 3 gigabit ethernet ports, 1 GB RAM, 16M SPI flash, 8GB eMMC and an uSD slot, as well as an USB 2.0 type A and an USB 3.0 type C port. Signed-off-by: Enrico Mioso CC: Pali Reviewed-by: Pali Rohár Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/Makefile | 1 + .../boot/dts/marvell/armada-3720-gl-mv1000.dts | 239 +++++++++++++++++++++ 2 files changed, 240 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 058237681fe5..79ac09b58a89 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-emmc.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-ultra.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7-emmc.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-gl-mv1000.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts new file mode 100644 index 000000000000..b1b45b4fa9d4 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) + +/dts-v1/; +#include +#include +#include "armada-372x.dtsi" + +/ { + model = "GL.iNet GL-MV1000"; + compatible = "glinet,gl-mv1000", "marvell,armada3720"; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; + + vcc_sd_reg1: regulator { + compatible = "regulator-gpio"; + regulator-name = "vcc_sd1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + gpios-states = <0>; + states = <1800000 0x1 + 3300000 0x0>; + enable-active-high; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; + }; + + switch { + label = "switch"; + linux,code = ; + gpios = <&gpiosb 22 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + vpn { + label = "green:vpn"; + gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; + }; + + wan { + label = "green:wan"; + gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; + }; + + led_power: power { + label = "green:power"; + gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <104000000>; + m25p,fast-read; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "firmware"; + reg = <0 0xf0000>; + }; + + partition@f0000 { + label = "u-boot-env"; + reg = <0xf0000 0x8000>; + }; + + factory: partition@f8000 { + label = "factory"; + reg = <0xf8000 0x8000>; + read-only; + }; + + partition@100000 { + label = "dtb"; + reg = <0x100000 0x10000>; + read-only; + }; + + partition@110000 { + label = "rescue"; + reg = <0x110000 0x1000000>; + }; + }; + }; +}; + +&sdhci1 { + wp-inverted; + bus-width = <4>; + cd-gpios = <&gpionb 17 GPIO_ACTIVE_LOW>; + marvell,pad-type = "sd"; + no-1-8-v; + vqmmc-supply = <&vcc_sd_reg1>; + status = "okay"; +}; + +&sdhci0 { + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + non-removable; + no-sd; + no-sdio; + marvell,pad-type = "fixed-1-8v"; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&mdio { + switch0: switch0@1 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dsa,member = <0 0>; + + ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <ð0>; + }; + + port@1 { + reg = <1>; + label = "wan"; + phy-handle = <&switch0phy0>; + }; + + port@2 { + reg = <2>; + label = "lan0"; + phy-handle = <&switch0phy1>; + + nvmem-cells = <&macaddr_factory_6>; + nvmem-cell-names = "mac-address"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + phy-handle = <&switch0phy2>; + + nvmem-cells = <&macaddr_factory_6>; + nvmem-cell-names = "mac-address"; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch0phy0: switch0phy0@11 { + reg = <0x11>; + }; + switch0phy1: switch0phy1@12 { + reg = <0x12>; + }; + switch0phy2: switch0phy2@13 { + reg = <0x13>; + }; + }; + }; +}; + +ð0 { + nvmem-cells = <&macaddr_factory_0>; + nvmem-cell-names = "mac-address"; + phy-mode = "rgmii-id"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&factory { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_factory_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; -- cgit v1.2.3 From 218669c662e3a38fdbd7e0ce56a20784da29546e Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Fri, 7 Apr 2023 17:18:39 +0200 Subject: ARM64: dts: marvell: cn9310: Add missing phy-mode The DSA framework has got more picky about always having a phy-mode for the CPU port. The SoC Ethernet is being configured to 10gbase-r. Set the switch phy-mode based on this. Additionally, the SoC Ethernet is using in-band signalling to determine the link speed, so add same parameter to the switch. Additionally, the cpu label has never actually been used in the binding, so remove it. Signed-off-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index 8e4ec243fb8f..32cfb3e2efc3 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -282,8 +282,9 @@ port@a { reg = <10>; - label = "cpu"; ethernet = <&cp0_eth0>; + phy-mode = "10gbase-r"; + managed = "in-band-status"; }; }; -- cgit v1.2.3