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path: root/drivers/gpu/drm/i915/intel_pm.c
AgeCommit message (Expand)Author
2014-10-21Merge branch 'drm-intel-next-fixes' into drm-intel-nextDaniel Vetter
2014-10-03drm/i915: s/pm._irqs_disabled/pm.irqs_enabled/Daniel Vetter
2014-10-01drm/i915: Extract intel_runtime_pm.cDaniel Vetter
2014-09-30Merge branch 'topic/skl-stage1' into drm-intel-next-queuedDaniel Vetter
2014-09-29drm/i915: Don't spam dmesg with rps messages on vlv/chvVille Syrjälä
2014-09-29Revert "drm/i915/bdw: BDW Software Turbo"Daniel Vetter
2014-09-29drm/i915: Minimize the huge amount of unecessary fbc sw cache clean.Rodrigo Vivi
2014-09-24drm/i915/skl: Move gen9 pm initialization into its own branchDamien Lespiau
2014-09-24drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:sklDamien Lespiau
2014-09-24drm/i915/skl: Implement Wa4x4STCOptimizationDisable:sklDamien Lespiau
2014-09-24drm/i915/skl: Implement WaDisableSDEUnitClockGating:sklDamien Lespiau
2014-09-24drm/i915/skl: Restore pipe B/C interruptsSatheeshakrishna M
2014-09-24drm/i915/skl: Provide a placeholder for init_clock_gating()Damien Lespiau
2014-09-23drm/i915: add SW tracking to FBC enablingPaulo Zanoni
2014-09-23drm/i915: extract intel_init_fbc()Paulo Zanoni
2014-09-19drm/i915: Avoid reading fbc registers in vain when fbc was never enabled.Rodrigo Vivi
2014-09-19drm/i915: Only flush fbc on sw when fbc is enabled.Rodrigo Vivi
2014-09-19drm/i915: Limit the watermark to at least 8 entries on gen2/3Ville Syrjälä
2014-09-04drm/i915: Reset power sequencer pipe tracking when disp2d is offVille Syrjälä
2014-09-03drm/i915: Rename global latency_ns variableChris Wilson
2014-09-03drm/i915: Disable trickle feed for gen2/3Ville Syrjälä
2014-09-03drm/i915: Fix gen2 planes B and C max watermark valueVille Syrjälä
2014-09-03drm/i915: Init some CHV workarounds via LRIs in ring->init_context()Ville Syrjälä
2014-09-03drm/i915: Warn about odd rps values on CHVVille Syrjälä
2014-09-03drm/i915/bdw: BDW Software TurboDaisy Sun
2014-09-03drm/i915: Populate mem_freq in init_gt_powerwave()Ville Syrjälä
2014-09-03drm/i915/bdw: Apply workarounds in render ring init functionArun Siluvery
2014-09-03drm/i915: FBC flush nuke for BDWRodrigo Vivi
2014-09-03drm/i915: rename gen8_init_clock_gating to broadwell_init_clock_gatingPaulo Zanoni
2014-09-03drm/i915: call lpt_init_clock_gating on BDW tooPaulo Zanoni
2014-09-03drm/i915: Bring UP Power Wells before disabling RC6.Deepak S
2014-09-03drm/i915: Use dev_priv as first argument of for_each_pipe()Damien Lespiau
2014-09-03drm/i915: Add 180 degree primary plane rotation supportSonika Jindal
2014-09-03Merge tag 'drm-intel-next-2014-09-01' of git://anongit.freedesktop.org/drm-in...Dave Airlie
2014-08-26Merge tag 'drm-intel-next-2014-08-08' of git://anongit.freedesktop.org/drm-in...Dave Airlie
2014-08-11drm/i915: Remove set but unused 'gt_perf_status'Damien Lespiau
2014-08-08Merge tag 'drm-intel-fixes-2014-08-08' of git://anongit.freedesktop.org/drm-i...Linus Torvalds
2014-08-08drm/i915: Add sprite watermark programming for VLV and CHVGajanan Bhat
2014-08-08drm/i915: Round-up clock and limit drain latencyGajanan Bhat
2014-08-08drm/i915: Generalize drain latency computationGajanan Bhat
2014-08-08drm/i915: Polish the chv cmnlane resrt macrosVille Syrjälä
2014-08-08drm/i915: Hack to tie both common lanes together on chvVille Syrjälä
2014-08-08drm/i915: Add cherryview_update_wm()Ville Syrjälä
2014-08-08drm/i915: Update DDL only for current CRTCGajanan Bhat
2014-08-08drm/i915: Parametrize VLV_DDL registersVille Syrjälä
2014-08-08drm/i915: Fill out the FWx watermark register definesVille Syrjälä
2014-08-08drm/i915: Introduce FBC False Color for debug purposes.Rodrigo Vivi
2014-08-08drm/i915: Split a few long debug printsVille Syrjälä
2014-08-08drm/i915: Add chv port D TX wellsVille Syrjälä
2014-08-08drm/i915: Add chv port B and C TX wellsVille Syrjälä