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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)Author
2021-01-07Merge tag 'drm-intel-next-2021-01-04' of git://anongit.freedesktop.org/drm/dr...Daniel Vetter
2020-12-03drm/i915: Add VRR_CTL_LINE_COUNT field to VRR_CTL register defManasi Navare
2020-12-03Merge tag 'drm-intel-next-queued-2020-11-27' of git://anongit.freedesktop.org...Dave Airlie
2020-12-02drm/i915: remove last traces of I915_READ(), I915_WRITE() and POSTING_READ()Jani Nikula
2020-11-19drm/i915/perf: workaround register corruption in OATAILPTRLionel Landwerlin
2020-11-13Merge tag 'drm-intel-gt-next-2020-11-12-1' of git://anongit.freedesktop.org/d...Dave Airlie
2020-11-11drm/i915/tgl: Fix Media power gate sequence.Rodrigo Vivi
2020-11-09drm/i915/dg1: map/unmap pll clocksLucas De Marchi
2020-10-30drm/i915: Enable hpd logic only for ports that are presentVille Syrjälä
2020-10-30drm/i915: Remove per-platform IIR HPD maskingVille Syrjälä
2020-10-30drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bitsVille Syrjälä
2020-10-30drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC,TBT}_HOTPLUG()Ville Syrjälä
2020-10-30drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bitsVille Syrjälä
2020-10-30drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()Ville Syrjälä
2020-10-30drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pinVille Syrjälä
2020-10-30drm/i915: s/PORT_TC/TC_PORT_/Ville Syrjälä
2020-10-29drm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registersVille Syrjälä
2020-10-23drm/i915/dg1: invert HPD pinsClinton A Taylor
2020-10-23drm/i915/dg1: add hpd interrupt handlingLucas De Marchi
2020-10-21drm/i915: Introduce scaling filter related registers and bit fieldsPankaj Bharadiya
2020-10-20drm/i915: Sort the mess around ICP TC hotplugs regsVille Syrjälä
2020-10-19drm/i915/display: Program DBUF_CTL tracker state serviceJosé Roberto de Souza
2020-10-15drm/i915/dg1: Update DMC_DEBUG registerAnshuman Gupta
2020-10-15drm/i915/dg1: Add initial DG1 workaroundsStuart Summers
2020-10-15drm/i915/dg1: Enable DPLL for DG1Lucas De Marchi
2020-10-15drm/i915/dg1: Add DPLL macros for DG1Aditya Swarup
2020-10-09drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GTMatt Roper
2020-10-06drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programmingImre Deak
2020-10-05drm/i915/dg1: Wait for pcode/uncore handshake at startupMatt Roper
2020-10-01drm/i915: Implement display WA #1142:kbl,cfl,cmlVille Syrjälä
2020-09-28drm/i915: Relocate CHV CGM gamma masksVille Syrjälä
2020-09-28drm/i915: Add support for async flips in I915Karthik B S
2020-09-15drm/i915: Nuke the redundant TC/TBT HPD bit definesVille Syrjälä
2020-09-11drm/i915: Nuke dpio_phy_iosf_port[]Ville Syrjälä
2020-08-26drm/i915/gt: Implement WA_1406941453Clint Taylor
2020-08-17drm/i915/display: Implement WA 1408330847José Roberto de Souza
2020-08-17drm/i915/tgl: Set subplatformsJosé Roberto de Souza
2020-08-17drm/i915/tgl: Fix TC-cold block/unblock sequenceImre Deak
2020-08-17Revert "drm/i915/rkl: Add Wa_14011224835 for PHY B initialization"Matt Roper
2020-08-17drm/i915: Implement WA 14011294188José Roberto de Souza
2020-08-17drm/i915/rkl: Add Wa_14011224835 for PHY B initializationMatt Roper
2020-08-17drm/i915/rkl: Handle HTIMatt Roper
2020-08-17drm/i915/rkl: Add DPLL4 supportMatt Roper
2020-08-17drm/i915/rkl: Handle new DPCLKA_CFGCR0 layoutMatt Roper
2020-08-17drm/i915/display: Implement HOBLJosé Roberto de Souza
2020-07-14drm/i915/dg1: add support for the master unit interruptLucas De Marchi
2020-07-07drm/i915/display: Implement new combo phy initialization stepJosé Roberto de Souza
2020-07-06drm/i915: Fix spelling mistake in i915_reg.hFlavio Suligoi
2020-07-03drm/i915/fbc: Allow FBC to recompress after a 3D workload on i85x/i865Ville Syrjälä
2020-06-30drm/i915: Add PSR2 selective fetch registersJosé Roberto de Souza