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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)Author
2019-01-29drm/i915/icl: use tc_port in MG_PLL macrosLucas De Marchi
2019-01-25drm/i915/tv: Generate better pipe timings for TV encoderVille Syrjälä
2019-01-22drm/i915: Add PSR2 selective update status registers and bits definitionsJosé Roberto de Souza
2019-01-18drm/i915/dp: remove PANEL_POWER_OFF macro and its useJani Nikula
2019-01-17drm/i915: small isolated c99 types to kernel types switchJani Nikula
2019-01-15drm/i915/cnl: Fix CNL macros for Voltage Swing programmingAditya Swarup
2019-01-02drm/i915: always use INTEL_INFO() to access device infoJani Nikula
2019-01-02drm/i915/reg: abstract display_mmio_offset accessJani Nikula
2018-12-18drm/i915/icl: combo port vswing programming changes per BSPECClint Taylor
2018-12-13drm/i915/icl: Mind the SFC units when resetting VD or VEBox enginesOscar Mateo
2018-12-03drm/i915/icl: Define Panel power ctrl registerMadhav Chauhan
2018-12-03drm/i915/icl: Define missing bitfield for shortplug regMadhav Chauhan
2018-11-29i915/dp/fec: Configure the Forward Error Correction bits.Anusha Srivatsa
2018-11-29drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPsManasi Navare
2018-11-21drm/i915: Make CHICKEN_TRANS reg not depend on enum valueImre Deak
2018-11-21drm/i915: Make EDP PSR flags not depend on enum valuesImre Deak
2018-11-19Revert "drm/i915/perf: add a parameter to control the size of OA buffer"Joonas Lahtinen
2018-11-14drm/i915: Deduplicate register definition for GAMW_ECO_DEV_RW_IAMika Kuoppala
2018-11-13drm/i915: rename CNP_RAWCLK_FRAC to CNP_RAWCLK_DENPaulo Zanoni
2018-11-09drm/i915: Polish the skl+ plane keyval/msk/max register setupVille Syrjälä
2018-11-06drm/i915/icl: Define Plane Input CSC Coefficient RegistersUma Shankar
2018-11-02drm/i915/fia: FIA registers offset implementation.Anusha Srivatsa
2018-11-02drm/i915: also group device info array helper macros with othersJani Nikula
2018-11-02drm/i915: reorder and reindent the register choosing helper wrappersJani Nikula
2018-11-02drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE()Jani Nikula
2018-11-02drm/i915: remove palette_offsets from device info in favor of _PICK()Jani Nikula
2018-11-01drm/i915/icl: Fix DSS_CTL register namesAnusha Srivatsa
2018-11-01drm/i915/icl: WaAllowUMDToModifySamplerModeOscar Mateo
2018-11-01drm/i915/icl: Add WaEnable32PlaneModeRadhakrishna Sripada
2018-11-01drm/i915/icl: Add DSS_CTL RegistersAnusha Srivatsa
2018-11-01drm/i915/icl: Add DSI packet payload/header registersMadhav Chauhan
2018-10-31drm/i915/icl: Fix the macros for DFLEXDPMLE register bitsManasi Navare
2018-10-31drm/i915/dsc: Add slice_row_per_frame in DSC PPS programmingAnusha Srivatsa
2018-10-31drm/i915/icl: Define DSI timeout registersMadhav Chauhan
2018-10-29drm/i915: Move VIDEO_DIP_CTL definitions to their right place.Dhinakaran Pandiyan
2018-10-29drm/i915: Fix VIDEO_DIP_CTL bit shiftsDhinakaran Pandiyan
2018-10-29drm/i915: Define Intel HDCP2.2 registersRamalingam C
2018-10-24drm/i915/gen11: Program the Y and UV plane for planar mode correctly, v3.Maarten Lankhorst
2018-10-24drm/i915/gen11: Program the chroma upsampler for HDR planes.Maarten Lankhorst
2018-10-24drm/i915/gen11: Program the scalers correctly for planar formats, v3.Maarten Lankhorst
2018-10-23drm/i915/perf: add a parameter to control the size of OA bufferLionel Landwerlin
2018-10-22drm/i915/icl: Define DSI panel programming registersMadhav Chauhan
2018-10-22drm/i915/icl: Define TRANS_CONF register for DSIMadhav Chauhan
2018-10-22drm/i915/icl: Define DSI transcoder timing registersMadhav Chauhan
2018-10-22drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registersMadhav Chauhan
2018-10-22drm/i915/icl: Define TRANS_DSI_FUNC_CONF registerMadhav Chauhan
2018-10-22drm/i915/icl: Add macros for MMIO of DSI transcoder registersMadhav Chauhan
2018-10-16drm/i915/icl: Fix DDI/TC port clk_off bitsMahesh Kumar
2018-10-16drm/i915/icl: Introduce new macros to get combophy registersLucas De Marchi
2018-10-16drm/i915/icl: Combine all port/combophy macros at one placeMahesh Kumar