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path: root/drivers/cxl
AgeCommit message (Expand)Author
2024-01-24cxl/region：Fix overflow issue in alloc_hpa()Quanquan Cao
2024-01-22cxl/pci: Skip irq features if MSI/MSI-X are not supportedIra Weiny
2024-01-12cxl/core: use sysfs_emit() for attr's _show()Shiyang Ruan
2024-01-09Merge branch 'for-6.8/cxl-cper' into for-6.8/cxlDan Williams
2024-01-09cxl/pci: Register for and process CPER eventsIra Weiny
2024-01-09cxl/events: Create a CXL event unionIra Weiny
2024-01-09cxl/events: Separate UUID from event structuresIra Weiny
2024-01-09cxl/events: Remove passing a UUID to known event tracesIra Weiny
2024-01-09cxl/events: Create common event UUID definesIra Weiny
2024-01-05Merge branch 'for-6.7/cxl' into for-6.8/cxlDan Williams
2024-01-05Merge branch 'for-6.8/cxl-misc' into for-6.8/cxlDan Williams
2024-01-05Merge branch 'for-6.8/cxl-cdat' into for-6.8/cxlDan Williams
2024-01-05cxl/events: Promote CXL event structures to a core headerIra Weiny
2024-01-05cxl: Refactor to use __free() for cxl_root allocation in cxl_endpoint_port_pr...Dave Jiang
2024-01-05cxl: Refactor to use __free() for cxl_root allocation in cxl_find_nvdimm_brid...Dave Jiang
2024-01-05cxl: Fix device reference leak in cxl_port_perf_data_calculate()Dave Jiang
2024-01-05cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang
2024-01-05cxl: Introduce put_cxl_root() helperDave Jiang
2024-01-04cxl/port: Fix missing target list lockDan Williams
2024-01-04cxl/port: Fix decoder initialization when nr_targets > interleave_waysHuang Ying
2024-01-03cxl/region: fix x9 interleave typoJim Harris
2024-01-03cxl/trace: Pass UUID explicitly to event tracesIra Weiny
2024-01-02Merge branch 'for-6.8/cxl-cdat' into for-6.8/cxlDan Williams
2024-01-02cxl/region: use %pap format to print resource_size_tRandy Dunlap
2023-12-24cxl/region: Add dev_dbg() detail on failure to allocate HPA spaceAlison Schofield
2023-12-22cxl: Check qos_class validity on memdev probeDave Jiang
2023-12-22cxl: Export sysfs attributes for memory device QoS classDave Jiang
2023-12-22cxl: Store QTG IDs and related info to the CXL memory device contextDave Jiang
2023-12-22cxl: Compute the entire CXL path latency and bandwidth dataDave Jiang
2023-12-22cxl: Add helper function that calculate performance data for downstream portsDave Jiang
2023-12-22cxl: Store the access coordinates for the generic portsDave Jiang
2023-12-22cxl: Calculate and store PCI link latency for the downstream portsDave Jiang
2023-12-22cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang
2023-12-22cxl: Add callback to parse the SSLBIS subtable from CDATDave Jiang
2023-12-22cxl: Add callback to parse the DSLBIS subtable from CDATDave Jiang
2023-12-22cxl: Add callback to parse the DSMAS subtables from CDATDave Jiang
2023-12-18cxl: Fix unregister_region() callback parameter assignmentDave Jiang
2023-12-14cxl/pmu: Ensure put_device on pmu devicesIra Weiny
2023-12-08cxl/cdat: Free correct buffer on checksum errorIra Weiny
2023-12-07cxl/hdm: Fix dpa translation lockingDan Williams
2023-12-07cxl: Add Support for Get TimestampDavidlohr Bueso
2023-11-29cxl/memdev: Hold region_rwsem during inject and clear poison opsAlison Schofield
2023-11-29cxl/core: Always hold region_rwsem while reading poison listsAlison Schofield
2023-11-22cxl/hdm: Fix a benign lockdep splatDave Jiang
2023-11-02cxl/pci: Change CXL AER support check to use native AERTerry Bowman
2023-10-31cxl/hdm: Remove broken error pathDan Williams
2023-10-31cxl/hdm: Fix && vs || bugDan Carpenter
2023-10-31Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams
2023-10-31Merge branch 'for-6.7/cxl' into cxl/nextDan Williams
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams