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path: root/drivers/cxl
AgeCommit message (Expand)Author
2023-01-26cxl/mem: Trace Memory Module Event RecordIra Weiny
2023-01-26cxl/mem: Trace DRAM Event RecordIra Weiny
2023-01-26cxl/mem: Trace General Media Event RecordIra Weiny
2023-01-26cxl/mem: Wire up event interruptsDavidlohr Bueso
2023-01-26cxl: fix spelling mistakesRandy Dunlap
2023-01-26cxl/mbox: Add debug messages for enabled mailbox commandsRobert Richter
2023-01-26cxl/mem: Read, trace, and clear events on driver loadIra Weiny
2023-01-25cxl/pmem: Fix nvdimm unregistration when cxl_pmem driver is absentDan Williams
2023-01-25cxl/port: Link the 'parent_dport' in portX/ and endpointX/ sysfsDan Williams
2023-01-25cxl/region: Clarify when a cxld->commit() callback is mandatoryDan Williams
2023-01-24cxl/pci: Show opcode in debug messages when sending a commandRobert Richter
2023-01-09cxl: fix cxl_report_and_clear() RAS UE addr mis-assignmentDave Jiang
2023-01-05cxl/region: Only warn about cpu_cache_invalidate_memregion() onceDavidlohr Bueso
2023-01-04cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams
2022-12-08cxl/region: Fix memdev reuse checkFan Ni
2022-12-06cxl/pci: Remove endian confusionDan Williams
2022-12-06cxl/pci: Add some type-safety to the AER trace pointsDan Williams
2022-12-06cxl/security: Drop security command ioctl uapiDan Williams
2022-12-06cxl/mbox: Add variable output size validation for internal commandsDan Williams
2022-12-06cxl/mbox: Enable cxl_mbox_send_cmd() users to validate output sizeDan Williams
2022-12-06cxl/security: Fix Get Security State output payload endian handlingDan Williams
2022-12-05cxl: update names for interleave ways conversion macrosDave Jiang
2022-12-05cxl: update names for interleave granularity conversion macrosDave Jiang
2022-12-05cxl/acpi: Warn about an invalid CHBCR in an existing CHBS entryRobert Richter
2022-12-05cxl/acpi: Fail decoder add if CXIMS for HBIG is missingAlison Schofield
2022-12-05cxl/region: Fix spelling mistake "memergion" -> "memregion"Colin Ian King
2022-12-05cxl/regs: Fix sparse warningDan Williams
2022-12-05Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams
2022-12-05Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams
2022-12-05Merge branch 'for-6.2/cxl-security' into for-6.2/cxlDan Williams
2022-12-05cxl/port: Add RCD endpoint port enumerationDan Williams
2022-12-05cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_memDan Williams
2022-12-03cxl/acpi: Support CXL XOR Interleave Math (CXIMS)Alison Schofield
2022-12-03cxl/pci: Add callback to log AER correctable errorDave Jiang
2022-12-03cxl/pci: Add (hopeful) error handling supportDan Williams
2022-12-03cxl/pci: add tracepoint events for CXL RASDave Jiang
2022-12-03cxl/pci: Find and map the RAS Capability StructureDan Williams
2022-12-03cxl/pci: Prepare for mapping RAS Capability StructureDan Williams
2022-12-03cxl/port: Limit the port driver to just the HDM Decoder CapabilityDan Williams
2022-12-03cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams
2022-12-03cxl/pci: Kill cxl_map_regs()Dan Williams
2022-12-03cxl/pci: Cleanup cxl_map_device_regs()Dan Williams
2022-12-03cxl/pci: Cleanup repeated code in cxl_probe_regs() helpersDan Williams
2022-12-03cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter
2022-12-03cxl/region: Manage CPU caches relative to DPA invalidation eventsDan Williams
2022-12-02cxl/pmem: Enforce keyctl ABI for PMEM securityDan Williams
2022-12-02cxl/region: Fix missing probe failureDan Williams
2022-12-02cxl: add dimm_id support for __nvdimm_create()Dave Jiang
2022-12-02cxl/ACPI: Register CXL host ports by bridge deviceRobert Richter
2022-12-02tools/testing/cxl: Make mock CEDT parsing more robustDan Williams