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path: root/drivers/clk/samsung
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2024-12-14clk: samsung: Introduce Exynos990 clock controller driverIgor Belwon
The current implementation contains support for: - CMU_TOP - which generates clocks for other blocks - CMU_HSI0 - which generates clocks for USB31. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241209-exynos990-cmu-v4-3-57f07080f9e4@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-14clk: samsung: clk-pll: Add support for pll_{0717x, 0718x, 0732x}Igor Belwon
These PLLs are found in the Exynos990 SoC. The PLLs are similar to pll0822x. pll0717x and pll0718x are an exception, and they use the mdiv mask from 1718X (that is, one bit smaller). Apart from that, the masks/shifts are identical to those of 0822x. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241209-exynos990-cmu-v4-2-57f07080f9e4@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-26clk: samsung: Introduce Exynos8895 clock driverIvaylo Ivanov
CMU_TOP is the top level clock management unit which contains PLLs, muxes, dividers and gates that feed the other clock management units. CMU_PERIS provides clocks for GIC and MCT CMU_FSYS0 provides clocks for USBDRD30 CMU_FSYS1 provides clocks for MMC, UFS and PCIE CMU_PERIC0 provides clocks for UART_DBG, USI00 ~ USI03 CMU_PERIC1 provides clocks for SPI_CAM0/1, UART_BT, USI04 ~ USI13, HSI2C_CAM0/1/2/3 Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20241023090136.537395-4-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-26clk: samsung: clk-pll: Add support for pll_{1051x,1052x}Ivaylo Ivanov
These plls are found in the Exynos8895 SoC: - pll1051x: Integer PLL with middle frequency - pll1052x: Integer PLL with low frequency The PLLs are similar enough to pll_0822x, so the same code can handle all. Locktime for 1051x, 1052x is 150 - the same as the pll_0822x lock factor. MDIV, SDIV, PDIV masks and bit shifts are also the same as 0822x. When defining a PLL, the "con" parameter should be set to CON0 register, like this: PLL(pll_1051x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, pll_shared0_rate_table), Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20241023090136.537395-3-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-21clk: samsung: gs101: make all ufs related clocks criticalPeter Griffin
Enabling UFSHCD_CAP_HIBERN8_WITH_CLK_GATING in the UFS driver means all UFS clocks are gated/ungated, which leads to the UFS IP getting into a bad state and being completely non functional. Downstream these clocks are all left in Automatic Clock Gate (ACG) mode, and are not exposed to the UFS driver in DT. Enabling ACG is ultimately what we need to do in the upstream Samsung clock driver as well. However until ACG is enabled upstream, we mark these clocks as critical to avoid them being disabled. This then allow us to enable UFSHCD_CAP_HIBERN8_WITH_CLK_GATING and have UFS hibern8. Whilst this may seem at first glance a strange thing to do, the clocks between UFS host and UFS device are still gated after this change, and enabling UFS hibern8 leads to substantially cooler device when running the upstream kernel on a Pixel 6 phone. This change only effects the clocks from the CMU to the UFS IP. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20241018130215.487425-1-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-10clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock supportSunyeal Hong
Register compatible and cmu_info data to support clocks. CMU_PERIC1, this provides clocks for USI09 ~ USI17, USI_I2C and USI_I3C. CMU_MISC, this provides clocks for MISC, GIC and OTP. CMU_HSI0, this provides clocks for PCIE. CMU_HSI1, this provides clocks for USB and MMC. Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> Link: https://lore.kernel.org/r/20241009042110.2379903-3-sunyeal.hong@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-10Merge tag 'samsung-clk-fixes-6.12' into next/clkKrzysztof Kozlowski
Samsung clock controller fixes for v6.12 Add missing sentinel in of_device_id table, so the code iterating over it will not go over the size of an array. Further code depends on the fixes branch.
2024-09-30clk: samsung: Fix out-of-bound access of of_match_node()Jinjie Ruan
Currently, there is no terminator entry for exynosautov920_cmu_of_match, hence facing below KASAN warning, BUG: KASAN: global-out-of-bounds in of_match_node+0x120/0x13c Read of size 1 at addr ffffffe31cc9e628 by task swapper/0/1 CPU: 1 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.11.0+ #334 Hardware name: linux,dummy-virt (DT) Call trace: dump_backtrace+0x94/0xec show_stack+0x18/0x24 dump_stack_lvl+0x90/0xd0 print_report+0x1f4/0x5b4 kasan_report+0xc8/0x110 __asan_report_load1_noabort+0x20/0x2c of_match_node+0x120/0x13c of_match_device+0x70/0xb4 platform_match+0xa0/0x25c __device_attach_driver+0x7c/0x2d4 bus_for_each_drv+0x100/0x188 __device_attach+0x174/0x364 device_initial_probe+0x14/0x20 bus_probe_device+0x128/0x158 device_add+0xb3c/0x10fc of_device_add+0xdc/0x150 of_platform_device_create_pdata+0x120/0x20c of_platform_bus_create+0x2bc/0x620 of_platform_populate+0x58/0x108 of_platform_default_populate_init+0x100/0x120 do_one_initcall+0x110/0x788 kernel_init_freeable+0x44c/0x61c kernel_init+0x24/0x1e4 ret_from_fork+0x10/0x20 The buggy address belongs to the variable: exynosautov920_cmu_of_match+0xc8/0x2c80 Add a dummy terminator entry at the end to assist of_match_node() in traversing up to the terminator entry without accessing an out-of-boundary index. Fixes: 485e13fe2fb6 ("clk: samsung: add top clock support for ExynosAuto v920 SoC") Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20240927102104.3268790-1-ruanjinjie@huawei.com [krzk: drop trailing comma] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-09-30clk: samsung: fsd: do not define number of clocks in bindingsInbaraj E
Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Signed-off-by: Inbaraj E <inbaraj.e@samsung.com> Link: https://lore.kernel.org/r/20240917094355.37887-2-inbaraj.e@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-09-30clk: samsung: Fix errors reported by checkpatchVarada Pavani
Fix checkpatch errors from clock drivers. ERROR: space prohibited before that ',' ERROR: space required after that ',' Signed-off-by: Varada Pavani <v.pavani@samsung.com> Link: https://lore.kernel.org/r/20240926145132.1763-3-v.pavani@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-09-30clk: samsung: Fix block comment style warnings reported by checkpatchVarada Pavani
Fix checkpatch giving warnings on driver files related to comment style. WARNING: Block comments should align the * on each line which is Signed-off-by: Varada Pavani <v.pavani@samsung.com> Link: https://lore.kernel.org/r/20240926145132.1763-2-v.pavani@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-09-21clk: Switch back to struct platform_driver::remove()Uwe Kleine-König
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all clk drivers to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20240909144026.870565-2-u.kleine-koenig@baylibre.com Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-08-23clk: samsung: add top clock support for ExynosAuto v920 SoCSunyeal Hong
This adds support for CMU_TOP which generates clocks for all the function blocks such as CORE, HSI0/1/2, PERIC0/1 and so on. For CMU_TOP, PLL_SHARED0,1,2,3,4 and 5 will be the sources of this block and they will generate bus clocks. Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> Link: https://lore.kernel.org/r/20240821232652.1077701-5-sunyeal.hong@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-23clk: samsung: clk-pll: Add support for pll_531xSunyeal Hong
pll531x PLL is used in Exynos Auto v920 SoC for shared pll. pll531x: Integer/fractional PLL with mid frequency FVCO (800 to 3120 MHz) PLL531x FOUT = (MDIV x FIN)/(PDIV x 2^SDIV) for integer PLL FOUT = (MDIV + F/2^32-F[31]) x FIN/(PDIV x 2^SDIV) for fractional PLL Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20240821232652.1077701-4-sunyeal.hong@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-21clk: samsung: exynos7885: Add USB related clocks to CMU_FSYSDavid Virag
Exynos7885 SoC has a DWC3 USB Controller with Exynos USB PHY which in theory supports USB3 SuperSpeed, but is only used as USB2 in all known devices. These clocks are needed for everything related to USB. While at it, also remove the CLK_SET_RATE_PARENT capability of CLK_MOUT_FSYS_USB30DRD_USER, since it's not actually needed. Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20240816175034.769628-3-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-21clk: samsung: clk-pll: Add support for pll_1418xDavid Virag
pll1418x is used in Exynos7885 SoC for USB PHY clock. Operation-wise it is very similar to pll0822x, except that MDIV is only 9 bits wide instead of 10, and we use the CON1 register in the PLL macro's "con" parameter instead of CON3 like this: PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk", PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB, pll_usb_rate_table), Technically the PLL should work fine with pll0822x code if the PLL tables are correct, but it's more "correct" to actually update the mask. Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20240816175034.769628-2-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-11clk: samsung: exynosautov9: add dpum clock supportKwanghoon Son
Add dpum clock for exynosautov9. Signed-off-by: Kwanghoon Son <k.son@samsung.com> Link: https://lore.kernel.org/r/20240809-clk_dpum-v3-3-359decc30fe2@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-08clk: samsung: exynos7885: Add missing MUX clocks from PLLs in CMU_TOPDavid Virag
In Exynos7885 (and seemingly all modern Exynos SoCs) all PLLs have a MUX attached to them controlled by bit 4 in the PLL's CON0 register. These MUXes can select between OSCCLK or the PLL's output, essentially making the PLL bypassable. These weren't modeled in the driver because the vendor provided drivers didn't model it properly, instead setting them when updating the PMS values. Not having them modeled didn't cause any problems in this case, since these MUXes were set to the PLL's output by default, but this is not the case everywhere in this SoC. Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20240806121157.479212-6-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-08clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fixDavid Virag
Update CLKS_NR_FSYS to the proper value after a fix in DT bindings. This should always be the last clock in a CMU + 1. Fixes: cd268e309c29 ("dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS") Cc: stable@vger.kernel.org Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20240806121157.479212-5-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-07-31clk: samsung: exynos850: Add TMU clockSam Protsenko
Add TMU PCLK clock in CMU_PERI unit. It acts simultaneously as an interface clock (to access TMU registers) and an operating clock which makes TMU IP-core functional. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240723163311.28654-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-07-23clk: samsung: fix getting Exynos4 fin_pll rate from external clocksKrzysztof Kozlowski
Commit 0dc83ad8bfc9 ("clk: samsung: Don't register clkdev lookup for the fixed rate clocks") claimed registering clkdev lookup is not necessary anymore, but that was not entirely true: Exynos4210/4212/4412 clock code still relied on it to get the clock rate of xxti or xusbxti external clocks. Drop that requirement by accessing already registered clk_hw when looking up the xxti/xusbxti rate. Reported-by: Artur Weber <aweber.kernel@gmail.com> Closes: https://lore.kernel.org/all/6227c1fb-d769-462a-b79b-abcc15d3db8e@gmail.com/ Fixes: 0dc83ad8bfc9 ("clk: samsung: Don't register clkdev lookup for the fixed rate clocks") Cc: <stable@vger.kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240722063309.60054-1-krzysztof.kozlowski@linaro.org Tested-by: Artur Weber <aweber.kernel@gmail.com> # Exynos4212 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-07-01clk: samsung: gs101: mark gout_hsi2_ufs_embd_i_clk_unipro as criticalPeter Griffin
The system hangs on poweroff when this UFS clock is turned off, meaning the system never powers down. For the moment mark the clock as critical. Reviewed-by: Will McVicker <willmcvicker@google.com> Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240628223506.1237523-5-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-06-16clk: samsung: Switch to use kmemdup_array()Andy Shevchenko
Let the kememdup_array() take care about multiplication and possible overflows. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20240606161028.2986587-4-andriy.shevchenko@linux.intel.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-05-27clk: samsung: exynos-clkout: Remove misleading ↵Marek Szyprowski
of_match_table/MODULE_DEVICE_TABLE Since commit 9484f2cb8332 ("clk: samsung: exynos-clkout: convert to module driver") this driver is instantiated as MFD-cell (matched by platform device name) not as a real platform device created by OF code. Remove then of_match_table and change related MODULE_DEVICE_TABLE to simple MODULE_ALIAS to avoid further confusion. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20240510070653.537089-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-05-18Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "I'm actually surprised this time. There aren't any new Qualcomm SoC clk drivers. And there's zero diff in the core clk framework. Instead we have new clk drivers for STM and Sophgo, with Samsung^WGoogle in third for the diffstat because they introduced HSI0 and HSI2 clk drivers for Google's GS101 SoC (high speed interface things like PCIe, UFS, and MMC). Beyond those big diffs there's the usual updates to various clk drivers for incorrect parent descriptions or mising MODULE_DEVICE_TABLE()s, etc. Nothing in particular stands out as super interesting here. New Drivers: - STM32MP257 SoC clk driver - Airoha EN7581 SoC clk driver - Sophgo CV1800B, CV1812H and SG2000 SoC clk driver - Loongson-2k0500 and Loongson-2k2000 SoC clk driver - Add HSI0 and HSI2 clock controllers for Google GS101 - Add i.MX95 BLK CTL clock driver Updates: - Allocate clk_ops dynamically for SCMI clk driver - Add support in qcom RCG and RCG2 for multiple configurations for the same frequency - Use above support for IPQ8074 NSS port 5 and 6 clocks to resolve issues - Fix the Qualcomm APSS IPQ5018 PLL to fix boot failures of some boards - Cleanups and fixes for Qualcomm Stromer PLLs - Reduce max CPU frequency on Qualcomm APSS IPQ5018 - Fix Kconfig dependencies of Qualcomm SM8650 GPU and SC8280XP camera clk drivers - Make Qualcomm MSM8998 Venus clocks functional - Cleanup downstream remnants related to DisplayPort across Qualcomm SM8450, SM6350, SM8550, and SM8650 - Reuse the Huayra APSS register map on Qualcomm MSM8996 CBF PLL - Use a specific Qualcomm QCS404 compatible for the otherwise generic HFPLL - Remove Qualcomm SM8150 CPUSS AHB clk as it is unused - Remove an unused field in the Qualcomm RPM clk driver - Add missing MODULE_DEVICE_TABLE to Qualcomm MSM8917 and MSM8953 global clock controller drivers - Allow choice of manual or firmware-driven control over PLLs, needed to fully implement CPU clock controllers on Exynos850 - Correct PLL clock IDs on ExynosAutov9 - Propagate certain clock rates to allow setting proper SPI clock rates on Google GS101 - Mark certain Google GS101 clocks critical - Convert old S3C64xx clock controller bindings to DT schema - Add new PLL rate and missing mux on Rockchip rk3568 - Add missing reset line on Rockchip rk3588 - Removal of an unused field in struct rockchip_mmc_clock - Amlogic s4/a1: add regmap maximum register for proper debugfs dump - Amlogic s4: add MODULE_DEVICE_TABLE() on pll and periph controllers - Amlogic pll driver: print clock name on lock error to help debug - Amlogic vclk: finish dsi clock path support - Amlogic license: fix occurence "GPL v2" as reported by checkpatch - Add PM runtime support to i.MX8MP Audiomix - Add DT schema for i.MX95 Display Master Block Control - Convert to platform remove callback returning void for i.MX8MP Audiomix - Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on Renesas R-Car V4M - Add interrupt controller (PLIC) clock and reset on Renesas RZ/Five - Prepare power domain support for Renesas RZ/G2L family members, and add actual support on Renesas RZ/G3S SoC - Add thermal, serial (SCIF), and timer (CMT/TMU) clocks on Renesas R-Car V4M - Add additional constraints to Allwinner A64 PLL MIPI clock - Fix autoloading sunxi-ng clocks when build as a module" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (118 commits) clk: samsung: Don't register clkdev lookup for the fixed rate clocks clk, reset: microchip: mpfs: fix incorrect preprocessor conditions clk: qcom: clk-alpha-pll: fix rate setting for Stromer PLLs clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018 clk: qcom: Fix SM_GPUCC_8650 dependencies clk: qcom: Fix SC_CAMCC_8280XP dependencies dt-bindings: clocks: stm32mp25: add access-controllers description clock, reset: microchip: move all mpfs reset code to the reset subsystem clk: samsung: gs101: drop unused HSI2 clock parent data clk: rockchip: rk3568: Add PLL rate for 724 MHz clk: rockchip: Remove an unused field in struct rockchip_mmc_clock dt-bindings: clock: fixed: Define a preferred node name clk: meson: s4: fix module autoloading clk: samsung: gs101: mark some apm UASC and XIU clocks critical clk: imx: imx8mp: Convert to platform remove callback returning void clk: imx: imx8mp: Switch to RUNTIME_PM_OPS() clk: bcm: rpi: Assign ->num before accessing ->hws clk: bcm: dvp: Assign ->num before accessing ->hws clk: samsung: gs101: add support for cmu_hsi2 clk: samsung: gs101: add support for cmu_hsi0 ...
2024-05-14clk: samsung: Don't register clkdev lookup for the fixed rate clocksMarek Szyprowski
Commit 4d11c62ca8d7 ("clkdev: report over-sized strings when creating clkdev entries") revealed that clock lookup is registered for all fixed clocks. The mentioned commit added a check if the registered name is not too long. This fails for some clocks registered for Exynos542x SoCs family. This lookup is a left-over from early common clock framework days, not really needed nowadays, so remove it to avoid further issues. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Tested-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240510065901.535124-1-m.szyprowski@samsung.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-05-07clk: samsung: gs101: drop unused HSI2 clock parent dataKrzysztof Kozlowski
Drop static const arrays with HSI2 clocks parent data which are not referenced by any clock. This might cause -Werror=unused-const-variable warnings. Reported-by: Stephen Boyd <sboyd@kernel.org> Closes: https://lore.kernel.org/all/8bf65df598680f0785c3d6db70acfb9a.sboyd@kernel.org/ Fixes: 093c290084a4 ("clk: samsung: gs101: add support for cmu_hsi2") Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240507055948.34554-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-05-03clk: samsung: gs101: mark some apm UASC and XIU clocks criticalAndré Draszik
The system hangs when any of these clocks are turned off. With the introduction of pinctrl clock support [1], the approach taken in this clock driver for the APM clocks to rely solely on the clk_ignore_unused kernel command line option does not work anymore and the system hangs during boot. gout_apm_func is a parent clock to the clocks that are going to be handled by the pinctrl driver [2], namely gout_apm_apbif_gpio_alive_pclk and gout_apm_apbif_gpio_far_alive_pclk. It also is the parent to the clocks marked as critical in this commit here (and some others that aren't relevant for this commit)). This means that once the pinctrl driver decides to turn off clocks, the clock framework will subsequently turn off parent clocks of those pinctrl clocks if they have no (apparent) user. Since gout_apm_func is the parent, and since no drivers are hooked up to it or any of its other children, gout_apm_func will be turned off. This will cause the system to hang, as the clocks marked as critical in this commit stop having an input. We might have to add a driver for these clocks, but in the meantime let's just ensure they stay on even if siblings are turned off. For the avoidance of doubt: This commit doesn't mean that we can boot without clk_ignore_unused. Link: https://lore.kernel.org/r/20240426-samsung-pinctrl-busclock-v3-0-adb8664b8a7e@linaro.org [1] Link: https://lore.kernel.org/r/20240429-samsung-pinctrl-busclock-dts-v1-0-5e935179f3ca@linaro.org [2] Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240430-gs101-apm-clocks-v1-1-b2e2335e84f5@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-30clk: samsung: Revert "clk: Use device_get_match_data()"Marek Szyprowski
device_get_match_data() function should not be used on the device other than the one matched to the given driver, because it always returns the match_data of the matched driver. In case of exynos-clkout driver, the original code matches the OF IDs on the PARENT device, so replacing it with of_device_get_match_data() broke the driver. This has been already pointed once in commit 2bc5febd05ab ("clk: samsung: Revert "clk: samsung: exynos-clkout: Use of_device_get_match_data()""). To avoid further confusion, add a comment about this special case, which requires direct of_match_device() call to pass custom IDs array. This partially reverts commit 409c39ec92a35e3708f5b5798c78eae78512cd71. Cc: <stable@vger.kernel.org> Fixes: 409c39ec92a3 ("clk: Use device_get_match_data()") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20240425075628.838497-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240430184656.357805-1-krzysztof.kozlowski@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-29clk: samsung: gs101: add support for cmu_hsi2Peter Griffin
CMU_HSI2 is the clock management unit used for the hsi2 block. HSI stands for High Speed Interface and as such it generates clocks for PCIe, UFS and MMC card. This patch adds support for the muxes, dividers, and gates in cmu_hsi2. The following clocks are marked CLK_IS_CRITICAL as disabling them results in an immediate system hang. CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK The following clocks are marked CLK_IGNORE_UNUSED as they are needed for UFS to be functional. CLK_GOUT_HSI2_SSMT_HSI2_ACLK CLK_GOUT_HSI2_SSMT_HSI2_PCLK CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2 CLK_GOUT_HSI2_XIU_D_HSI2_ACLK CLK_GOUT_HSI2_XIU_P_HSI2_ACLK CLK_GOUT_HSI2_GPIO_HSI2_PCLK is marked CLK_IGNORE_UNUSED until the exynos pinctrl clock patches land then it can be removed. Some clocks in this unit have very long names. To help with this the clock name mangling strategy was updated to include removing the following sub-strings. - G4X2_DWC_PCIE_CTL_ - G4X1_DWC_PCIE_CTL_ - PCIE_SUB_CTRL_ - INST_0_ - LN05LPE_ - TM_WRAPPER_ - SF_ Signed-off-by: Peter Griffin <peter.griffin@linaro.org> [AD: resolve merge conflicts] Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240429-hsi0-gs101-v3-3-f233be0a2455@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-29clk: samsung: gs101: add support for cmu_hsi0André Draszik
CMU_HSI0 is the clock management unit for one of the high speed interfaces, which is used (amongst others) for USB Some notes about the clocks marked as CLK_IGNORE_UNUSED: * CLK_GOUT_HSI0_PCLK CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK CLK_GOUT_HSI0_XIU_P_HSI0_ACLK need to be kept running as otherwise the system becomes unresponsive and it doesn't complete booting. * CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK CLK_GOUT_HSI0_SSMT_USB_ACLK CLK_GOUT_HSI0_SSMT_USB_PCLK CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2 CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK are needed for USB to come up properly (SSMT is for (secure) memory tagging). While at the moment we only support booting with the clk_ignore_unused kernel command line paramenter, it's still worthwhile to explicitly mark those clocks. While the usual (sed) script has been used to derive the linux clock names from the data sheet, one manual tweak was applied to fix a typo coming from the data sheet which we don't want to carry: hsi0_uspdpdbg_user -> hsi0_usbdpdbg_user (note usb vs usp). Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240426-hsi0-gs101-v2-4-2157da8b63e3@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-22clk: samsung: gs101: propagate PERIC1 USI SPI clock rateTudor Ambarus
When SPI transfer is being prepared, the spi-s3c64xx driver will call clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK is a gate (leaf) clock, so it must propagate the rate change up the clock tree, so that corresponding MUX/DIV clocks can actually change their values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for all USI instances in GS101 PERIC1: USI{0, 9, 10, 11, 12, 13}. This change involves the following clocks: PERIC1 USI*: Clock Div range MUX Selection ------------------------------------------------------------------- gout_peric1_peric1_top0_ipclk_* - - dout_peric1_usi*_usi /1..16 - mout_peric1_usi*_usi_user - {24.5 MHz, 400 MHz} With input clock of 400 MHz this scheme provides the following IPCLK rate range, for each USI block: PERIC1 USI*: 1.5 MHz ... 400 MHz Accounting for internal /4 divider in SPI blocks, and because the max SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates: PERIC1 USI_SPI*: 384 KHz ... 49.9 MHz Which shall be fine for the applications of the SPI bus. Note that with this we allow the reparenting of the MUX_USIx clocks to OSCCLK. Each instance of the USI IP has its own MUX_USI clock, thus the reparenting of a MUX_USI clock corresponds to a single instance of the USI IP. The datasheet mentions OSCCLK just in the low-power mode context, but the downstream driver reparents too the MUX_USI clocks to OSCCLK. Follow the downstream driver and do the same. Fixes: 2999e786d7e9 ("clk: samsung: gs101: add support for cmu_peric1") Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240419100915.2168573-3-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-22clk: samsung: gs101: propagate PERIC0 USI SPI clock rateTudor Ambarus
Introduce nMUX() for MUX clocks that can be reparented on clock rate change. "nMUX" comes from "n-to-1 selector", hopefully emphasising that the selector can change on clock rate changes. Ideally MUX/MUX_F() should change to not have the CLK_SET_RATE_NO_REPARENT flag set by default, and all their users to be updated to add the flag back (like in the case of DIV and GATE). But this is a very intrusive change and because for now only GS101 allows MUX reparenting on clock rate change, stick with nMUX(). GS101 defines MUX clocks that are dedicated for each instance of the IP. One example is USI IP (SPI, I2C, serial). The reparenting of these MUX clocks will not affect other instances of the same IP or different IPs altogether. When SPI transfer is being prepared, the spi-s3c64xx driver will call clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK is a gate (leaf) clock, so it must propagate the rate change up the clock tree, so that corresponding MUX/DIV clocks can actually change their values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for all USI instances in GS101 PERIC0: USI{1-8, 14}. This change involves the following clocks: PERIC0 USI*: Clock Div range MUX Selection ------------------------------------------------------------------- gout_peric0_peric0_top0_ipclk_* - - dout_peric0_usi*_usi /1..16 - mout_peric0_usi*_usi_user - {24.5 MHz, 400 MHz} With input clock of 400 MHz this scheme provides the following IPCLK rate range, for each USI block: PERIC0 USI*: 1.5 MHz ... 400 MHz Accounting for internal /4 divider in SPI blocks, and because the max SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates: PERIC0 USI_SPI*: 384 KHz ... 49.9 MHz Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0") Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240419100915.2168573-2-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-31clk: samsung: exynosautov9: fix wrong pll clock id valueJaewon Kim
All PLL id values of CMU_TOP were incorrectly set to FOUT_SHARED0_PLL. It modified to the correct PLL clock id value. Fixes: 6587c62f69dc ("clk: samsung: add top clock support for Exynos Auto v9 SoC") Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240328091000.17660-1-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-26clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1Sam Protsenko
Implement support for CPU clock management units: - CMU_CPUCL0: clocks for cluster 0: 4 x Cortex-A55 (cpu0..cpu3) - CMU_CPUCL1: clocks for cluster 1: 4 x Cortex-A55 (cpu4..cpu7) CPU PLLs are generating main CPU clocks for each cluster, and there are alternate ("switch") clocks that can be used temporarily while re-configuring the PLL for a new rate. ACLK, ATCLK, PCLKDBG and PERIPHCLK clocks are driving corresponding buses. CLK_CLUSTERx_SCLK are actual leaf CPU clocks and should be used to change CPU rates. Also some CoreSight clocks can be derived from DBG_USER (debug clock). PLL table was extracted from ECT table. ECT stands for "Exynos Characteristic Table", it's a Samsung specific binary data populated by BL2 bootloader in RAM at 0x90000000 address, containing PLL tables for various CMUs and other hardware specific information. The particular PLL type used in CMU_CPUCL0 and CMU_CPUCL1 (pll0822x) is an integer PLL with middle FVCO. The equation to calculate its output rate is: fout = fin * M / (P*2^S) where: fin = 26 MHz (OSCCLK frequency) M = 64..1023 P = 1..63 S = 0..6 The PLL table tries to keep "P" value low to reduce the locking time, which for pll0822x is "t = P * 150" (in OSCCLK cycles). Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240301015118.30072-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-26clk: samsung: Implement manual PLL control for ARM64 SoCsSam Protsenko
Some ARM64 Exynos chips are capable to control PLL clocks automatically. For those chips, whether the PLL is controlled automatically or manually is chosen in PLL_CON1 register with next bits: [28] ENABLE_AUTOMATIC_CLKGATING [1] MANUAL_PLL_CTRL [0] AUTO_PLL_CTRL The bl2 bootloader sets 0x10000001 value for some PLL_CON1 registers, which means any attempt to control those PLLs manually (e.g. disabling/enabling those PLLs or changing MUX parent clocks) would lead to PLL lock timeout with error message like this: Could not lock PLL ... At the moment, all Samsung clock drivers implement manual clock control. So in order to make it possible to control PLLs, corresponding PLL_CON1 registers should be set to 0x2 first. Some older ARM64 chips don't implement the automatic clock control though. It also might be desirable to configure some PLLs for manual control, while keeping the default configuration for the rest. So it'd convenient to choose this PLL mode for each CMU separately. Introduce .manual_plls field to CMU structure to choose the PLL control mode. Because it'll be initialized with "false" in all existing CMU structures by default, it won't affect any existing clock drivers, allowing for this feature to be enabled gradually when it's needed with no change for the rest of users. In case .manual_plls is set, set PLL_CON1 registers to manual control, akin to what's already done for gate clocks in exynos_arm64_init_clocks(). Of course, PLL_CON1 registers should be added to corresponding struct samsung_cmu_info::clk_regs array to make sure they get initialized. No functional change. This patch adds a feature, but doesn't enable it for any users. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240301015118.30072-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Add CPU clock support for Exynos850Sam Protsenko
Implement CPU clock control for Exynos850 SoC. It follows the same procedure which is already implemented for other SoCs in clk-cpu.c: 1. Set the correct rate for the alternate parent (if needed) before switching to use it as the CPU clock 2. Switch to the alternate parent, so the CPU continues to get clocked while the PLL is being re-configured 3. Adjust the dividers for the CPU related buses (ACLK, ATCLK, etc) 4. Re-configure the PLL for the new CPU clock rate. It's done automatically, as the CPU clock rate change propagates to the PLL clock, because the CPU clock has CLK_SET_RATE_PARENT flag set in exynos_register_cpu_clock() 5. Once the PLL is locked, set it back as the CPU clock source 6. Set alternate parent clock rate back to max speed As in already existing clk-cpu.c code, the divider and mux clocks are configured in a low-level fashion (using direct register access instead of CCF API), to avoid affecting how DIV and MUX clock flags are declared in the actual clock driver (clk-exynos850.c). No functional change. This patch adds support for Exynos850 CPU clock, but doesn't enable it per se. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-13-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Pass mask to wait_until_mux_stable()Sam Protsenko
Make it possible to use wait_until_mux_stable() for MUX registers where the mask is different from MUX_MASK (e.g. in upcoming CPU clock implementation for Exynos850). No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-12-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Keep register offsets in chip specific structureSam Protsenko
Abstract CPU clock registers by keeping their offsets in a dedicated chip specific structure to accommodate for oncoming Exynos850 support, which has different offsets for cluster 0 and cluster 1. This rework also makes it possible to use exynos_set_safe_div() for all chips, so exynos5433_set_safe_div() is removed here to reduce the code duplication. The ".regs" field has to be (void *) as different Exynos chips can have very different register layout, so this way it's possible for ".regs" to point to different structures, each representing its own chip's layout. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-11-semen.protsenko@linaro.org [krzysztof: drop redundant const for regs in exynos_cpuclk_chip] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Keep CPU clock chip specific data in a dedicated structSam Protsenko
Keep chip specific data in the data structure, don't mix it with code. It makes it easier to add more chip specific data further. Having all chip specific data in the table eliminates possible code bloat when adding more rate handlers for new chips, and also makes it possible to keep some other chip related data in that array. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-10-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Pass register layout type explicitly to CLK_CPU()Sam Protsenko
Use a dedicated enum field to explicitly specify which register layout should be used for the CPU clock, instead of passing it as a bit flag. This way it would be possible to keep the chip-specific data in some array, where each chip structure could be accessed by its corresponding layout index. It prepares clk-cpu.c for adding new chips support, which might have different data for different CPU clusters. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-9-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Pass actual CPU clock registers base to CPU_CLK()Sam Protsenko
The documentation for struct exynos_cpuclk says .ctrl_base field should contain the controller base address. There are two different problems with that: 1. All Exynos clock drivers are actually passing CPU_SRC register offset via CPU_CLK() macro, which in turn gets assigned to mentioned .ctrl_base field. Because CPU_SRC register usually already has 0x200 offset from controller's base, all other register offsets in clk-cpu.c (like DIVs and MUXes) are specified as offsets from CPU_SRC offset, and not from controller's base. That makes things confusing and inconsistent with register offsets provided in Exynos clock drivers, also breaking the contract for .ctrl_base field as described in struct exynos_cpuclk doc. 2. Furthermore, some Exynos chips have an additional offset for the start of CPU clock registers block (inside of the CMU). There might be different reasons for that, e.g.: - The CMU contains clocks for two different CPUs (like in Exynos5420) - The CMU contains also non-CPU clocks as well (like in Exynos4) - The CPU CMU exists as a dedicated hardware block in the SoC layout, but is modelled as a part of bigger CMU in the driver (like in case of Exynos3250) That means the .ctrl_base field is actually not a controller's base, but instead it's a start address of the CPU clock registers inside of the CMU. Rework all register offsets in clk-cpu.c to be actual offsets from the CPU clock register block start, and fix offsets provided to CPU_CLK() macro in all Exynos clock drivers. Also clarify the .ctrl_base field documentation and rename it to just .base, because it doesn't really contain the CMU base. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-8-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Group CPU clock functions by chipSam Protsenko
clk-cpu.c is going to get messy as new chips support is added. Restructure the code by pulling related functions and definitions together, grouping those by their relation to a particular chip or other categories, to simplify the code navigation. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-7-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Use single CPU clock notifier callback for all chipsSam Protsenko
Reduce the code duplication by making all chips use a single version of exynos_cpuclk_notifier_cb() function. That will prevent the code bloat when adding new chips support too. Also don't pass base address to pre/post rate change functions, as it can be easily derived from already passed cpuclk param. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-6-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Reduce params count in exynos_register_cpu_clock()Sam Protsenko
Pass CPU clock data structure to exynos_register_cpu_clock() instead of passing its fields separately there. That simplifies the signature of exynos_register_cpu_clock() and makes it easier to add more fields to struct samsung_cpu_clock later. This style follows the example of samsung_clk_register_pll(). No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-5-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Pull struct exynos_cpuclk into clk-cpu.cSam Protsenko
Reduce the scope of struct exynos_cpuclk, as it's only used in clk-cpu.c internally. All drivers using clk-pll.h already include clk.h as well, so this change doesn't break anything. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-4-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Improve clk-cpu.c styleSam Protsenko
clk-cpu.c has numerous style issues reported by checkpatch and easily identified otherwise. Give it some love and fix those warnings where it makes sense. Also make stabilization time a named constant to get rid of the magic number in clk-cpu.c. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-3-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-07clk: samsung: gs101: add support for cmu_peric1André Draszik
CMU_PERIC1 is the clock management unit used for the peric1 block which is used for additional USI, I3C and PWM interfaces/busses. Add support for muxes, dividers and gates of cmu_peric1, except for CLK_GOUT_PERIC1_IP which isn't well described in the datasheet and which downstream also ignores (similar to cmu_peric0). Two clocks have been marked as CLK_IS_CRITICAL for the following reason: * disabling them makes it impossible to access any peric1 registers, (including those two registers). * disabling gout_peric1_lhm_axi_p_peric1_i_clk sometimes has the additional effect of making the whole system unresponsive. One clock marked as CLK_IGNORE_UNUSED needs to be kept on until we have updated the respective driver for the following reason: * gout_peric1_gpio_peric1_pclk is required by the pinctrl configuration. With this clock disabled, reconfiguring the pins (for USI/I2C, USI/UART) will hang during register access. Since pinctrl-samsung doesn't support a clock at the moment, we just keep the kernel from disabling it at boot, until we have an update for pinctrl-samsung, at which point we'll drop the flag. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240201161258.1013664-4-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-07clk: samsung: gs101: drop extra empty lineAndré Draszik
There is an extra empty line here which doesn't exist in any of the other cmu code blocks in this file. Drop it to align cmu_top with the rest of the file. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240201161258.1013664-2-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-01clk: samsung: exynos850: Propagate SPI IPCLK rate changeSam Protsenko
When SPI transfer is being prepared, the spi-s3c64xx driver will call clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK is a gate (leaf) clock, so it must propagate the rate change up the clock tree, so that corresponding DIV clocks can actually change their divider values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for all SPI instances in Exynos850 (spi_0, spi_1 and spi_2) to make it possible. This change involves next clocks: usi_spi_0: Clock Block Div range -------------------------------------------- gout_spi0_ipclk CMU_PERI - dout_peri_spi0 CMU_PERI /1..32 mout_peri_spi_user CMU_PERI - dout_peri_ip CMU_TOP /1..16 usi_cmgp0: Clock Block Div range -------------------------------------------- gout_cmgp_usi0_ipclk CMU_CMGP - dout_cmgp_usi0 CMU_CMGP /1..32 mout_cmgp_usi0 CMU_CMGP - gout_clkcmu_cmgp_bus CMU_APM - dout_apm_bus CMU_APM /1..8 usi_cmgp1: Clock Block Div range -------------------------------------------- gout_cmgp_usi1_ipclk CMU_CMGP - dout_cmgp_usi1 CMU_CMGP /1..32 mout_cmgp_usi1 CMU_CMGP - gout_clkcmu_cmgp_bus CMU_APM - dout_apm_bus CMU_APM /1..8 With input clock of 400 MHz, this scheme provides next IPCLK rate range, for each SPI block: SPI0: 781 kHz ... 400 MHz SPI1/2: 1.6 MHz ... 400 MHz Accounting for internal /4 divider in SPI blocks, and because the max SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates: SPI0: 200 kHz ... 49.9 MHz SPI1/2: 400 kHz ... 49.9 MHz Which should cover all possible applications of SPI bus. Of course, setting SPI frequency to values as low as 500 kHz will also affect the common bus dividers (dout_apm_bus or dout_peri_ip), which in turn effectively lowers the rates for all leaf bus clocks derived from those dividers, like HSI2C and I3C clocks. But at least it gives the board designer a choice, whether to keep all clocks (SPI/HSI2C/I3C) at high frequencies, or make all those clocks have lower frequencies. Not propagating the rate change to those common dividers would limit this choice to "only high frequencies are allowed for SPI/HSI2C/I3C" option, making the common dividers useless. This decision follows the "Worse is better" approach, relying on the users/engineers to know the system internals when working with such low-level features, instead of trying to account for all possible use-cases. Fixes: 7dd05578198b ("clk: samsung: Introduce Exynos850 clock driver") Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240125013858.3986-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>